1 /* 2 * Ralink RT3662/RT3883 SoC PCI support 3 * 4 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org> 5 * 6 * Parts of this file are based on Ralink's 2.6.21 BSP 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published 10 * by the Free Software Foundation. 11 */ 12 13 #include <linux/types.h> 14 #include <linux/pci.h> 15 #include <linux/io.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/of.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_pci.h> 22 #include <linux/platform_device.h> 23 24 #include <asm/mach-ralink/rt3883.h> 25 #include <asm/mach-ralink/ralink_regs.h> 26 27 #define RT3883_MEMORY_BASE 0x00000000 28 #define RT3883_MEMORY_SIZE 0x02000000 29 30 #define RT3883_PCI_REG_PCICFG 0x00 31 #define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf 32 #define RT3883_PCICFG_P2P_BR_DEVNUM_S 16 33 #define RT3883_PCICFG_PCIRST BIT(1) 34 #define RT3883_PCI_REG_PCIRAW 0x04 35 #define RT3883_PCI_REG_PCIINT 0x08 36 #define RT3883_PCI_REG_PCIENA 0x0c 37 38 #define RT3883_PCI_REG_CFGADDR 0x20 39 #define RT3883_PCI_REG_CFGDATA 0x24 40 #define RT3883_PCI_REG_MEMBASE 0x28 41 #define RT3883_PCI_REG_IOBASE 0x2c 42 #define RT3883_PCI_REG_ARBCTL 0x80 43 44 #define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000) 45 #define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10) 46 #define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18) 47 #define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30) 48 #define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34) 49 #define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38) 50 #define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50) 51 52 #define RT3883_PCI_MODE_NONE 0 53 #define RT3883_PCI_MODE_PCI BIT(0) 54 #define RT3883_PCI_MODE_PCIE BIT(1) 55 #define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE) 56 57 #define RT3883_PCI_IRQ_COUNT 32 58 59 #define RT3883_P2P_BR_DEVNUM 1 60 61 struct rt3883_pci_controller { 62 void __iomem *base; 63 64 struct device_node *intc_of_node; 65 struct irq_domain *irq_domain; 66 67 struct pci_controller pci_controller; 68 struct resource io_res; 69 struct resource mem_res; 70 71 bool pcie_ready; 72 }; 73 74 static inline struct rt3883_pci_controller * 75 pci_bus_to_rt3883_controller(struct pci_bus *bus) 76 { 77 struct pci_controller *hose; 78 79 hose = (struct pci_controller *) bus->sysdata; 80 return container_of(hose, struct rt3883_pci_controller, pci_controller); 81 } 82 83 static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc, 84 unsigned reg) 85 { 86 return ioread32(rpc->base + reg); 87 } 88 89 static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc, 90 u32 val, unsigned reg) 91 { 92 iowrite32(val, rpc->base + reg); 93 } 94 95 static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot, 96 unsigned int func, unsigned int where) 97 { 98 return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 99 0x80000000; 100 } 101 102 static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc, 103 unsigned bus, unsigned slot, 104 unsigned func, unsigned reg) 105 { 106 unsigned long flags; 107 u32 address; 108 u32 ret; 109 110 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); 111 112 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 113 ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 114 115 return ret; 116 } 117 118 static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc, 119 unsigned bus, unsigned slot, 120 unsigned func, unsigned reg, u32 val) 121 { 122 unsigned long flags; 123 u32 address; 124 125 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); 126 127 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 128 rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA); 129 } 130 131 static void rt3883_pci_irq_handler(struct irq_desc *desc) 132 { 133 struct rt3883_pci_controller *rpc; 134 u32 pending; 135 136 rpc = irq_desc_get_handler_data(desc); 137 138 pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) & 139 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 140 141 if (!pending) { 142 spurious_interrupt(); 143 return; 144 } 145 146 while (pending) { 147 unsigned irq, bit = __ffs(pending); 148 149 irq = irq_find_mapping(rpc->irq_domain, bit); 150 generic_handle_irq(irq); 151 152 pending &= ~BIT(bit); 153 } 154 } 155 156 static void rt3883_pci_irq_unmask(struct irq_data *d) 157 { 158 struct rt3883_pci_controller *rpc; 159 u32 t; 160 161 rpc = irq_data_get_irq_chip_data(d); 162 163 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 164 rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA); 165 /* flush write */ 166 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 167 } 168 169 static void rt3883_pci_irq_mask(struct irq_data *d) 170 { 171 struct rt3883_pci_controller *rpc; 172 u32 t; 173 174 rpc = irq_data_get_irq_chip_data(d); 175 176 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 177 rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA); 178 /* flush write */ 179 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 180 } 181 182 static struct irq_chip rt3883_pci_irq_chip = { 183 .name = "RT3883 PCI", 184 .irq_mask = rt3883_pci_irq_mask, 185 .irq_unmask = rt3883_pci_irq_unmask, 186 .irq_mask_ack = rt3883_pci_irq_mask, 187 }; 188 189 static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq, 190 irq_hw_number_t hw) 191 { 192 irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq); 193 irq_set_chip_data(irq, d->host_data); 194 195 return 0; 196 } 197 198 static const struct irq_domain_ops rt3883_pci_irq_domain_ops = { 199 .map = rt3883_pci_irq_map, 200 .xlate = irq_domain_xlate_onecell, 201 }; 202 203 static int rt3883_pci_irq_init(struct device *dev, 204 struct rt3883_pci_controller *rpc) 205 { 206 int irq; 207 208 irq = irq_of_parse_and_map(rpc->intc_of_node, 0); 209 if (irq == 0) { 210 dev_err(dev, "%s has no IRQ", 211 of_node_full_name(rpc->intc_of_node)); 212 return -EINVAL; 213 } 214 215 /* disable all interrupts */ 216 rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA); 217 218 rpc->irq_domain = 219 irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT, 220 &rt3883_pci_irq_domain_ops, 221 rpc); 222 if (!rpc->irq_domain) { 223 dev_err(dev, "unable to add IRQ domain\n"); 224 return -ENODEV; 225 } 226 227 irq_set_chained_handler_and_data(irq, rt3883_pci_irq_handler, rpc); 228 229 return 0; 230 } 231 232 static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn, 233 int where, int size, u32 *val) 234 { 235 struct rt3883_pci_controller *rpc; 236 unsigned long flags; 237 u32 address; 238 u32 data; 239 240 rpc = pci_bus_to_rt3883_controller(bus); 241 242 if (!rpc->pcie_ready && bus->number == 1) 243 return PCIBIOS_DEVICE_NOT_FOUND; 244 245 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), 246 PCI_FUNC(devfn), where); 247 248 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 249 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 250 251 switch (size) { 252 case 1: 253 *val = (data >> ((where & 3) << 3)) & 0xff; 254 break; 255 case 2: 256 *val = (data >> ((where & 3) << 3)) & 0xffff; 257 break; 258 case 4: 259 *val = data; 260 break; 261 } 262 263 return PCIBIOS_SUCCESSFUL; 264 } 265 266 static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn, 267 int where, int size, u32 val) 268 { 269 struct rt3883_pci_controller *rpc; 270 unsigned long flags; 271 u32 address; 272 u32 data; 273 274 rpc = pci_bus_to_rt3883_controller(bus); 275 276 if (!rpc->pcie_ready && bus->number == 1) 277 return PCIBIOS_DEVICE_NOT_FOUND; 278 279 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), 280 PCI_FUNC(devfn), where); 281 282 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 283 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 284 285 switch (size) { 286 case 1: 287 data = (data & ~(0xff << ((where & 3) << 3))) | 288 (val << ((where & 3) << 3)); 289 break; 290 case 2: 291 data = (data & ~(0xffff << ((where & 3) << 3))) | 292 (val << ((where & 3) << 3)); 293 break; 294 case 4: 295 data = val; 296 break; 297 } 298 299 rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA); 300 301 return PCIBIOS_SUCCESSFUL; 302 } 303 304 static struct pci_ops rt3883_pci_ops = { 305 .read = rt3883_pci_config_read, 306 .write = rt3883_pci_config_write, 307 }; 308 309 static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode) 310 { 311 u32 syscfg1; 312 u32 rstctrl; 313 u32 clkcfg1; 314 u32 t; 315 316 rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); 317 syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); 318 clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); 319 320 if (mode & RT3883_PCI_MODE_PCIE) { 321 rstctrl |= RT3883_RSTCTRL_PCIE; 322 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 323 324 /* setup PCI PAD drive mode */ 325 syscfg1 &= ~(0x30); 326 syscfg1 |= (2 << 4); 327 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); 328 329 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 330 t &= ~BIT(31); 331 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 332 333 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); 334 t &= 0x80ffffff; 335 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); 336 337 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); 338 t |= 0xa << 24; 339 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); 340 341 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 342 t |= BIT(31); 343 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 344 345 msleep(50); 346 347 rstctrl &= ~RT3883_RSTCTRL_PCIE; 348 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 349 } 350 351 syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE); 352 353 clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN); 354 355 if (mode & RT3883_PCI_MODE_PCI) { 356 clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN; 357 rstctrl &= ~RT3883_RSTCTRL_PCI; 358 } 359 360 if (mode & RT3883_PCI_MODE_PCIE) { 361 clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN; 362 rstctrl &= ~RT3883_RSTCTRL_PCIE; 363 } 364 365 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); 366 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 367 rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1); 368 369 msleep(500); 370 371 /* 372 * setup the device number of the P2P bridge 373 * and de-assert the reset line 374 */ 375 t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S); 376 rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG); 377 378 /* flush write */ 379 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG); 380 msleep(500); 381 382 if (mode & RT3883_PCI_MODE_PCIE) { 383 msleep(500); 384 385 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1)); 386 387 rpc->pcie_ready = t & BIT(0); 388 389 if (!rpc->pcie_ready) { 390 /* reset the PCIe block */ 391 t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); 392 t |= RT3883_RSTCTRL_PCIE; 393 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); 394 t &= ~RT3883_RSTCTRL_PCIE; 395 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); 396 397 /* turn off PCIe clock */ 398 t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); 399 t &= ~RT3883_CLKCFG1_PCIE_CLK_EN; 400 rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1); 401 402 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 403 t &= ~0xf000c080; 404 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 405 } 406 } 407 408 /* enable PCI arbiter */ 409 rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL); 410 } 411 412 static int rt3883_pci_probe(struct platform_device *pdev) 413 { 414 struct rt3883_pci_controller *rpc; 415 struct device *dev = &pdev->dev; 416 struct device_node *np = dev->of_node; 417 struct resource *res; 418 struct device_node *child; 419 u32 val; 420 int err; 421 int mode; 422 423 rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL); 424 if (!rpc) 425 return -ENOMEM; 426 427 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 428 rpc->base = devm_ioremap_resource(dev, res); 429 if (IS_ERR(rpc->base)) 430 return PTR_ERR(rpc->base); 431 432 /* find the interrupt controller child node */ 433 for_each_child_of_node(np, child) { 434 if (of_get_property(child, "interrupt-controller", NULL)) { 435 rpc->intc_of_node = child; 436 break; 437 } 438 } 439 440 if (!rpc->intc_of_node) { 441 dev_err(dev, "%s has no %s child node", 442 of_node_full_name(rpc->intc_of_node), 443 "interrupt controller"); 444 return -EINVAL; 445 } 446 447 /* find the PCI host bridge child node */ 448 for_each_child_of_node(np, child) { 449 if (child->type && 450 of_node_cmp(child->type, "pci") == 0) { 451 rpc->pci_controller.of_node = child; 452 break; 453 } 454 } 455 456 if (!rpc->pci_controller.of_node) { 457 dev_err(dev, "%s has no %s child node", 458 of_node_full_name(rpc->intc_of_node), 459 "PCI host bridge"); 460 err = -EINVAL; 461 goto err_put_intc_node; 462 } 463 464 mode = RT3883_PCI_MODE_NONE; 465 for_each_available_child_of_node(rpc->pci_controller.of_node, child) { 466 int devfn; 467 468 if (!child->type || 469 of_node_cmp(child->type, "pci") != 0) 470 continue; 471 472 devfn = of_pci_get_devfn(child); 473 if (devfn < 0) 474 continue; 475 476 switch (PCI_SLOT(devfn)) { 477 case 1: 478 mode |= RT3883_PCI_MODE_PCIE; 479 break; 480 481 case 17: 482 case 18: 483 mode |= RT3883_PCI_MODE_PCI; 484 break; 485 } 486 } 487 488 if (mode == RT3883_PCI_MODE_NONE) { 489 dev_err(dev, "unable to determine PCI mode\n"); 490 err = -EINVAL; 491 goto err_put_hb_node; 492 } 493 494 dev_info(dev, "mode:%s%s\n", 495 (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "", 496 (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : ""); 497 498 rt3883_pci_preinit(rpc, mode); 499 500 rpc->pci_controller.pci_ops = &rt3883_pci_ops; 501 rpc->pci_controller.io_resource = &rpc->io_res; 502 rpc->pci_controller.mem_resource = &rpc->mem_res; 503 504 /* Load PCI I/O and memory resources from DT */ 505 pci_load_of_ranges(&rpc->pci_controller, 506 rpc->pci_controller.of_node); 507 508 rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE); 509 rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE); 510 511 ioport_resource.start = rpc->io_res.start; 512 ioport_resource.end = rpc->io_res.end; 513 514 /* PCI */ 515 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0)); 516 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0)); 517 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0)); 518 rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0)); 519 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0)); 520 521 /* PCIe */ 522 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1)); 523 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1)); 524 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1)); 525 rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1)); 526 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1)); 527 528 err = rt3883_pci_irq_init(dev, rpc); 529 if (err) 530 goto err_put_hb_node; 531 532 /* PCIe */ 533 val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND); 534 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 535 rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val); 536 537 /* PCI */ 538 val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND); 539 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 540 rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val); 541 542 if (mode == RT3883_PCI_MODE_PCIE) { 543 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0)); 544 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1)); 545 546 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 547 PCI_BASE_ADDRESS_0, 548 RT3883_MEMORY_BASE); 549 /* flush write */ 550 rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 551 PCI_BASE_ADDRESS_0); 552 } else { 553 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 554 PCI_IO_BASE, 0x00000101); 555 } 556 557 register_pci_controller(&rpc->pci_controller); 558 559 return 0; 560 561 err_put_hb_node: 562 of_node_put(rpc->pci_controller.of_node); 563 err_put_intc_node: 564 of_node_put(rpc->intc_of_node); 565 return err; 566 } 567 568 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 569 { 570 return of_irq_parse_and_map_pci(dev, slot, pin); 571 } 572 573 int pcibios_plat_dev_init(struct pci_dev *dev) 574 { 575 return 0; 576 } 577 578 static const struct of_device_id rt3883_pci_ids[] = { 579 { .compatible = "ralink,rt3883-pci" }, 580 {}, 581 }; 582 583 static struct platform_driver rt3883_pci_driver = { 584 .probe = rt3883_pci_probe, 585 .driver = { 586 .name = "rt3883-pci", 587 .of_match_table = of_match_ptr(rt3883_pci_ids), 588 }, 589 }; 590 591 static int __init rt3883_pci_init(void) 592 { 593 return platform_driver_register(&rt3883_pci_driver); 594 } 595 596 postcore_initcall(rt3883_pci_init); 597