1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ralink RT3662/RT3883 SoC PCI support 4 * 5 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org> 6 * 7 * Parts of this file are based on Ralink's 2.6.21 BSP 8 */ 9 10 #include <linux/types.h> 11 #include <linux/pci.h> 12 #include <linux/io.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/interrupt.h> 16 #include <linux/of.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_pci.h> 19 #include <linux/platform_device.h> 20 21 #include <asm/mach-ralink/rt3883.h> 22 #include <asm/mach-ralink/ralink_regs.h> 23 24 #define RT3883_MEMORY_BASE 0x00000000 25 #define RT3883_MEMORY_SIZE 0x02000000 26 27 #define RT3883_PCI_REG_PCICFG 0x00 28 #define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf 29 #define RT3883_PCICFG_P2P_BR_DEVNUM_S 16 30 #define RT3883_PCICFG_PCIRST BIT(1) 31 #define RT3883_PCI_REG_PCIRAW 0x04 32 #define RT3883_PCI_REG_PCIINT 0x08 33 #define RT3883_PCI_REG_PCIENA 0x0c 34 35 #define RT3883_PCI_REG_CFGADDR 0x20 36 #define RT3883_PCI_REG_CFGDATA 0x24 37 #define RT3883_PCI_REG_MEMBASE 0x28 38 #define RT3883_PCI_REG_IOBASE 0x2c 39 #define RT3883_PCI_REG_ARBCTL 0x80 40 41 #define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000) 42 #define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10) 43 #define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18) 44 #define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30) 45 #define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34) 46 #define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38) 47 #define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50) 48 49 #define RT3883_PCI_MODE_NONE 0 50 #define RT3883_PCI_MODE_PCI BIT(0) 51 #define RT3883_PCI_MODE_PCIE BIT(1) 52 #define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE) 53 54 #define RT3883_PCI_IRQ_COUNT 32 55 56 #define RT3883_P2P_BR_DEVNUM 1 57 58 struct rt3883_pci_controller { 59 void __iomem *base; 60 61 struct device_node *intc_of_node; 62 struct irq_domain *irq_domain; 63 64 struct pci_controller pci_controller; 65 struct resource io_res; 66 struct resource mem_res; 67 68 bool pcie_ready; 69 }; 70 71 static inline struct rt3883_pci_controller * 72 pci_bus_to_rt3883_controller(struct pci_bus *bus) 73 { 74 struct pci_controller *hose; 75 76 hose = (struct pci_controller *) bus->sysdata; 77 return container_of(hose, struct rt3883_pci_controller, pci_controller); 78 } 79 80 static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc, 81 unsigned reg) 82 { 83 return ioread32(rpc->base + reg); 84 } 85 86 static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc, 87 u32 val, unsigned reg) 88 { 89 iowrite32(val, rpc->base + reg); 90 } 91 92 static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot, 93 unsigned int func, unsigned int where) 94 { 95 return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 96 0x80000000; 97 } 98 99 static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc, 100 unsigned bus, unsigned slot, 101 unsigned func, unsigned reg) 102 { 103 unsigned long flags; 104 u32 address; 105 u32 ret; 106 107 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); 108 109 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 110 ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 111 112 return ret; 113 } 114 115 static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc, 116 unsigned bus, unsigned slot, 117 unsigned func, unsigned reg, u32 val) 118 { 119 unsigned long flags; 120 u32 address; 121 122 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); 123 124 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 125 rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA); 126 } 127 128 static void rt3883_pci_irq_handler(struct irq_desc *desc) 129 { 130 struct rt3883_pci_controller *rpc; 131 u32 pending; 132 133 rpc = irq_desc_get_handler_data(desc); 134 135 pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) & 136 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 137 138 if (!pending) { 139 spurious_interrupt(); 140 return; 141 } 142 143 while (pending) { 144 unsigned irq, bit = __ffs(pending); 145 146 irq = irq_find_mapping(rpc->irq_domain, bit); 147 generic_handle_irq(irq); 148 149 pending &= ~BIT(bit); 150 } 151 } 152 153 static void rt3883_pci_irq_unmask(struct irq_data *d) 154 { 155 struct rt3883_pci_controller *rpc; 156 u32 t; 157 158 rpc = irq_data_get_irq_chip_data(d); 159 160 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 161 rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA); 162 /* flush write */ 163 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 164 } 165 166 static void rt3883_pci_irq_mask(struct irq_data *d) 167 { 168 struct rt3883_pci_controller *rpc; 169 u32 t; 170 171 rpc = irq_data_get_irq_chip_data(d); 172 173 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 174 rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA); 175 /* flush write */ 176 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 177 } 178 179 static struct irq_chip rt3883_pci_irq_chip = { 180 .name = "RT3883 PCI", 181 .irq_mask = rt3883_pci_irq_mask, 182 .irq_unmask = rt3883_pci_irq_unmask, 183 .irq_mask_ack = rt3883_pci_irq_mask, 184 }; 185 186 static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq, 187 irq_hw_number_t hw) 188 { 189 irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq); 190 irq_set_chip_data(irq, d->host_data); 191 192 return 0; 193 } 194 195 static const struct irq_domain_ops rt3883_pci_irq_domain_ops = { 196 .map = rt3883_pci_irq_map, 197 .xlate = irq_domain_xlate_onecell, 198 }; 199 200 static int rt3883_pci_irq_init(struct device *dev, 201 struct rt3883_pci_controller *rpc) 202 { 203 int irq; 204 205 irq = irq_of_parse_and_map(rpc->intc_of_node, 0); 206 if (irq == 0) { 207 dev_err(dev, "%pOF has no IRQ", rpc->intc_of_node); 208 return -EINVAL; 209 } 210 211 /* disable all interrupts */ 212 rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA); 213 214 rpc->irq_domain = 215 irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT, 216 &rt3883_pci_irq_domain_ops, 217 rpc); 218 if (!rpc->irq_domain) { 219 dev_err(dev, "unable to add IRQ domain\n"); 220 return -ENODEV; 221 } 222 223 irq_set_chained_handler_and_data(irq, rt3883_pci_irq_handler, rpc); 224 225 return 0; 226 } 227 228 static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn, 229 int where, int size, u32 *val) 230 { 231 struct rt3883_pci_controller *rpc; 232 unsigned long flags; 233 u32 address; 234 u32 data; 235 236 rpc = pci_bus_to_rt3883_controller(bus); 237 238 if (!rpc->pcie_ready && bus->number == 1) 239 return PCIBIOS_DEVICE_NOT_FOUND; 240 241 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), 242 PCI_FUNC(devfn), where); 243 244 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 245 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 246 247 switch (size) { 248 case 1: 249 *val = (data >> ((where & 3) << 3)) & 0xff; 250 break; 251 case 2: 252 *val = (data >> ((where & 3) << 3)) & 0xffff; 253 break; 254 case 4: 255 *val = data; 256 break; 257 } 258 259 return PCIBIOS_SUCCESSFUL; 260 } 261 262 static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn, 263 int where, int size, u32 val) 264 { 265 struct rt3883_pci_controller *rpc; 266 unsigned long flags; 267 u32 address; 268 u32 data; 269 270 rpc = pci_bus_to_rt3883_controller(bus); 271 272 if (!rpc->pcie_ready && bus->number == 1) 273 return PCIBIOS_DEVICE_NOT_FOUND; 274 275 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), 276 PCI_FUNC(devfn), where); 277 278 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 279 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 280 281 switch (size) { 282 case 1: 283 data = (data & ~(0xff << ((where & 3) << 3))) | 284 (val << ((where & 3) << 3)); 285 break; 286 case 2: 287 data = (data & ~(0xffff << ((where & 3) << 3))) | 288 (val << ((where & 3) << 3)); 289 break; 290 case 4: 291 data = val; 292 break; 293 } 294 295 rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA); 296 297 return PCIBIOS_SUCCESSFUL; 298 } 299 300 static struct pci_ops rt3883_pci_ops = { 301 .read = rt3883_pci_config_read, 302 .write = rt3883_pci_config_write, 303 }; 304 305 static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode) 306 { 307 u32 syscfg1; 308 u32 rstctrl; 309 u32 clkcfg1; 310 u32 t; 311 312 rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); 313 syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); 314 clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); 315 316 if (mode & RT3883_PCI_MODE_PCIE) { 317 rstctrl |= RT3883_RSTCTRL_PCIE; 318 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 319 320 /* setup PCI PAD drive mode */ 321 syscfg1 &= ~(0x30); 322 syscfg1 |= (2 << 4); 323 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); 324 325 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 326 t &= ~BIT(31); 327 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 328 329 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); 330 t &= 0x80ffffff; 331 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); 332 333 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); 334 t |= 0xa << 24; 335 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); 336 337 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 338 t |= BIT(31); 339 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 340 341 msleep(50); 342 343 rstctrl &= ~RT3883_RSTCTRL_PCIE; 344 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 345 } 346 347 syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE); 348 349 clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN); 350 351 if (mode & RT3883_PCI_MODE_PCI) { 352 clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN; 353 rstctrl &= ~RT3883_RSTCTRL_PCI; 354 } 355 356 if (mode & RT3883_PCI_MODE_PCIE) { 357 clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN; 358 rstctrl &= ~RT3883_RSTCTRL_PCIE; 359 } 360 361 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); 362 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 363 rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1); 364 365 msleep(500); 366 367 /* 368 * setup the device number of the P2P bridge 369 * and de-assert the reset line 370 */ 371 t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S); 372 rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG); 373 374 /* flush write */ 375 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG); 376 msleep(500); 377 378 if (mode & RT3883_PCI_MODE_PCIE) { 379 msleep(500); 380 381 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1)); 382 383 rpc->pcie_ready = t & BIT(0); 384 385 if (!rpc->pcie_ready) { 386 /* reset the PCIe block */ 387 t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); 388 t |= RT3883_RSTCTRL_PCIE; 389 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); 390 t &= ~RT3883_RSTCTRL_PCIE; 391 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); 392 393 /* turn off PCIe clock */ 394 t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); 395 t &= ~RT3883_CLKCFG1_PCIE_CLK_EN; 396 rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1); 397 398 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 399 t &= ~0xf000c080; 400 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 401 } 402 } 403 404 /* enable PCI arbiter */ 405 rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL); 406 } 407 408 static int rt3883_pci_probe(struct platform_device *pdev) 409 { 410 struct rt3883_pci_controller *rpc; 411 struct device *dev = &pdev->dev; 412 struct device_node *np = dev->of_node; 413 struct resource *res; 414 struct device_node *child; 415 u32 val; 416 int err; 417 int mode; 418 419 rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL); 420 if (!rpc) 421 return -ENOMEM; 422 423 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 424 rpc->base = devm_ioremap_resource(dev, res); 425 if (IS_ERR(rpc->base)) 426 return PTR_ERR(rpc->base); 427 428 /* find the interrupt controller child node */ 429 for_each_child_of_node(np, child) { 430 if (of_get_property(child, "interrupt-controller", NULL)) { 431 rpc->intc_of_node = child; 432 break; 433 } 434 } 435 436 if (!rpc->intc_of_node) { 437 dev_err(dev, "%pOF has no %s child node", 438 rpc->intc_of_node, 439 "interrupt controller"); 440 return -EINVAL; 441 } 442 443 /* find the PCI host bridge child node */ 444 for_each_child_of_node(np, child) { 445 if (of_node_is_type(child, "pci")) { 446 rpc->pci_controller.of_node = child; 447 break; 448 } 449 } 450 451 if (!rpc->pci_controller.of_node) { 452 dev_err(dev, "%pOF has no %s child node", 453 rpc->intc_of_node, 454 "PCI host bridge"); 455 err = -EINVAL; 456 goto err_put_intc_node; 457 } 458 459 mode = RT3883_PCI_MODE_NONE; 460 for_each_available_child_of_node(rpc->pci_controller.of_node, child) { 461 int devfn; 462 463 if (!of_node_is_type(child, "pci")) 464 continue; 465 466 devfn = of_pci_get_devfn(child); 467 if (devfn < 0) 468 continue; 469 470 switch (PCI_SLOT(devfn)) { 471 case 1: 472 mode |= RT3883_PCI_MODE_PCIE; 473 break; 474 475 case 17: 476 case 18: 477 mode |= RT3883_PCI_MODE_PCI; 478 break; 479 } 480 } 481 482 if (mode == RT3883_PCI_MODE_NONE) { 483 dev_err(dev, "unable to determine PCI mode\n"); 484 err = -EINVAL; 485 goto err_put_hb_node; 486 } 487 488 dev_info(dev, "mode:%s%s\n", 489 (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "", 490 (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : ""); 491 492 rt3883_pci_preinit(rpc, mode); 493 494 rpc->pci_controller.pci_ops = &rt3883_pci_ops; 495 rpc->pci_controller.io_resource = &rpc->io_res; 496 rpc->pci_controller.mem_resource = &rpc->mem_res; 497 498 /* Load PCI I/O and memory resources from DT */ 499 pci_load_of_ranges(&rpc->pci_controller, 500 rpc->pci_controller.of_node); 501 502 rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE); 503 rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE); 504 505 ioport_resource.start = rpc->io_res.start; 506 ioport_resource.end = rpc->io_res.end; 507 508 /* PCI */ 509 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0)); 510 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0)); 511 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0)); 512 rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0)); 513 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0)); 514 515 /* PCIe */ 516 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1)); 517 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1)); 518 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1)); 519 rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1)); 520 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1)); 521 522 err = rt3883_pci_irq_init(dev, rpc); 523 if (err) 524 goto err_put_hb_node; 525 526 /* PCIe */ 527 val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND); 528 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 529 rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val); 530 531 /* PCI */ 532 val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND); 533 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 534 rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val); 535 536 if (mode == RT3883_PCI_MODE_PCIE) { 537 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0)); 538 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1)); 539 540 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 541 PCI_BASE_ADDRESS_0, 542 RT3883_MEMORY_BASE); 543 /* flush write */ 544 rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 545 PCI_BASE_ADDRESS_0); 546 } else { 547 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 548 PCI_IO_BASE, 0x00000101); 549 } 550 551 register_pci_controller(&rpc->pci_controller); 552 553 return 0; 554 555 err_put_hb_node: 556 of_node_put(rpc->pci_controller.of_node); 557 err_put_intc_node: 558 of_node_put(rpc->intc_of_node); 559 return err; 560 } 561 562 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 563 { 564 return of_irq_parse_and_map_pci(dev, slot, pin); 565 } 566 567 int pcibios_plat_dev_init(struct pci_dev *dev) 568 { 569 return 0; 570 } 571 572 static const struct of_device_id rt3883_pci_ids[] = { 573 { .compatible = "ralink,rt3883-pci" }, 574 {}, 575 }; 576 577 static struct platform_driver rt3883_pci_driver = { 578 .probe = rt3883_pci_probe, 579 .driver = { 580 .name = "rt3883-pci", 581 .of_match_table = of_match_ptr(rt3883_pci_ids), 582 }, 583 }; 584 585 static int __init rt3883_pci_init(void) 586 { 587 return platform_driver_register(&rt3883_pci_driver); 588 } 589 590 postcore_initcall(rt3883_pci_init); 591