1 /* 2 * Ralink RT3662/RT3883 SoC PCI support 3 * 4 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org> 5 * 6 * Parts of this file are based on Ralink's 2.6.21 BSP 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published 10 * by the Free Software Foundation. 11 */ 12 13 #include <linux/types.h> 14 #include <linux/pci.h> 15 #include <linux/io.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/of.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_pci.h> 22 #include <linux/platform_device.h> 23 24 #include <asm/mach-ralink/rt3883.h> 25 #include <asm/mach-ralink/ralink_regs.h> 26 27 #define RT3883_MEMORY_BASE 0x00000000 28 #define RT3883_MEMORY_SIZE 0x02000000 29 30 #define RT3883_PCI_REG_PCICFG 0x00 31 #define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf 32 #define RT3883_PCICFG_P2P_BR_DEVNUM_S 16 33 #define RT3883_PCICFG_PCIRST BIT(1) 34 #define RT3883_PCI_REG_PCIRAW 0x04 35 #define RT3883_PCI_REG_PCIINT 0x08 36 #define RT3883_PCI_REG_PCIENA 0x0c 37 38 #define RT3883_PCI_REG_CFGADDR 0x20 39 #define RT3883_PCI_REG_CFGDATA 0x24 40 #define RT3883_PCI_REG_MEMBASE 0x28 41 #define RT3883_PCI_REG_IOBASE 0x2c 42 #define RT3883_PCI_REG_ARBCTL 0x80 43 44 #define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000) 45 #define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10) 46 #define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18) 47 #define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30) 48 #define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34) 49 #define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38) 50 #define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50) 51 52 #define RT3883_PCI_MODE_NONE 0 53 #define RT3883_PCI_MODE_PCI BIT(0) 54 #define RT3883_PCI_MODE_PCIE BIT(1) 55 #define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE) 56 57 #define RT3883_PCI_IRQ_COUNT 32 58 59 #define RT3883_P2P_BR_DEVNUM 1 60 61 struct rt3883_pci_controller { 62 void __iomem *base; 63 64 struct device_node *intc_of_node; 65 struct irq_domain *irq_domain; 66 67 struct pci_controller pci_controller; 68 struct resource io_res; 69 struct resource mem_res; 70 71 bool pcie_ready; 72 }; 73 74 static inline struct rt3883_pci_controller * 75 pci_bus_to_rt3883_controller(struct pci_bus *bus) 76 { 77 struct pci_controller *hose; 78 79 hose = (struct pci_controller *) bus->sysdata; 80 return container_of(hose, struct rt3883_pci_controller, pci_controller); 81 } 82 83 static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc, 84 unsigned reg) 85 { 86 return ioread32(rpc->base + reg); 87 } 88 89 static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc, 90 u32 val, unsigned reg) 91 { 92 iowrite32(val, rpc->base + reg); 93 } 94 95 static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot, 96 unsigned int func, unsigned int where) 97 { 98 return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 99 0x80000000; 100 } 101 102 static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc, 103 unsigned bus, unsigned slot, 104 unsigned func, unsigned reg) 105 { 106 unsigned long flags; 107 u32 address; 108 u32 ret; 109 110 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); 111 112 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 113 ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 114 115 return ret; 116 } 117 118 static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc, 119 unsigned bus, unsigned slot, 120 unsigned func, unsigned reg, u32 val) 121 { 122 unsigned long flags; 123 u32 address; 124 125 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); 126 127 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 128 rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA); 129 } 130 131 static void rt3883_pci_irq_handler(struct irq_desc *desc) 132 { 133 struct rt3883_pci_controller *rpc; 134 u32 pending; 135 136 rpc = irq_desc_get_handler_data(desc); 137 138 pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) & 139 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 140 141 if (!pending) { 142 spurious_interrupt(); 143 return; 144 } 145 146 while (pending) { 147 unsigned irq, bit = __ffs(pending); 148 149 irq = irq_find_mapping(rpc->irq_domain, bit); 150 generic_handle_irq(irq); 151 152 pending &= ~BIT(bit); 153 } 154 } 155 156 static void rt3883_pci_irq_unmask(struct irq_data *d) 157 { 158 struct rt3883_pci_controller *rpc; 159 u32 t; 160 161 rpc = irq_data_get_irq_chip_data(d); 162 163 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 164 rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA); 165 /* flush write */ 166 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 167 } 168 169 static void rt3883_pci_irq_mask(struct irq_data *d) 170 { 171 struct rt3883_pci_controller *rpc; 172 u32 t; 173 174 rpc = irq_data_get_irq_chip_data(d); 175 176 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 177 rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA); 178 /* flush write */ 179 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 180 } 181 182 static struct irq_chip rt3883_pci_irq_chip = { 183 .name = "RT3883 PCI", 184 .irq_mask = rt3883_pci_irq_mask, 185 .irq_unmask = rt3883_pci_irq_unmask, 186 .irq_mask_ack = rt3883_pci_irq_mask, 187 }; 188 189 static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq, 190 irq_hw_number_t hw) 191 { 192 irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq); 193 irq_set_chip_data(irq, d->host_data); 194 195 return 0; 196 } 197 198 static const struct irq_domain_ops rt3883_pci_irq_domain_ops = { 199 .map = rt3883_pci_irq_map, 200 .xlate = irq_domain_xlate_onecell, 201 }; 202 203 static int rt3883_pci_irq_init(struct device *dev, 204 struct rt3883_pci_controller *rpc) 205 { 206 int irq; 207 208 irq = irq_of_parse_and_map(rpc->intc_of_node, 0); 209 if (irq == 0) { 210 dev_err(dev, "%pOF has no IRQ", rpc->intc_of_node); 211 return -EINVAL; 212 } 213 214 /* disable all interrupts */ 215 rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA); 216 217 rpc->irq_domain = 218 irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT, 219 &rt3883_pci_irq_domain_ops, 220 rpc); 221 if (!rpc->irq_domain) { 222 dev_err(dev, "unable to add IRQ domain\n"); 223 return -ENODEV; 224 } 225 226 irq_set_chained_handler_and_data(irq, rt3883_pci_irq_handler, rpc); 227 228 return 0; 229 } 230 231 static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn, 232 int where, int size, u32 *val) 233 { 234 struct rt3883_pci_controller *rpc; 235 unsigned long flags; 236 u32 address; 237 u32 data; 238 239 rpc = pci_bus_to_rt3883_controller(bus); 240 241 if (!rpc->pcie_ready && bus->number == 1) 242 return PCIBIOS_DEVICE_NOT_FOUND; 243 244 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), 245 PCI_FUNC(devfn), where); 246 247 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 248 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 249 250 switch (size) { 251 case 1: 252 *val = (data >> ((where & 3) << 3)) & 0xff; 253 break; 254 case 2: 255 *val = (data >> ((where & 3) << 3)) & 0xffff; 256 break; 257 case 4: 258 *val = data; 259 break; 260 } 261 262 return PCIBIOS_SUCCESSFUL; 263 } 264 265 static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn, 266 int where, int size, u32 val) 267 { 268 struct rt3883_pci_controller *rpc; 269 unsigned long flags; 270 u32 address; 271 u32 data; 272 273 rpc = pci_bus_to_rt3883_controller(bus); 274 275 if (!rpc->pcie_ready && bus->number == 1) 276 return PCIBIOS_DEVICE_NOT_FOUND; 277 278 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), 279 PCI_FUNC(devfn), where); 280 281 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 282 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 283 284 switch (size) { 285 case 1: 286 data = (data & ~(0xff << ((where & 3) << 3))) | 287 (val << ((where & 3) << 3)); 288 break; 289 case 2: 290 data = (data & ~(0xffff << ((where & 3) << 3))) | 291 (val << ((where & 3) << 3)); 292 break; 293 case 4: 294 data = val; 295 break; 296 } 297 298 rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA); 299 300 return PCIBIOS_SUCCESSFUL; 301 } 302 303 static struct pci_ops rt3883_pci_ops = { 304 .read = rt3883_pci_config_read, 305 .write = rt3883_pci_config_write, 306 }; 307 308 static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode) 309 { 310 u32 syscfg1; 311 u32 rstctrl; 312 u32 clkcfg1; 313 u32 t; 314 315 rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); 316 syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); 317 clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); 318 319 if (mode & RT3883_PCI_MODE_PCIE) { 320 rstctrl |= RT3883_RSTCTRL_PCIE; 321 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 322 323 /* setup PCI PAD drive mode */ 324 syscfg1 &= ~(0x30); 325 syscfg1 |= (2 << 4); 326 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); 327 328 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 329 t &= ~BIT(31); 330 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 331 332 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); 333 t &= 0x80ffffff; 334 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); 335 336 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); 337 t |= 0xa << 24; 338 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); 339 340 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 341 t |= BIT(31); 342 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 343 344 msleep(50); 345 346 rstctrl &= ~RT3883_RSTCTRL_PCIE; 347 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 348 } 349 350 syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE); 351 352 clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN); 353 354 if (mode & RT3883_PCI_MODE_PCI) { 355 clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN; 356 rstctrl &= ~RT3883_RSTCTRL_PCI; 357 } 358 359 if (mode & RT3883_PCI_MODE_PCIE) { 360 clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN; 361 rstctrl &= ~RT3883_RSTCTRL_PCIE; 362 } 363 364 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); 365 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 366 rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1); 367 368 msleep(500); 369 370 /* 371 * setup the device number of the P2P bridge 372 * and de-assert the reset line 373 */ 374 t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S); 375 rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG); 376 377 /* flush write */ 378 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG); 379 msleep(500); 380 381 if (mode & RT3883_PCI_MODE_PCIE) { 382 msleep(500); 383 384 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1)); 385 386 rpc->pcie_ready = t & BIT(0); 387 388 if (!rpc->pcie_ready) { 389 /* reset the PCIe block */ 390 t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); 391 t |= RT3883_RSTCTRL_PCIE; 392 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); 393 t &= ~RT3883_RSTCTRL_PCIE; 394 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); 395 396 /* turn off PCIe clock */ 397 t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); 398 t &= ~RT3883_CLKCFG1_PCIE_CLK_EN; 399 rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1); 400 401 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 402 t &= ~0xf000c080; 403 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 404 } 405 } 406 407 /* enable PCI arbiter */ 408 rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL); 409 } 410 411 static int rt3883_pci_probe(struct platform_device *pdev) 412 { 413 struct rt3883_pci_controller *rpc; 414 struct device *dev = &pdev->dev; 415 struct device_node *np = dev->of_node; 416 struct resource *res; 417 struct device_node *child; 418 u32 val; 419 int err; 420 int mode; 421 422 rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL); 423 if (!rpc) 424 return -ENOMEM; 425 426 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 427 rpc->base = devm_ioremap_resource(dev, res); 428 if (IS_ERR(rpc->base)) 429 return PTR_ERR(rpc->base); 430 431 /* find the interrupt controller child node */ 432 for_each_child_of_node(np, child) { 433 if (of_get_property(child, "interrupt-controller", NULL)) { 434 rpc->intc_of_node = child; 435 break; 436 } 437 } 438 439 if (!rpc->intc_of_node) { 440 dev_err(dev, "%pOF has no %s child node", 441 rpc->intc_of_node, 442 "interrupt controller"); 443 return -EINVAL; 444 } 445 446 /* find the PCI host bridge child node */ 447 for_each_child_of_node(np, child) { 448 if (of_node_is_type(child, "pci")) { 449 rpc->pci_controller.of_node = child; 450 break; 451 } 452 } 453 454 if (!rpc->pci_controller.of_node) { 455 dev_err(dev, "%pOF has no %s child node", 456 rpc->intc_of_node, 457 "PCI host bridge"); 458 err = -EINVAL; 459 goto err_put_intc_node; 460 } 461 462 mode = RT3883_PCI_MODE_NONE; 463 for_each_available_child_of_node(rpc->pci_controller.of_node, child) { 464 int devfn; 465 466 if (!of_node_is_type(child, "pci")) 467 continue; 468 469 devfn = of_pci_get_devfn(child); 470 if (devfn < 0) 471 continue; 472 473 switch (PCI_SLOT(devfn)) { 474 case 1: 475 mode |= RT3883_PCI_MODE_PCIE; 476 break; 477 478 case 17: 479 case 18: 480 mode |= RT3883_PCI_MODE_PCI; 481 break; 482 } 483 } 484 485 if (mode == RT3883_PCI_MODE_NONE) { 486 dev_err(dev, "unable to determine PCI mode\n"); 487 err = -EINVAL; 488 goto err_put_hb_node; 489 } 490 491 dev_info(dev, "mode:%s%s\n", 492 (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "", 493 (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : ""); 494 495 rt3883_pci_preinit(rpc, mode); 496 497 rpc->pci_controller.pci_ops = &rt3883_pci_ops; 498 rpc->pci_controller.io_resource = &rpc->io_res; 499 rpc->pci_controller.mem_resource = &rpc->mem_res; 500 501 /* Load PCI I/O and memory resources from DT */ 502 pci_load_of_ranges(&rpc->pci_controller, 503 rpc->pci_controller.of_node); 504 505 rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE); 506 rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE); 507 508 ioport_resource.start = rpc->io_res.start; 509 ioport_resource.end = rpc->io_res.end; 510 511 /* PCI */ 512 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0)); 513 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0)); 514 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0)); 515 rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0)); 516 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0)); 517 518 /* PCIe */ 519 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1)); 520 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1)); 521 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1)); 522 rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1)); 523 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1)); 524 525 err = rt3883_pci_irq_init(dev, rpc); 526 if (err) 527 goto err_put_hb_node; 528 529 /* PCIe */ 530 val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND); 531 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 532 rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val); 533 534 /* PCI */ 535 val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND); 536 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 537 rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val); 538 539 if (mode == RT3883_PCI_MODE_PCIE) { 540 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0)); 541 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1)); 542 543 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 544 PCI_BASE_ADDRESS_0, 545 RT3883_MEMORY_BASE); 546 /* flush write */ 547 rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 548 PCI_BASE_ADDRESS_0); 549 } else { 550 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 551 PCI_IO_BASE, 0x00000101); 552 } 553 554 register_pci_controller(&rpc->pci_controller); 555 556 return 0; 557 558 err_put_hb_node: 559 of_node_put(rpc->pci_controller.of_node); 560 err_put_intc_node: 561 of_node_put(rpc->intc_of_node); 562 return err; 563 } 564 565 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 566 { 567 return of_irq_parse_and_map_pci(dev, slot, pin); 568 } 569 570 int pcibios_plat_dev_init(struct pci_dev *dev) 571 { 572 return 0; 573 } 574 575 static const struct of_device_id rt3883_pci_ids[] = { 576 { .compatible = "ralink,rt3883-pci" }, 577 {}, 578 }; 579 580 static struct platform_driver rt3883_pci_driver = { 581 .probe = rt3883_pci_probe, 582 .driver = { 583 .name = "rt3883-pci", 584 .of_match_table = of_match_ptr(rt3883_pci_ids), 585 }, 586 }; 587 588 static int __init rt3883_pci_init(void) 589 { 590 return platform_driver_register(&rt3883_pci_driver); 591 } 592 593 postcore_initcall(rt3883_pci_init); 594