1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2005-2009 Cavium Networks 7 */ 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/pci.h> 11 #include <linux/interrupt.h> 12 #include <linux/time.h> 13 #include <linux/delay.h> 14 #include <linux/swiotlb.h> 15 16 #include <asm/time.h> 17 18 #include <asm/octeon/octeon.h> 19 #include <asm/octeon/cvmx-npi-defs.h> 20 #include <asm/octeon/cvmx-pci-defs.h> 21 #include <asm/octeon/pci-octeon.h> 22 23 #include <dma-coherence.h> 24 25 #define USE_OCTEON_INTERNAL_ARBITER 26 27 /* 28 * Octeon's PCI controller uses did=3, subdid=2 for PCI IO 29 * addresses. Use PCI endian swapping 1 so no address swapping is 30 * necessary. The Linux io routines will endian swap the data. 31 */ 32 #define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull 33 #define OCTEON_PCI_IOSPACE_SIZE (1ull<<32) 34 35 /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */ 36 #define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull) 37 38 u64 octeon_bar1_pci_phys; 39 40 /** 41 * This is the bit decoding used for the Octeon PCI controller addresses 42 */ 43 union octeon_pci_address { 44 uint64_t u64; 45 struct { 46 uint64_t upper:2; 47 uint64_t reserved:13; 48 uint64_t io:1; 49 uint64_t did:5; 50 uint64_t subdid:3; 51 uint64_t reserved2:4; 52 uint64_t endian_swap:2; 53 uint64_t reserved3:10; 54 uint64_t bus:8; 55 uint64_t dev:5; 56 uint64_t func:3; 57 uint64_t reg:8; 58 } s; 59 }; 60 61 int __initdata (*octeon_pcibios_map_irq)(const struct pci_dev *dev, 62 u8 slot, u8 pin); 63 enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID; 64 65 /** 66 * Map a PCI device to the appropriate interrupt line 67 * 68 * @dev: The Linux PCI device structure for the device to map 69 * @slot: The slot number for this device on __BUS 0__. Linux 70 * enumerates through all the bridges and figures out the 71 * slot on Bus 0 where this device eventually hooks to. 72 * @pin: The PCI interrupt pin read from the device, then swizzled 73 * as it goes through each bridge. 74 * Returns Interrupt number for the device 75 */ 76 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 77 { 78 if (octeon_pcibios_map_irq) 79 return octeon_pcibios_map_irq(dev, slot, pin); 80 else 81 panic("octeon_pcibios_map_irq not set."); 82 } 83 84 85 /* 86 * Called to perform platform specific PCI setup 87 */ 88 int pcibios_plat_dev_init(struct pci_dev *dev) 89 { 90 uint16_t config; 91 uint32_t dconfig; 92 int pos; 93 /* 94 * Force the Cache line setting to 64 bytes. The standard 95 * Linux bus scan doesn't seem to set it. Octeon really has 96 * 128 byte lines, but Intel bridges get really upset if you 97 * try and set values above 64 bytes. Value is specified in 98 * 32bit words. 99 */ 100 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4); 101 /* Set latency timers for all devices */ 102 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48); 103 104 /* Enable reporting System errors and parity errors on all devices */ 105 /* Enable parity checking and error reporting */ 106 pci_read_config_word(dev, PCI_COMMAND, &config); 107 config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; 108 pci_write_config_word(dev, PCI_COMMAND, config); 109 110 if (dev->subordinate) { 111 /* Set latency timers on sub bridges */ 112 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48); 113 /* More bridge error detection */ 114 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); 115 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; 116 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); 117 } 118 119 /* Enable the PCIe normal error reporting */ 120 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 121 if (pos) { 122 /* Update Device Control */ 123 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); 124 /* Correctable Error Reporting */ 125 config |= PCI_EXP_DEVCTL_CERE; 126 /* Non-Fatal Error Reporting */ 127 config |= PCI_EXP_DEVCTL_NFERE; 128 /* Fatal Error Reporting */ 129 config |= PCI_EXP_DEVCTL_FERE; 130 /* Unsupported Request */ 131 config |= PCI_EXP_DEVCTL_URRE; 132 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); 133 } 134 135 /* Find the Advanced Error Reporting capability */ 136 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 137 if (pos) { 138 /* Clear Uncorrectable Error Status */ 139 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, 140 &dconfig); 141 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, 142 dconfig); 143 /* Enable reporting of all uncorrectable errors */ 144 /* Uncorrectable Error Mask - turned on bits disable errors */ 145 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); 146 /* 147 * Leave severity at HW default. This only controls if 148 * errors are reported as uncorrectable or 149 * correctable, not if the error is reported. 150 */ 151 /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ 152 /* Clear Correctable Error Status */ 153 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); 154 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); 155 /* Enable reporting of all correctable errors */ 156 /* Correctable Error Mask - turned on bits disable errors */ 157 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); 158 /* Advanced Error Capabilities */ 159 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); 160 /* ECRC Generation Enable */ 161 if (config & PCI_ERR_CAP_ECRC_GENC) 162 config |= PCI_ERR_CAP_ECRC_GENE; 163 /* ECRC Check Enable */ 164 if (config & PCI_ERR_CAP_ECRC_CHKC) 165 config |= PCI_ERR_CAP_ECRC_CHKE; 166 pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); 167 /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ 168 /* Report all errors to the root complex */ 169 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, 170 PCI_ERR_ROOT_CMD_COR_EN | 171 PCI_ERR_ROOT_CMD_NONFATAL_EN | 172 PCI_ERR_ROOT_CMD_FATAL_EN); 173 /* Clear the Root status register */ 174 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); 175 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); 176 } 177 178 dev->dev.archdata.dma_ops = octeon_pci_dma_map_ops; 179 180 return 0; 181 } 182 183 /** 184 * Return the mapping of PCI device number to IRQ line. Each 185 * character in the return string represents the interrupt 186 * line for the device at that position. Device 1 maps to the 187 * first character, etc. The characters A-D are used for PCI 188 * interrupts. 189 * 190 * Returns PCI interrupt mapping 191 */ 192 const char *octeon_get_pci_interrupts(void) 193 { 194 /* 195 * Returning an empty string causes the interrupts to be 196 * routed based on the PCI specification. From the PCI spec: 197 * 198 * INTA# of Device Number 0 is connected to IRQW on the system 199 * board. (Device Number has no significance regarding being 200 * located on the system board or in a connector.) INTA# of 201 * Device Number 1 is connected to IRQX on the system 202 * board. INTA# of Device Number 2 is connected to IRQY on the 203 * system board. INTA# of Device Number 3 is connected to IRQZ 204 * on the system board. The table below describes how each 205 * agent's INTx# lines are connected to the system board 206 * interrupt lines. The following equation can be used to 207 * determine to which INTx# signal on the system board a given 208 * device's INTx# line(s) is connected. 209 * 210 * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0, 211 * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I = 212 * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and 213 * INTD# = 3) 214 */ 215 switch (octeon_bootinfo->board_type) { 216 case CVMX_BOARD_TYPE_NAO38: 217 /* This is really the NAC38 */ 218 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA"; 219 case CVMX_BOARD_TYPE_EBH3100: 220 case CVMX_BOARD_TYPE_CN3010_EVB_HS5: 221 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 222 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA"; 223 case CVMX_BOARD_TYPE_BBGW_REF: 224 return "AABCD"; 225 case CVMX_BOARD_TYPE_THUNDER: 226 case CVMX_BOARD_TYPE_EBH3000: 227 default: 228 return ""; 229 } 230 } 231 232 /** 233 * Map a PCI device to the appropriate interrupt line 234 * 235 * @dev: The Linux PCI device structure for the device to map 236 * @slot: The slot number for this device on __BUS 0__. Linux 237 * enumerates through all the bridges and figures out the 238 * slot on Bus 0 where this device eventually hooks to. 239 * @pin: The PCI interrupt pin read from the device, then swizzled 240 * as it goes through each bridge. 241 * Returns Interrupt number for the device 242 */ 243 int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev, 244 u8 slot, u8 pin) 245 { 246 int irq_num; 247 const char *interrupts; 248 int dev_num; 249 250 /* Get the board specific interrupt mapping */ 251 interrupts = octeon_get_pci_interrupts(); 252 253 dev_num = dev->devfn >> 3; 254 if (dev_num < strlen(interrupts)) 255 irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) + 256 OCTEON_IRQ_PCI_INT0; 257 else 258 irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0; 259 return irq_num; 260 } 261 262 263 /* 264 * Read a value from configuration space 265 */ 266 static int octeon_read_config(struct pci_bus *bus, unsigned int devfn, 267 int reg, int size, u32 *val) 268 { 269 union octeon_pci_address pci_addr; 270 271 pci_addr.u64 = 0; 272 pci_addr.s.upper = 2; 273 pci_addr.s.io = 1; 274 pci_addr.s.did = 3; 275 pci_addr.s.subdid = 1; 276 pci_addr.s.endian_swap = 1; 277 pci_addr.s.bus = bus->number; 278 pci_addr.s.dev = devfn >> 3; 279 pci_addr.s.func = devfn & 0x7; 280 pci_addr.s.reg = reg; 281 282 #if PCI_CONFIG_SPACE_DELAY 283 udelay(PCI_CONFIG_SPACE_DELAY); 284 #endif 285 switch (size) { 286 case 4: 287 *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64)); 288 return PCIBIOS_SUCCESSFUL; 289 case 2: 290 *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64)); 291 return PCIBIOS_SUCCESSFUL; 292 case 1: 293 *val = cvmx_read64_uint8(pci_addr.u64); 294 return PCIBIOS_SUCCESSFUL; 295 } 296 return PCIBIOS_FUNC_NOT_SUPPORTED; 297 } 298 299 300 /* 301 * Write a value to PCI configuration space 302 */ 303 static int octeon_write_config(struct pci_bus *bus, unsigned int devfn, 304 int reg, int size, u32 val) 305 { 306 union octeon_pci_address pci_addr; 307 308 pci_addr.u64 = 0; 309 pci_addr.s.upper = 2; 310 pci_addr.s.io = 1; 311 pci_addr.s.did = 3; 312 pci_addr.s.subdid = 1; 313 pci_addr.s.endian_swap = 1; 314 pci_addr.s.bus = bus->number; 315 pci_addr.s.dev = devfn >> 3; 316 pci_addr.s.func = devfn & 0x7; 317 pci_addr.s.reg = reg; 318 319 #if PCI_CONFIG_SPACE_DELAY 320 udelay(PCI_CONFIG_SPACE_DELAY); 321 #endif 322 switch (size) { 323 case 4: 324 cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val)); 325 return PCIBIOS_SUCCESSFUL; 326 case 2: 327 cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val)); 328 return PCIBIOS_SUCCESSFUL; 329 case 1: 330 cvmx_write64_uint8(pci_addr.u64, val); 331 return PCIBIOS_SUCCESSFUL; 332 } 333 return PCIBIOS_FUNC_NOT_SUPPORTED; 334 } 335 336 337 static struct pci_ops octeon_pci_ops = { 338 octeon_read_config, 339 octeon_write_config, 340 }; 341 342 static struct resource octeon_pci_mem_resource = { 343 .start = 0, 344 .end = 0, 345 .name = "Octeon PCI MEM", 346 .flags = IORESOURCE_MEM, 347 }; 348 349 /* 350 * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI 351 * bridge 352 */ 353 static struct resource octeon_pci_io_resource = { 354 .start = 0x4000, 355 .end = OCTEON_PCI_IOSPACE_SIZE - 1, 356 .name = "Octeon PCI IO", 357 .flags = IORESOURCE_IO, 358 }; 359 360 static struct pci_controller octeon_pci_controller = { 361 .pci_ops = &octeon_pci_ops, 362 .mem_resource = &octeon_pci_mem_resource, 363 .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET, 364 .io_resource = &octeon_pci_io_resource, 365 .io_offset = 0, 366 .io_map_base = OCTEON_PCI_IOSPACE_BASE, 367 }; 368 369 370 /* 371 * Low level initialize the Octeon PCI controller 372 */ 373 static void octeon_pci_initialize(void) 374 { 375 union cvmx_pci_cfg01 cfg01; 376 union cvmx_npi_ctl_status ctl_status; 377 union cvmx_pci_ctl_status_2 ctl_status_2; 378 union cvmx_pci_cfg19 cfg19; 379 union cvmx_pci_cfg16 cfg16; 380 union cvmx_pci_cfg22 cfg22; 381 union cvmx_pci_cfg56 cfg56; 382 383 /* Reset the PCI Bus */ 384 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1); 385 cvmx_read_csr(CVMX_CIU_SOFT_PRST); 386 387 udelay(2000); /* Hold PCI reset for 2 ms */ 388 389 ctl_status.u64 = 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */ 390 ctl_status.s.max_word = 1; 391 ctl_status.s.timer = 1; 392 cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64); 393 394 /* Deassert PCI reset and advertize PCX Host Mode Device Capability 395 (64b) */ 396 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4); 397 cvmx_read_csr(CVMX_CIU_SOFT_PRST); 398 399 udelay(2000); /* Wait 2 ms after deasserting PCI reset */ 400 401 ctl_status_2.u32 = 0; 402 ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set 403 before any PCI reads. */ 404 ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */ 405 ctl_status_2.s.bar2_enb = 1; 406 ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */ 407 ctl_status_2.s.bar2_esx = 1; 408 ctl_status_2.s.pmo_amod = 1; /* Round robin priority */ 409 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) { 410 /* BAR1 hole */ 411 ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS; 412 ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */ 413 ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */ 414 ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */ 415 ctl_status_2.s.bb1 = 1; /* BAR1 is big */ 416 ctl_status_2.s.bb0 = 1; /* BAR0 is big */ 417 } 418 419 octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32); 420 udelay(2000); /* Wait 2 ms before doing PCI reads */ 421 422 ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2); 423 pr_notice("PCI Status: %s %s-bit\n", 424 ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI", 425 ctl_status_2.s.ap_64ad ? "64" : "32"); 426 427 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) { 428 union cvmx_pci_cnt_reg cnt_reg_start; 429 union cvmx_pci_cnt_reg cnt_reg_end; 430 unsigned long cycles, pci_clock; 431 432 cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG); 433 cycles = read_c0_cvmcount(); 434 udelay(1000); 435 cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG); 436 cycles = read_c0_cvmcount() - cycles; 437 pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) / 438 (cycles / (mips_hpt_frequency / 1000000)); 439 pr_notice("PCI Clock: %lu MHz\n", pci_clock); 440 } 441 442 /* 443 * TDOMC must be set to one in PCI mode. TDOMC should be set to 4 444 * in PCI-X mode to allow four oustanding splits. Otherwise, 445 * should not change from its reset value. Don't write PCI_CFG19 446 * in PCI mode (0x82000001 reset value), write it to 0x82000004 447 * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero. 448 * MRBCM -> must be one. 449 */ 450 if (ctl_status_2.s.ap_pcix) { 451 cfg19.u32 = 0; 452 /* 453 * Target Delayed/Split request outstanding maximum 454 * count. [1..31] and 0=32. NOTE: If the user 455 * programs these bits beyond the Designed Maximum 456 * outstanding count, then the designed maximum table 457 * depth will be used instead. No additional 458 * Deferred/Split transactions will be accepted if 459 * this outstanding maximum count is 460 * reached. Furthermore, no additional deferred/split 461 * transactions will be accepted if the I/O delay/ I/O 462 * Split Request outstanding maximum is reached. 463 */ 464 cfg19.s.tdomc = 4; 465 /* 466 * Master Deferred Read Request Outstanding Max Count 467 * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC 468 * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101 469 * 5 2 110 6 3 111 7 3 For example, if these bits are 470 * programmed to 100, the core can support 2 DAC 471 * cycles, 4 SAC cycles or a combination of 1 DAC and 472 * 2 SAC cycles. NOTE: For the PCI-X maximum 473 * outstanding split transactions, refer to 474 * CRE0[22:20]. 475 */ 476 cfg19.s.mdrrmc = 2; 477 /* 478 * Master Request (Memory Read) Byte Count/Byte Enable 479 * select. 0 = Byte Enables valid. In PCI mode, a 480 * burst transaction cannot be performed using Memory 481 * Read command=4?h6. 1 = DWORD Byte Count valid 482 * (default). In PCI Mode, the memory read byte 483 * enables are automatically generated by the 484 * core. Note: N3 Master Request transaction sizes are 485 * always determined through the 486 * am_attr[<35:32>|<7:0>] field. 487 */ 488 cfg19.s.mrbcm = 1; 489 octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32); 490 } 491 492 493 cfg01.u32 = 0; 494 cfg01.s.msae = 1; /* Memory Space Access Enable */ 495 cfg01.s.me = 1; /* Master Enable */ 496 cfg01.s.pee = 1; /* PERR# Enable */ 497 cfg01.s.see = 1; /* System Error Enable */ 498 cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */ 499 500 octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); 501 502 #ifdef USE_OCTEON_INTERNAL_ARBITER 503 /* 504 * When OCTEON is a PCI host, most systems will use OCTEON's 505 * internal arbiter, so must enable it before any PCI/PCI-X 506 * traffic can occur. 507 */ 508 { 509 union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg; 510 511 pci_int_arb_cfg.u64 = 0; 512 pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */ 513 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64); 514 } 515 #endif /* USE_OCTEON_INTERNAL_ARBITER */ 516 517 /* 518 * Preferrably written to 1 to set MLTD. [RDSATI,TRTAE, 519 * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to 520 * 1..7. 521 */ 522 cfg16.u32 = 0; 523 cfg16.s.mltd = 1; /* Master Latency Timer Disable */ 524 octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32); 525 526 /* 527 * Should be written to 0x4ff00. MTTV -> must be zero. 528 * FLUSH -> must be 1. MRV -> should be 0xFF. 529 */ 530 cfg22.u32 = 0; 531 /* Master Retry Value [1..255] and 0=infinite */ 532 cfg22.s.mrv = 0xff; 533 /* 534 * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper 535 * N3K operation. 536 */ 537 cfg22.s.flush = 1; 538 octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32); 539 540 /* 541 * MOST Indicates the maximum number of outstanding splits (in -1 542 * notation) when OCTEON is in PCI-X mode. PCI-X performance is 543 * affected by the MOST selection. Should generally be written 544 * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807, 545 * depending on the desired MOST of 3, 2, 1, or 0, respectively. 546 */ 547 cfg56.u32 = 0; 548 cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */ 549 cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */ 550 cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */ 551 cfg56.s.roe = 1; /* Relaxed Ordering Enable */ 552 cfg56.s.mmbc = 1; /* Maximum Memory Byte Count 553 [0=512B,1=1024B,2=2048B,3=4096B] */ 554 cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1 555 .. 7=32] */ 556 557 octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32); 558 559 /* 560 * Affects PCI performance when OCTEON services reads to its 561 * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are 562 * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and 563 * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700, 564 * these values need to be changed so they won't possibly prefetch off 565 * of the end of memory if PCI is DMAing a buffer at the end of 566 * memory. Note that these values differ from their reset values. 567 */ 568 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21); 569 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31); 570 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31); 571 } 572 573 574 /* 575 * Initialize the Octeon PCI controller 576 */ 577 static int __init octeon_pci_setup(void) 578 { 579 union cvmx_npi_mem_access_subidx mem_access; 580 int index; 581 582 /* Only these chips have PCI */ 583 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) 584 return 0; 585 586 /* Point pcibios_map_irq() to the PCI version of it */ 587 octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq; 588 589 /* Only use the big bars on chips that support it */ 590 if (OCTEON_IS_MODEL(OCTEON_CN31XX) || 591 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 592 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)) 593 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL; 594 else 595 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; 596 597 /* PCI I/O and PCI MEM values */ 598 set_io_port_base(OCTEON_PCI_IOSPACE_BASE); 599 ioport_resource.start = 0; 600 ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; 601 if (!octeon_is_pci_host()) { 602 pr_notice("Not in host mode, PCI Controller not initialized\n"); 603 return 0; 604 } 605 606 pr_notice("%s Octeon big bar support\n", 607 (octeon_dma_bar_type == 608 OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling"); 609 610 octeon_pci_initialize(); 611 612 mem_access.u64 = 0; 613 mem_access.s.esr = 1; /* Endian-Swap on read. */ 614 mem_access.s.esw = 1; /* Endian-Swap on write. */ 615 mem_access.s.nsr = 0; /* No-Snoop on read. */ 616 mem_access.s.nsw = 0; /* No-Snoop on write. */ 617 mem_access.s.ror = 0; /* Relax Read on read. */ 618 mem_access.s.row = 0; /* Relax Order on write. */ 619 mem_access.s.ba = 0; /* PCI Address bits [63:36]. */ 620 cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64); 621 622 /* 623 * Remap the Octeon BAR 2 above all 32 bit devices 624 * (0x8000000000ul). This is done here so it is remapped 625 * before the readl()'s below. We don't want BAR2 overlapping 626 * with BAR0/BAR1 during these reads. 627 */ 628 octeon_npi_write32(CVMX_NPI_PCI_CFG08, 629 (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull)); 630 octeon_npi_write32(CVMX_NPI_PCI_CFG09, 631 (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32)); 632 633 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) { 634 /* Remap the Octeon BAR 0 to 0-2GB */ 635 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0); 636 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0); 637 638 /* 639 * Remap the Octeon BAR 1 to map 2GB-4GB (minus the 640 * BAR 1 hole). 641 */ 642 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30); 643 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); 644 645 /* BAR1 movable mappings set for identity mapping */ 646 octeon_bar1_pci_phys = 0x80000000ull; 647 for (index = 0; index < 32; index++) { 648 union cvmx_pci_bar1_indexx bar1_index; 649 650 bar1_index.u32 = 0; 651 /* Address bits[35:22] sent to L2C */ 652 bar1_index.s.addr_idx = 653 (octeon_bar1_pci_phys >> 22) + index; 654 /* Don't put PCI accesses in L2. */ 655 bar1_index.s.ca = 1; 656 /* Endian Swap Mode */ 657 bar1_index.s.end_swp = 1; 658 /* Set '1' when the selected address range is valid. */ 659 bar1_index.s.addr_v = 1; 660 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 661 bar1_index.u32); 662 } 663 664 /* Devices go after BAR1 */ 665 octeon_pci_mem_resource.start = 666 OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) - 667 (OCTEON_PCI_BAR1_HOLE_SIZE << 20); 668 octeon_pci_mem_resource.end = 669 octeon_pci_mem_resource.start + (1ul << 30); 670 } else { 671 /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */ 672 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20); 673 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0); 674 675 /* Remap the Octeon BAR 1 to map 0-128MB */ 676 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0); 677 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); 678 679 /* BAR1 movable regions contiguous to cover the swiotlb */ 680 octeon_bar1_pci_phys = 681 virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1); 682 683 for (index = 0; index < 32; index++) { 684 union cvmx_pci_bar1_indexx bar1_index; 685 686 bar1_index.u32 = 0; 687 /* Address bits[35:22] sent to L2C */ 688 bar1_index.s.addr_idx = 689 (octeon_bar1_pci_phys >> 22) + index; 690 /* Don't put PCI accesses in L2. */ 691 bar1_index.s.ca = 1; 692 /* Endian Swap Mode */ 693 bar1_index.s.end_swp = 1; 694 /* Set '1' when the selected address range is valid. */ 695 bar1_index.s.addr_v = 1; 696 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 697 bar1_index.u32); 698 } 699 700 /* Devices go after BAR0 */ 701 octeon_pci_mem_resource.start = 702 OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) + 703 (4ul << 10); 704 octeon_pci_mem_resource.end = 705 octeon_pci_mem_resource.start + (1ul << 30); 706 } 707 708 register_pci_controller(&octeon_pci_controller); 709 710 /* 711 * Clear any errors that might be pending from before the bus 712 * was setup properly. 713 */ 714 cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1); 715 716 octeon_pci_dma_init(); 717 718 return 0; 719 } 720 721 arch_initcall(octeon_pci_setup); 722