101a6221aSDavid Daney /*
201a6221aSDavid Daney * This file is subject to the terms and conditions of the GNU General Public
301a6221aSDavid Daney * License. See the file "COPYING" in the main directory of this archive
401a6221aSDavid Daney * for more details.
501a6221aSDavid Daney *
601a6221aSDavid Daney * Copyright (C) 2005-2009 Cavium Networks
701a6221aSDavid Daney */
801a6221aSDavid Daney #include <linux/kernel.h>
901a6221aSDavid Daney #include <linux/init.h>
1001a6221aSDavid Daney #include <linux/pci.h>
1101a6221aSDavid Daney #include <linux/interrupt.h>
1201a6221aSDavid Daney #include <linux/time.h>
1301a6221aSDavid Daney #include <linux/delay.h>
14f65aad41SRalf Baechle #include <linux/platform_device.h>
15b93b2abcSDavid Daney #include <linux/swiotlb.h>
1601a6221aSDavid Daney
1701a6221aSDavid Daney #include <asm/time.h>
1801a6221aSDavid Daney
1901a6221aSDavid Daney #include <asm/octeon/octeon.h>
2001a6221aSDavid Daney #include <asm/octeon/cvmx-npi-defs.h>
2101a6221aSDavid Daney #include <asm/octeon/cvmx-pci-defs.h>
2201a6221aSDavid Daney #include <asm/octeon/pci-octeon.h>
2301a6221aSDavid Daney
2401a6221aSDavid Daney #define USE_OCTEON_INTERNAL_ARBITER
2501a6221aSDavid Daney
2601a6221aSDavid Daney /*
2701a6221aSDavid Daney * Octeon's PCI controller uses did=3, subdid=2 for PCI IO
2801a6221aSDavid Daney * addresses. Use PCI endian swapping 1 so no address swapping is
2901a6221aSDavid Daney * necessary. The Linux io routines will endian swap the data.
3001a6221aSDavid Daney */
3101a6221aSDavid Daney #define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull
3201a6221aSDavid Daney #define OCTEON_PCI_IOSPACE_SIZE (1ull<<32)
3301a6221aSDavid Daney
3401a6221aSDavid Daney /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
3501a6221aSDavid Daney #define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
3601a6221aSDavid Daney
37b93b2abcSDavid Daney u64 octeon_bar1_pci_phys;
38b93b2abcSDavid Daney
3901a6221aSDavid Daney /**
4001a6221aSDavid Daney * This is the bit decoding used for the Octeon PCI controller addresses
4101a6221aSDavid Daney */
4201a6221aSDavid Daney union octeon_pci_address {
4301a6221aSDavid Daney uint64_t u64;
4401a6221aSDavid Daney struct {
4501a6221aSDavid Daney uint64_t upper:2;
4601a6221aSDavid Daney uint64_t reserved:13;
4701a6221aSDavid Daney uint64_t io:1;
4801a6221aSDavid Daney uint64_t did:5;
4901a6221aSDavid Daney uint64_t subdid:3;
5001a6221aSDavid Daney uint64_t reserved2:4;
5101a6221aSDavid Daney uint64_t endian_swap:2;
5201a6221aSDavid Daney uint64_t reserved3:10;
5301a6221aSDavid Daney uint64_t bus:8;
5401a6221aSDavid Daney uint64_t dev:5;
5501a6221aSDavid Daney uint64_t func:3;
5601a6221aSDavid Daney uint64_t reg:8;
5701a6221aSDavid Daney } s;
5801a6221aSDavid Daney };
5901a6221aSDavid Daney
6019a8d6b7SLorenzo Pieralisi int (*octeon_pcibios_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
6101a6221aSDavid Daney enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
6201a6221aSDavid Daney
6301a6221aSDavid Daney /**
6401a6221aSDavid Daney * Map a PCI device to the appropriate interrupt line
6501a6221aSDavid Daney *
6601a6221aSDavid Daney * @dev: The Linux PCI device structure for the device to map
6701a6221aSDavid Daney * @slot: The slot number for this device on __BUS 0__. Linux
6801a6221aSDavid Daney * enumerates through all the bridges and figures out the
6901a6221aSDavid Daney * slot on Bus 0 where this device eventually hooks to.
7001a6221aSDavid Daney * @pin: The PCI interrupt pin read from the device, then swizzled
7101a6221aSDavid Daney * as it goes through each bridge.
7201a6221aSDavid Daney * Returns Interrupt number for the device
7301a6221aSDavid Daney */
pcibios_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)7419a8d6b7SLorenzo Pieralisi int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
7501a6221aSDavid Daney {
7601a6221aSDavid Daney if (octeon_pcibios_map_irq)
7701a6221aSDavid Daney return octeon_pcibios_map_irq(dev, slot, pin);
7801a6221aSDavid Daney else
7901a6221aSDavid Daney panic("octeon_pcibios_map_irq not set.");
8001a6221aSDavid Daney }
8101a6221aSDavid Daney
8201a6221aSDavid Daney
8301a6221aSDavid Daney /*
8401a6221aSDavid Daney * Called to perform platform specific PCI setup
8501a6221aSDavid Daney */
pcibios_plat_dev_init(struct pci_dev * dev)8601a6221aSDavid Daney int pcibios_plat_dev_init(struct pci_dev *dev)
8701a6221aSDavid Daney {
8801a6221aSDavid Daney uint16_t config;
8901a6221aSDavid Daney uint32_t dconfig;
9001a6221aSDavid Daney int pos;
9101a6221aSDavid Daney /*
9201a6221aSDavid Daney * Force the Cache line setting to 64 bytes. The standard
9301a6221aSDavid Daney * Linux bus scan doesn't seem to set it. Octeon really has
9401a6221aSDavid Daney * 128 byte lines, but Intel bridges get really upset if you
9501a6221aSDavid Daney * try and set values above 64 bytes. Value is specified in
9601a6221aSDavid Daney * 32bit words.
9701a6221aSDavid Daney */
9801a6221aSDavid Daney pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
9901a6221aSDavid Daney /* Set latency timers for all devices */
10053efc98eSDavid Daney pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
10101a6221aSDavid Daney
10201a6221aSDavid Daney /* Enable reporting System errors and parity errors on all devices */
10301a6221aSDavid Daney /* Enable parity checking and error reporting */
10401a6221aSDavid Daney pci_read_config_word(dev, PCI_COMMAND, &config);
10501a6221aSDavid Daney config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10601a6221aSDavid Daney pci_write_config_word(dev, PCI_COMMAND, config);
10701a6221aSDavid Daney
10801a6221aSDavid Daney if (dev->subordinate) {
10901a6221aSDavid Daney /* Set latency timers on sub bridges */
11053efc98eSDavid Daney pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64);
11101a6221aSDavid Daney /* More bridge error detection */
11201a6221aSDavid Daney pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
11301a6221aSDavid Daney config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
11401a6221aSDavid Daney pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
11501a6221aSDavid Daney }
11601a6221aSDavid Daney
11701a6221aSDavid Daney /* Enable the PCIe normal error reporting */
11839a3612eSJiang Liu config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
11953efc98eSDavid Daney config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
12053efc98eSDavid Daney config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */
12153efc98eSDavid Daney config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */
12239a3612eSJiang Liu pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
12301a6221aSDavid Daney
12401a6221aSDavid Daney /* Find the Advanced Error Reporting capability */
12501a6221aSDavid Daney pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
12601a6221aSDavid Daney if (pos) {
12701a6221aSDavid Daney /* Clear Uncorrectable Error Status */
12801a6221aSDavid Daney pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
12901a6221aSDavid Daney &dconfig);
13001a6221aSDavid Daney pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
13101a6221aSDavid Daney dconfig);
13201a6221aSDavid Daney /* Enable reporting of all uncorrectable errors */
13301a6221aSDavid Daney /* Uncorrectable Error Mask - turned on bits disable errors */
13401a6221aSDavid Daney pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
13501a6221aSDavid Daney /*
13601a6221aSDavid Daney * Leave severity at HW default. This only controls if
13701a6221aSDavid Daney * errors are reported as uncorrectable or
13801a6221aSDavid Daney * correctable, not if the error is reported.
13901a6221aSDavid Daney */
14001a6221aSDavid Daney /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
14101a6221aSDavid Daney /* Clear Correctable Error Status */
14201a6221aSDavid Daney pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
14301a6221aSDavid Daney pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
14401a6221aSDavid Daney /* Enable reporting of all correctable errors */
14501a6221aSDavid Daney /* Correctable Error Mask - turned on bits disable errors */
14601a6221aSDavid Daney pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
14701a6221aSDavid Daney /* Advanced Error Capabilities */
14801a6221aSDavid Daney pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
14901a6221aSDavid Daney /* ECRC Generation Enable */
15001a6221aSDavid Daney if (config & PCI_ERR_CAP_ECRC_GENC)
15101a6221aSDavid Daney config |= PCI_ERR_CAP_ECRC_GENE;
15201a6221aSDavid Daney /* ECRC Check Enable */
15301a6221aSDavid Daney if (config & PCI_ERR_CAP_ECRC_CHKC)
15401a6221aSDavid Daney config |= PCI_ERR_CAP_ECRC_CHKE;
15501a6221aSDavid Daney pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
15601a6221aSDavid Daney /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
15701a6221aSDavid Daney /* Report all errors to the root complex */
15801a6221aSDavid Daney pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
15901a6221aSDavid Daney PCI_ERR_ROOT_CMD_COR_EN |
16001a6221aSDavid Daney PCI_ERR_ROOT_CMD_NONFATAL_EN |
16101a6221aSDavid Daney PCI_ERR_ROOT_CMD_FATAL_EN);
16201a6221aSDavid Daney /* Clear the Root status register */
16301a6221aSDavid Daney pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
16401a6221aSDavid Daney pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
16501a6221aSDavid Daney }
16601a6221aSDavid Daney
16701a6221aSDavid Daney return 0;
16801a6221aSDavid Daney }
16901a6221aSDavid Daney
17001a6221aSDavid Daney /**
17101a6221aSDavid Daney * Return the mapping of PCI device number to IRQ line. Each
17201a6221aSDavid Daney * character in the return string represents the interrupt
17301a6221aSDavid Daney * line for the device at that position. Device 1 maps to the
17401a6221aSDavid Daney * first character, etc. The characters A-D are used for PCI
17501a6221aSDavid Daney * interrupts.
17601a6221aSDavid Daney *
17701a6221aSDavid Daney * Returns PCI interrupt mapping
17801a6221aSDavid Daney */
octeon_get_pci_interrupts(void)17901a6221aSDavid Daney const char *octeon_get_pci_interrupts(void)
18001a6221aSDavid Daney {
18101a6221aSDavid Daney /*
18201a6221aSDavid Daney * Returning an empty string causes the interrupts to be
18301a6221aSDavid Daney * routed based on the PCI specification. From the PCI spec:
18401a6221aSDavid Daney *
18501a6221aSDavid Daney * INTA# of Device Number 0 is connected to IRQW on the system
18601a6221aSDavid Daney * board. (Device Number has no significance regarding being
18701a6221aSDavid Daney * located on the system board or in a connector.) INTA# of
18801a6221aSDavid Daney * Device Number 1 is connected to IRQX on the system
18901a6221aSDavid Daney * board. INTA# of Device Number 2 is connected to IRQY on the
19001a6221aSDavid Daney * system board. INTA# of Device Number 3 is connected to IRQZ
19101a6221aSDavid Daney * on the system board. The table below describes how each
19201a6221aSDavid Daney * agent's INTx# lines are connected to the system board
19301a6221aSDavid Daney * interrupt lines. The following equation can be used to
19401a6221aSDavid Daney * determine to which INTx# signal on the system board a given
19501a6221aSDavid Daney * device's INTx# line(s) is connected.
19601a6221aSDavid Daney *
19701a6221aSDavid Daney * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0,
19801a6221aSDavid Daney * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I =
19901a6221aSDavid Daney * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and
20001a6221aSDavid Daney * INTD# = 3)
20101a6221aSDavid Daney */
202e6e5b7b6SAaro Koskinen if (of_machine_is_compatible("dlink,dsr-500n"))
203e6e5b7b6SAaro Koskinen return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
20401a6221aSDavid Daney switch (octeon_bootinfo->board_type) {
20501a6221aSDavid Daney case CVMX_BOARD_TYPE_NAO38:
20601a6221aSDavid Daney /* This is really the NAC38 */
20701a6221aSDavid Daney return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
20801a6221aSDavid Daney case CVMX_BOARD_TYPE_EBH3100:
20901a6221aSDavid Daney case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
21001a6221aSDavid Daney case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
21101a6221aSDavid Daney return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
21201a6221aSDavid Daney case CVMX_BOARD_TYPE_BBGW_REF:
21301a6221aSDavid Daney return "AABCD";
214b083518cSAaro Koskinen case CVMX_BOARD_TYPE_CUST_DSR1000N:
215b083518cSAaro Koskinen return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
2162fe06260SRoel Kluin case CVMX_BOARD_TYPE_THUNDER:
2172fe06260SRoel Kluin case CVMX_BOARD_TYPE_EBH3000:
21801a6221aSDavid Daney default:
21901a6221aSDavid Daney return "";
22001a6221aSDavid Daney }
22101a6221aSDavid Daney }
22201a6221aSDavid Daney
22301a6221aSDavid Daney /**
22401a6221aSDavid Daney * Map a PCI device to the appropriate interrupt line
22501a6221aSDavid Daney *
22601a6221aSDavid Daney * @dev: The Linux PCI device structure for the device to map
22701a6221aSDavid Daney * @slot: The slot number for this device on __BUS 0__. Linux
22801a6221aSDavid Daney * enumerates through all the bridges and figures out the
22901a6221aSDavid Daney * slot on Bus 0 where this device eventually hooks to.
23001a6221aSDavid Daney * @pin: The PCI interrupt pin read from the device, then swizzled
23101a6221aSDavid Daney * as it goes through each bridge.
23201a6221aSDavid Daney * Returns Interrupt number for the device
23301a6221aSDavid Daney */
octeon_pci_pcibios_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)23401a6221aSDavid Daney int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
23501a6221aSDavid Daney u8 slot, u8 pin)
23601a6221aSDavid Daney {
23701a6221aSDavid Daney int irq_num;
23801a6221aSDavid Daney const char *interrupts;
23901a6221aSDavid Daney int dev_num;
24001a6221aSDavid Daney
24101a6221aSDavid Daney /* Get the board specific interrupt mapping */
24201a6221aSDavid Daney interrupts = octeon_get_pci_interrupts();
24301a6221aSDavid Daney
24401a6221aSDavid Daney dev_num = dev->devfn >> 3;
24501a6221aSDavid Daney if (dev_num < strlen(interrupts))
24601a6221aSDavid Daney irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +
24701a6221aSDavid Daney OCTEON_IRQ_PCI_INT0;
24801a6221aSDavid Daney else
24901a6221aSDavid Daney irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;
25001a6221aSDavid Daney return irq_num;
25101a6221aSDavid Daney }
25201a6221aSDavid Daney
25301a6221aSDavid Daney
25401a6221aSDavid Daney /*
25501a6221aSDavid Daney * Read a value from configuration space
25601a6221aSDavid Daney */
octeon_read_config(struct pci_bus * bus,unsigned int devfn,int reg,int size,u32 * val)25701a6221aSDavid Daney static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
25801a6221aSDavid Daney int reg, int size, u32 *val)
25901a6221aSDavid Daney {
26001a6221aSDavid Daney union octeon_pci_address pci_addr;
26101a6221aSDavid Daney
26201a6221aSDavid Daney pci_addr.u64 = 0;
26301a6221aSDavid Daney pci_addr.s.upper = 2;
26401a6221aSDavid Daney pci_addr.s.io = 1;
26501a6221aSDavid Daney pci_addr.s.did = 3;
26601a6221aSDavid Daney pci_addr.s.subdid = 1;
26701a6221aSDavid Daney pci_addr.s.endian_swap = 1;
26801a6221aSDavid Daney pci_addr.s.bus = bus->number;
26901a6221aSDavid Daney pci_addr.s.dev = devfn >> 3;
27001a6221aSDavid Daney pci_addr.s.func = devfn & 0x7;
27101a6221aSDavid Daney pci_addr.s.reg = reg;
27201a6221aSDavid Daney
27301a6221aSDavid Daney switch (size) {
27401a6221aSDavid Daney case 4:
27501a6221aSDavid Daney *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
27601a6221aSDavid Daney return PCIBIOS_SUCCESSFUL;
27701a6221aSDavid Daney case 2:
27801a6221aSDavid Daney *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64));
27901a6221aSDavid Daney return PCIBIOS_SUCCESSFUL;
28001a6221aSDavid Daney case 1:
28101a6221aSDavid Daney *val = cvmx_read64_uint8(pci_addr.u64);
28201a6221aSDavid Daney return PCIBIOS_SUCCESSFUL;
28301a6221aSDavid Daney }
28401a6221aSDavid Daney return PCIBIOS_FUNC_NOT_SUPPORTED;
28501a6221aSDavid Daney }
28601a6221aSDavid Daney
28701a6221aSDavid Daney
28801a6221aSDavid Daney /*
28901a6221aSDavid Daney * Write a value to PCI configuration space
29001a6221aSDavid Daney */
octeon_write_config(struct pci_bus * bus,unsigned int devfn,int reg,int size,u32 val)29101a6221aSDavid Daney static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
29201a6221aSDavid Daney int reg, int size, u32 val)
29301a6221aSDavid Daney {
29401a6221aSDavid Daney union octeon_pci_address pci_addr;
29501a6221aSDavid Daney
29601a6221aSDavid Daney pci_addr.u64 = 0;
29701a6221aSDavid Daney pci_addr.s.upper = 2;
29801a6221aSDavid Daney pci_addr.s.io = 1;
29901a6221aSDavid Daney pci_addr.s.did = 3;
30001a6221aSDavid Daney pci_addr.s.subdid = 1;
30101a6221aSDavid Daney pci_addr.s.endian_swap = 1;
30201a6221aSDavid Daney pci_addr.s.bus = bus->number;
30301a6221aSDavid Daney pci_addr.s.dev = devfn >> 3;
30401a6221aSDavid Daney pci_addr.s.func = devfn & 0x7;
30501a6221aSDavid Daney pci_addr.s.reg = reg;
30601a6221aSDavid Daney
30701a6221aSDavid Daney switch (size) {
30801a6221aSDavid Daney case 4:
30901a6221aSDavid Daney cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
31001a6221aSDavid Daney return PCIBIOS_SUCCESSFUL;
31101a6221aSDavid Daney case 2:
31201a6221aSDavid Daney cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val));
31301a6221aSDavid Daney return PCIBIOS_SUCCESSFUL;
31401a6221aSDavid Daney case 1:
31501a6221aSDavid Daney cvmx_write64_uint8(pci_addr.u64, val);
31601a6221aSDavid Daney return PCIBIOS_SUCCESSFUL;
31701a6221aSDavid Daney }
31801a6221aSDavid Daney return PCIBIOS_FUNC_NOT_SUPPORTED;
31901a6221aSDavid Daney }
32001a6221aSDavid Daney
32101a6221aSDavid Daney
32201a6221aSDavid Daney static struct pci_ops octeon_pci_ops = {
3237b09777cSRob Herring .read = octeon_read_config,
3247b09777cSRob Herring .write = octeon_write_config,
32501a6221aSDavid Daney };
32601a6221aSDavid Daney
32701a6221aSDavid Daney static struct resource octeon_pci_mem_resource = {
32801a6221aSDavid Daney .start = 0,
32901a6221aSDavid Daney .end = 0,
33001a6221aSDavid Daney .name = "Octeon PCI MEM",
33101a6221aSDavid Daney .flags = IORESOURCE_MEM,
33201a6221aSDavid Daney };
33301a6221aSDavid Daney
33401a6221aSDavid Daney /*
33501a6221aSDavid Daney * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI
33601a6221aSDavid Daney * bridge
33701a6221aSDavid Daney */
33801a6221aSDavid Daney static struct resource octeon_pci_io_resource = {
33901a6221aSDavid Daney .start = 0x4000,
34001a6221aSDavid Daney .end = OCTEON_PCI_IOSPACE_SIZE - 1,
34101a6221aSDavid Daney .name = "Octeon PCI IO",
34201a6221aSDavid Daney .flags = IORESOURCE_IO,
34301a6221aSDavid Daney };
34401a6221aSDavid Daney
34501a6221aSDavid Daney static struct pci_controller octeon_pci_controller = {
34601a6221aSDavid Daney .pci_ops = &octeon_pci_ops,
34701a6221aSDavid Daney .mem_resource = &octeon_pci_mem_resource,
34801a6221aSDavid Daney .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET,
34901a6221aSDavid Daney .io_resource = &octeon_pci_io_resource,
35001a6221aSDavid Daney .io_offset = 0,
35101a6221aSDavid Daney .io_map_base = OCTEON_PCI_IOSPACE_BASE,
35201a6221aSDavid Daney };
35301a6221aSDavid Daney
35401a6221aSDavid Daney
35501a6221aSDavid Daney /*
35601a6221aSDavid Daney * Low level initialize the Octeon PCI controller
35701a6221aSDavid Daney */
octeon_pci_initialize(void)35801a6221aSDavid Daney static void octeon_pci_initialize(void)
35901a6221aSDavid Daney {
36001a6221aSDavid Daney union cvmx_pci_cfg01 cfg01;
36101a6221aSDavid Daney union cvmx_npi_ctl_status ctl_status;
36201a6221aSDavid Daney union cvmx_pci_ctl_status_2 ctl_status_2;
36301a6221aSDavid Daney union cvmx_pci_cfg19 cfg19;
36401a6221aSDavid Daney union cvmx_pci_cfg16 cfg16;
36501a6221aSDavid Daney union cvmx_pci_cfg22 cfg22;
36601a6221aSDavid Daney union cvmx_pci_cfg56 cfg56;
36701a6221aSDavid Daney
36801a6221aSDavid Daney /* Reset the PCI Bus */
36901a6221aSDavid Daney cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
37001a6221aSDavid Daney cvmx_read_csr(CVMX_CIU_SOFT_PRST);
37101a6221aSDavid Daney
37201a6221aSDavid Daney udelay(2000); /* Hold PCI reset for 2 ms */
37301a6221aSDavid Daney
37401a6221aSDavid Daney ctl_status.u64 = 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */
37501a6221aSDavid Daney ctl_status.s.max_word = 1;
37601a6221aSDavid Daney ctl_status.s.timer = 1;
37701a6221aSDavid Daney cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
37801a6221aSDavid Daney
37901a6221aSDavid Daney /* Deassert PCI reset and advertize PCX Host Mode Device Capability
38001a6221aSDavid Daney (64b) */
38101a6221aSDavid Daney cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
38201a6221aSDavid Daney cvmx_read_csr(CVMX_CIU_SOFT_PRST);
38301a6221aSDavid Daney
38401a6221aSDavid Daney udelay(2000); /* Wait 2 ms after deasserting PCI reset */
38501a6221aSDavid Daney
38601a6221aSDavid Daney ctl_status_2.u32 = 0;
38701a6221aSDavid Daney ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set
38801a6221aSDavid Daney before any PCI reads. */
38901a6221aSDavid Daney ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */
39001a6221aSDavid Daney ctl_status_2.s.bar2_enb = 1;
39101a6221aSDavid Daney ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */
39201a6221aSDavid Daney ctl_status_2.s.bar2_esx = 1;
39301a6221aSDavid Daney ctl_status_2.s.pmo_amod = 1; /* Round robin priority */
39401a6221aSDavid Daney if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
39501a6221aSDavid Daney /* BAR1 hole */
39601a6221aSDavid Daney ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
39701a6221aSDavid Daney ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */
39801a6221aSDavid Daney ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */
39901a6221aSDavid Daney ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */
40001a6221aSDavid Daney ctl_status_2.s.bb1 = 1; /* BAR1 is big */
40101a6221aSDavid Daney ctl_status_2.s.bb0 = 1; /* BAR0 is big */
40201a6221aSDavid Daney }
40301a6221aSDavid Daney
40401a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
40501a6221aSDavid Daney udelay(2000); /* Wait 2 ms before doing PCI reads */
40601a6221aSDavid Daney
40701a6221aSDavid Daney ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
40801a6221aSDavid Daney pr_notice("PCI Status: %s %s-bit\n",
40901a6221aSDavid Daney ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
41001a6221aSDavid Daney ctl_status_2.s.ap_64ad ? "64" : "32");
41101a6221aSDavid Daney
41201a6221aSDavid Daney if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
41301a6221aSDavid Daney union cvmx_pci_cnt_reg cnt_reg_start;
41401a6221aSDavid Daney union cvmx_pci_cnt_reg cnt_reg_end;
41501a6221aSDavid Daney unsigned long cycles, pci_clock;
41601a6221aSDavid Daney
41701a6221aSDavid Daney cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
41801a6221aSDavid Daney cycles = read_c0_cvmcount();
41901a6221aSDavid Daney udelay(1000);
42001a6221aSDavid Daney cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
42101a6221aSDavid Daney cycles = read_c0_cvmcount() - cycles;
42201a6221aSDavid Daney pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
42301a6221aSDavid Daney (cycles / (mips_hpt_frequency / 1000000));
42401a6221aSDavid Daney pr_notice("PCI Clock: %lu MHz\n", pci_clock);
42501a6221aSDavid Daney }
42601a6221aSDavid Daney
42701a6221aSDavid Daney /*
42801a6221aSDavid Daney * TDOMC must be set to one in PCI mode. TDOMC should be set to 4
42925985edcSLucas De Marchi * in PCI-X mode to allow four outstanding splits. Otherwise,
43001a6221aSDavid Daney * should not change from its reset value. Don't write PCI_CFG19
43101a6221aSDavid Daney * in PCI mode (0x82000001 reset value), write it to 0x82000004
43201a6221aSDavid Daney * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero.
43301a6221aSDavid Daney * MRBCM -> must be one.
43401a6221aSDavid Daney */
43501a6221aSDavid Daney if (ctl_status_2.s.ap_pcix) {
43601a6221aSDavid Daney cfg19.u32 = 0;
43701a6221aSDavid Daney /*
43801a6221aSDavid Daney * Target Delayed/Split request outstanding maximum
43901a6221aSDavid Daney * count. [1..31] and 0=32. NOTE: If the user
44001a6221aSDavid Daney * programs these bits beyond the Designed Maximum
44101a6221aSDavid Daney * outstanding count, then the designed maximum table
44201a6221aSDavid Daney * depth will be used instead. No additional
44301a6221aSDavid Daney * Deferred/Split transactions will be accepted if
44401a6221aSDavid Daney * this outstanding maximum count is
44501a6221aSDavid Daney * reached. Furthermore, no additional deferred/split
44601a6221aSDavid Daney * transactions will be accepted if the I/O delay/ I/O
44701a6221aSDavid Daney * Split Request outstanding maximum is reached.
44801a6221aSDavid Daney */
44901a6221aSDavid Daney cfg19.s.tdomc = 4;
45001a6221aSDavid Daney /*
45101a6221aSDavid Daney * Master Deferred Read Request Outstanding Max Count
45201a6221aSDavid Daney * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC
45301a6221aSDavid Daney * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
45401a6221aSDavid Daney * 5 2 110 6 3 111 7 3 For example, if these bits are
45501a6221aSDavid Daney * programmed to 100, the core can support 2 DAC
45601a6221aSDavid Daney * cycles, 4 SAC cycles or a combination of 1 DAC and
45701a6221aSDavid Daney * 2 SAC cycles. NOTE: For the PCI-X maximum
45801a6221aSDavid Daney * outstanding split transactions, refer to
45901a6221aSDavid Daney * CRE0[22:20].
46001a6221aSDavid Daney */
46101a6221aSDavid Daney cfg19.s.mdrrmc = 2;
46201a6221aSDavid Daney /*
46301a6221aSDavid Daney * Master Request (Memory Read) Byte Count/Byte Enable
46401a6221aSDavid Daney * select. 0 = Byte Enables valid. In PCI mode, a
46501a6221aSDavid Daney * burst transaction cannot be performed using Memory
46601a6221aSDavid Daney * Read command=4?h6. 1 = DWORD Byte Count valid
46701a6221aSDavid Daney * (default). In PCI Mode, the memory read byte
46801a6221aSDavid Daney * enables are automatically generated by the
46901a6221aSDavid Daney * core. Note: N3 Master Request transaction sizes are
47001a6221aSDavid Daney * always determined through the
47101a6221aSDavid Daney * am_attr[<35:32>|<7:0>] field.
47201a6221aSDavid Daney */
47301a6221aSDavid Daney cfg19.s.mrbcm = 1;
47401a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
47501a6221aSDavid Daney }
47601a6221aSDavid Daney
47701a6221aSDavid Daney
47801a6221aSDavid Daney cfg01.u32 = 0;
47901a6221aSDavid Daney cfg01.s.msae = 1; /* Memory Space Access Enable */
48001a6221aSDavid Daney cfg01.s.me = 1; /* Master Enable */
48101a6221aSDavid Daney cfg01.s.pee = 1; /* PERR# Enable */
48201a6221aSDavid Daney cfg01.s.see = 1; /* System Error Enable */
48301a6221aSDavid Daney cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */
48401a6221aSDavid Daney
48501a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
48601a6221aSDavid Daney
48701a6221aSDavid Daney #ifdef USE_OCTEON_INTERNAL_ARBITER
48801a6221aSDavid Daney /*
48901a6221aSDavid Daney * When OCTEON is a PCI host, most systems will use OCTEON's
49001a6221aSDavid Daney * internal arbiter, so must enable it before any PCI/PCI-X
49101a6221aSDavid Daney * traffic can occur.
49201a6221aSDavid Daney */
49301a6221aSDavid Daney {
49401a6221aSDavid Daney union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
49501a6221aSDavid Daney
49601a6221aSDavid Daney pci_int_arb_cfg.u64 = 0;
49701a6221aSDavid Daney pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */
49801a6221aSDavid Daney cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
49901a6221aSDavid Daney }
50001a6221aSDavid Daney #endif /* USE_OCTEON_INTERNAL_ARBITER */
50101a6221aSDavid Daney
50201a6221aSDavid Daney /*
50325985edcSLucas De Marchi * Preferably written to 1 to set MLTD. [RDSATI,TRTAE,
50401a6221aSDavid Daney * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to
50501a6221aSDavid Daney * 1..7.
50601a6221aSDavid Daney */
50701a6221aSDavid Daney cfg16.u32 = 0;
50801a6221aSDavid Daney cfg16.s.mltd = 1; /* Master Latency Timer Disable */
50901a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
51001a6221aSDavid Daney
51101a6221aSDavid Daney /*
51201a6221aSDavid Daney * Should be written to 0x4ff00. MTTV -> must be zero.
51301a6221aSDavid Daney * FLUSH -> must be 1. MRV -> should be 0xFF.
51401a6221aSDavid Daney */
51501a6221aSDavid Daney cfg22.u32 = 0;
51601a6221aSDavid Daney /* Master Retry Value [1..255] and 0=infinite */
51701a6221aSDavid Daney cfg22.s.mrv = 0xff;
51801a6221aSDavid Daney /*
51901a6221aSDavid Daney * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper
52001a6221aSDavid Daney * N3K operation.
52101a6221aSDavid Daney */
52201a6221aSDavid Daney cfg22.s.flush = 1;
52301a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
52401a6221aSDavid Daney
52501a6221aSDavid Daney /*
52601a6221aSDavid Daney * MOST Indicates the maximum number of outstanding splits (in -1
52701a6221aSDavid Daney * notation) when OCTEON is in PCI-X mode. PCI-X performance is
52801a6221aSDavid Daney * affected by the MOST selection. Should generally be written
52901a6221aSDavid Daney * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807,
53001a6221aSDavid Daney * depending on the desired MOST of 3, 2, 1, or 0, respectively.
53101a6221aSDavid Daney */
53201a6221aSDavid Daney cfg56.u32 = 0;
53301a6221aSDavid Daney cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */
53401a6221aSDavid Daney cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */
53501a6221aSDavid Daney cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */
53601a6221aSDavid Daney cfg56.s.roe = 1; /* Relaxed Ordering Enable */
53701a6221aSDavid Daney cfg56.s.mmbc = 1; /* Maximum Memory Byte Count
53801a6221aSDavid Daney [0=512B,1=1024B,2=2048B,3=4096B] */
53901a6221aSDavid Daney cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1
54001a6221aSDavid Daney .. 7=32] */
54101a6221aSDavid Daney
54201a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
54301a6221aSDavid Daney
54401a6221aSDavid Daney /*
54501a6221aSDavid Daney * Affects PCI performance when OCTEON services reads to its
54601a6221aSDavid Daney * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are
54701a6221aSDavid Daney * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
54801a6221aSDavid Daney * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
54901a6221aSDavid Daney * these values need to be changed so they won't possibly prefetch off
55001a6221aSDavid Daney * of the end of memory if PCI is DMAing a buffer at the end of
55101a6221aSDavid Daney * memory. Note that these values differ from their reset values.
55201a6221aSDavid Daney */
55301a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
55401a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
55501a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
55601a6221aSDavid Daney }
55701a6221aSDavid Daney
55801a6221aSDavid Daney
55901a6221aSDavid Daney /*
56001a6221aSDavid Daney * Initialize the Octeon PCI controller
56101a6221aSDavid Daney */
octeon_pci_setup(void)56201a6221aSDavid Daney static int __init octeon_pci_setup(void)
56301a6221aSDavid Daney {
56401a6221aSDavid Daney union cvmx_npi_mem_access_subidx mem_access;
56501a6221aSDavid Daney int index;
56601a6221aSDavid Daney
56701a6221aSDavid Daney /* Only these chips have PCI */
56801a6221aSDavid Daney if (octeon_has_feature(OCTEON_FEATURE_PCIE))
56901a6221aSDavid Daney return 0;
57001a6221aSDavid Daney
571dcf300a6SAaro Koskinen if (!octeon_is_pci_host()) {
572dcf300a6SAaro Koskinen pr_notice("Not in host mode, PCI Controller not initialized\n");
573dcf300a6SAaro Koskinen return 0;
574dcf300a6SAaro Koskinen }
575dcf300a6SAaro Koskinen
57601a6221aSDavid Daney /* Point pcibios_map_irq() to the PCI version of it */
57701a6221aSDavid Daney octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq;
57801a6221aSDavid Daney
57901a6221aSDavid Daney /* Only use the big bars on chips that support it */
58001a6221aSDavid Daney if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
58101a6221aSDavid Daney OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
58201a6221aSDavid Daney OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
58301a6221aSDavid Daney octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL;
58401a6221aSDavid Daney else
58501a6221aSDavid Daney octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
58601a6221aSDavid Daney
587d8b74276SAaro Koskinen /* PCI I/O and PCI MEM values */
588d8b74276SAaro Koskinen set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
589d8b74276SAaro Koskinen ioport_resource.start = 0;
590d8b74276SAaro Koskinen ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
591d8b74276SAaro Koskinen
59201a6221aSDavid Daney pr_notice("%s Octeon big bar support\n",
59301a6221aSDavid Daney (octeon_dma_bar_type ==
59401a6221aSDavid Daney OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
59501a6221aSDavid Daney
59601a6221aSDavid Daney octeon_pci_initialize();
59701a6221aSDavid Daney
59801a6221aSDavid Daney mem_access.u64 = 0;
59901a6221aSDavid Daney mem_access.s.esr = 1; /* Endian-Swap on read. */
60001a6221aSDavid Daney mem_access.s.esw = 1; /* Endian-Swap on write. */
60101a6221aSDavid Daney mem_access.s.nsr = 0; /* No-Snoop on read. */
60201a6221aSDavid Daney mem_access.s.nsw = 0; /* No-Snoop on write. */
60301a6221aSDavid Daney mem_access.s.ror = 0; /* Relax Read on read. */
60401a6221aSDavid Daney mem_access.s.row = 0; /* Relax Order on write. */
60501a6221aSDavid Daney mem_access.s.ba = 0; /* PCI Address bits [63:36]. */
60601a6221aSDavid Daney cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
60701a6221aSDavid Daney
60801a6221aSDavid Daney /*
60901a6221aSDavid Daney * Remap the Octeon BAR 2 above all 32 bit devices
61001a6221aSDavid Daney * (0x8000000000ul). This is done here so it is remapped
61101a6221aSDavid Daney * before the readl()'s below. We don't want BAR2 overlapping
61201a6221aSDavid Daney * with BAR0/BAR1 during these reads.
61301a6221aSDavid Daney */
614b93b2abcSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG08,
615b93b2abcSDavid Daney (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull));
616b93b2abcSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG09,
617b93b2abcSDavid Daney (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32));
61801a6221aSDavid Daney
61901a6221aSDavid Daney if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
62001a6221aSDavid Daney /* Remap the Octeon BAR 0 to 0-2GB */
62101a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0);
62201a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
62301a6221aSDavid Daney
62401a6221aSDavid Daney /*
62501a6221aSDavid Daney * Remap the Octeon BAR 1 to map 2GB-4GB (minus the
62601a6221aSDavid Daney * BAR 1 hole).
62701a6221aSDavid Daney */
62801a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
62901a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
63001a6221aSDavid Daney
631b93b2abcSDavid Daney /* BAR1 movable mappings set for identity mapping */
632b93b2abcSDavid Daney octeon_bar1_pci_phys = 0x80000000ull;
633b93b2abcSDavid Daney for (index = 0; index < 32; index++) {
634b93b2abcSDavid Daney union cvmx_pci_bar1_indexx bar1_index;
635b93b2abcSDavid Daney
636b93b2abcSDavid Daney bar1_index.u32 = 0;
637b93b2abcSDavid Daney /* Address bits[35:22] sent to L2C */
638b93b2abcSDavid Daney bar1_index.s.addr_idx =
639b93b2abcSDavid Daney (octeon_bar1_pci_phys >> 22) + index;
640b93b2abcSDavid Daney /* Don't put PCI accesses in L2. */
641b93b2abcSDavid Daney bar1_index.s.ca = 1;
642b93b2abcSDavid Daney /* Endian Swap Mode */
643b93b2abcSDavid Daney bar1_index.s.end_swp = 1;
644b93b2abcSDavid Daney /* Set '1' when the selected address range is valid. */
645b93b2abcSDavid Daney bar1_index.s.addr_v = 1;
646b93b2abcSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
647b93b2abcSDavid Daney bar1_index.u32);
648b93b2abcSDavid Daney }
649b93b2abcSDavid Daney
65001a6221aSDavid Daney /* Devices go after BAR1 */
65101a6221aSDavid Daney octeon_pci_mem_resource.start =
65201a6221aSDavid Daney OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
65301a6221aSDavid Daney (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
65401a6221aSDavid Daney octeon_pci_mem_resource.end =
65501a6221aSDavid Daney octeon_pci_mem_resource.start + (1ul << 30);
65601a6221aSDavid Daney } else {
65701a6221aSDavid Daney /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */
65801a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
65901a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
66001a6221aSDavid Daney
66101a6221aSDavid Daney /* Remap the Octeon BAR 1 to map 0-128MB */
66201a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
66301a6221aSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
66401a6221aSDavid Daney
665b93b2abcSDavid Daney /* BAR1 movable regions contiguous to cover the swiotlb */
666b93b2abcSDavid Daney octeon_bar1_pci_phys =
667*05ee7741SPetr Tesarik default_swiotlb_base() & ~((1ull << 22) - 1);
668b93b2abcSDavid Daney
669b93b2abcSDavid Daney for (index = 0; index < 32; index++) {
670b93b2abcSDavid Daney union cvmx_pci_bar1_indexx bar1_index;
671b93b2abcSDavid Daney
672b93b2abcSDavid Daney bar1_index.u32 = 0;
673b93b2abcSDavid Daney /* Address bits[35:22] sent to L2C */
674b93b2abcSDavid Daney bar1_index.s.addr_idx =
675b93b2abcSDavid Daney (octeon_bar1_pci_phys >> 22) + index;
676b93b2abcSDavid Daney /* Don't put PCI accesses in L2. */
677b93b2abcSDavid Daney bar1_index.s.ca = 1;
678b93b2abcSDavid Daney /* Endian Swap Mode */
679b93b2abcSDavid Daney bar1_index.s.end_swp = 1;
680b93b2abcSDavid Daney /* Set '1' when the selected address range is valid. */
681b93b2abcSDavid Daney bar1_index.s.addr_v = 1;
682b93b2abcSDavid Daney octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
683b93b2abcSDavid Daney bar1_index.u32);
684b93b2abcSDavid Daney }
685b93b2abcSDavid Daney
68601a6221aSDavid Daney /* Devices go after BAR0 */
68701a6221aSDavid Daney octeon_pci_mem_resource.start =
68801a6221aSDavid Daney OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
68901a6221aSDavid Daney (4ul << 10);
69001a6221aSDavid Daney octeon_pci_mem_resource.end =
69101a6221aSDavid Daney octeon_pci_mem_resource.start + (1ul << 30);
69201a6221aSDavid Daney }
69301a6221aSDavid Daney
69401a6221aSDavid Daney register_pci_controller(&octeon_pci_controller);
69501a6221aSDavid Daney
69601a6221aSDavid Daney /*
69701a6221aSDavid Daney * Clear any errors that might be pending from before the bus
69801a6221aSDavid Daney * was setup properly.
69901a6221aSDavid Daney */
70001a6221aSDavid Daney cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
701b93b2abcSDavid Daney
702e1ced097SDavid Daney if (IS_ERR(platform_device_register_simple("octeon_pci_edac",
703e1ced097SDavid Daney -1, NULL, 0)))
7046774def6SMasanari Iida pr_err("Registration of co_pci_edac failed!\n");
705f65aad41SRalf Baechle
706b93b2abcSDavid Daney octeon_pci_dma_init();
707b93b2abcSDavid Daney
70801a6221aSDavid Daney return 0;
70901a6221aSDavid Daney }
71001a6221aSDavid Daney
71101a6221aSDavid Daney arch_initcall(octeon_pci_setup);
712