1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Ralink MT7620A SoC PCI support
4 *
5 * Copyright (C) 2007-2013 Bruce Chang (Mediatek)
6 * Copyright (C) 2013-2016 John Crispin <john@phrozen.org>
7 */
8
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/io.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/of.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_pci.h>
18 #include <linux/reset.h>
19 #include <linux/platform_device.h>
20
21 #include <asm/mach-ralink/ralink_regs.h>
22 #include <asm/mach-ralink/mt7620.h>
23
24 #define RALINK_PCI_IO_MAP_BASE 0x10160000
25 #define RALINK_PCI_MEMORY_BASE 0x0
26
27 #define RALINK_INT_PCIE0 4
28
29 #define RALINK_CLKCFG1 0x30
30 #define RALINK_GPIOMODE 0x60
31
32 #define PPLL_CFG1 0x9c
33 #define PPLL_LD BIT(23)
34
35 #define PPLL_DRV 0xa0
36 #define PDRV_SW_SET BIT(31)
37 #define LC_CKDRVPD BIT(19)
38 #define LC_CKDRVOHZ BIT(18)
39 #define LC_CKDRVHZ BIT(17)
40 #define LC_CKTEST BIT(16)
41
42 /* PCI Bridge registers */
43 #define RALINK_PCI_PCICFG_ADDR 0x00
44 #define PCIRST BIT(1)
45
46 #define RALINK_PCI_PCIENA 0x0C
47 #define PCIINT2 BIT(20)
48
49 #define RALINK_PCI_CONFIG_ADDR 0x20
50 #define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
51 #define RALINK_PCI_MEMBASE 0x28
52 #define RALINK_PCI_IOBASE 0x2C
53
54 /* PCI RC registers */
55 #define RALINK_PCI0_BAR0SETUP_ADDR 0x10
56 #define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
57 #define RALINK_PCI0_ID 0x30
58 #define RALINK_PCI0_CLASS 0x34
59 #define RALINK_PCI0_SUBID 0x38
60 #define RALINK_PCI0_STATUS 0x50
61 #define PCIE_LINK_UP_ST BIT(0)
62
63 #define PCIEPHY0_CFG 0x90
64
65 #define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
66 #define RALINK_PCIE0_CLK_EN BIT(26)
67
68 #define BUSY 0x80000000
69 #define WAITRETRY_MAX 10
70 #define WRITE_MODE (1UL << 23)
71 #define DATA_SHIFT 0
72 #define ADDR_SHIFT 8
73
74
75 static void __iomem *bridge_base;
76 static void __iomem *pcie_base;
77
78 static struct reset_control *rstpcie0;
79
bridge_w32(u32 val,unsigned reg)80 static inline void bridge_w32(u32 val, unsigned reg)
81 {
82 iowrite32(val, bridge_base + reg);
83 }
84
bridge_r32(unsigned reg)85 static inline u32 bridge_r32(unsigned reg)
86 {
87 return ioread32(bridge_base + reg);
88 }
89
pcie_w32(u32 val,unsigned reg)90 static inline void pcie_w32(u32 val, unsigned reg)
91 {
92 iowrite32(val, pcie_base + reg);
93 }
94
pcie_r32(unsigned reg)95 static inline u32 pcie_r32(unsigned reg)
96 {
97 return ioread32(pcie_base + reg);
98 }
99
pcie_m32(u32 clr,u32 set,unsigned reg)100 static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
101 {
102 u32 val = pcie_r32(reg);
103
104 val &= ~clr;
105 val |= set;
106 pcie_w32(val, reg);
107 }
108
wait_pciephy_busy(void)109 static int wait_pciephy_busy(void)
110 {
111 unsigned long reg_value = 0x0, retry = 0;
112
113 while (1) {
114 reg_value = pcie_r32(PCIEPHY0_CFG);
115
116 if (reg_value & BUSY)
117 mdelay(100);
118 else
119 break;
120 if (retry++ > WAITRETRY_MAX) {
121 pr_warn("PCIE-PHY retry failed.\n");
122 return -1;
123 }
124 }
125 return 0;
126 }
127
pcie_phy(unsigned long addr,unsigned long val)128 static void pcie_phy(unsigned long addr, unsigned long val)
129 {
130 wait_pciephy_busy();
131 pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT),
132 PCIEPHY0_CFG);
133 mdelay(1);
134 wait_pciephy_busy();
135 }
136
pci_config_read(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)137 static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
138 int size, u32 *val)
139 {
140 unsigned int slot = PCI_SLOT(devfn);
141 u8 func = PCI_FUNC(devfn);
142 u32 address;
143 u32 data;
144 u32 num = 0;
145
146 if (bus)
147 num = bus->number;
148
149 address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
150 (func << 8) | (where & 0xfc) | 0x80000000;
151 bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
152 data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
153
154 switch (size) {
155 case 1:
156 *val = (data >> ((where & 3) << 3)) & 0xff;
157 break;
158 case 2:
159 *val = (data >> ((where & 3) << 3)) & 0xffff;
160 break;
161 case 4:
162 *val = data;
163 break;
164 }
165
166 return PCIBIOS_SUCCESSFUL;
167 }
168
pci_config_write(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)169 static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
170 int size, u32 val)
171 {
172 unsigned int slot = PCI_SLOT(devfn);
173 u8 func = PCI_FUNC(devfn);
174 u32 address;
175 u32 data;
176 u32 num = 0;
177
178 if (bus)
179 num = bus->number;
180
181 address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
182 (func << 8) | (where & 0xfc) | 0x80000000;
183 bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
184 data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
185
186 switch (size) {
187 case 1:
188 data = (data & ~(0xff << ((where & 3) << 3))) |
189 (val << ((where & 3) << 3));
190 break;
191 case 2:
192 data = (data & ~(0xffff << ((where & 3) << 3))) |
193 (val << ((where & 3) << 3));
194 break;
195 case 4:
196 data = val;
197 break;
198 }
199
200 bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
201
202 return PCIBIOS_SUCCESSFUL;
203 }
204
205 struct pci_ops mt7620_pci_ops = {
206 .read = pci_config_read,
207 .write = pci_config_write,
208 };
209
210 static struct resource mt7620_res_pci_mem1;
211 static struct resource mt7620_res_pci_io1;
212 struct pci_controller mt7620_controller = {
213 .pci_ops = &mt7620_pci_ops,
214 .mem_resource = &mt7620_res_pci_mem1,
215 .mem_offset = 0x00000000UL,
216 .io_resource = &mt7620_res_pci_io1,
217 .io_offset = 0x00000000UL,
218 .io_map_base = 0xa0000000,
219 };
220
mt7620_pci_hw_init(struct platform_device * pdev)221 static int mt7620_pci_hw_init(struct platform_device *pdev)
222 {
223 /* bypass PCIe DLL */
224 pcie_phy(0x0, 0x80);
225 pcie_phy(0x1, 0x04);
226
227 /* Elastic buffer control */
228 pcie_phy(0x68, 0xB4);
229
230 /* put core into reset */
231 pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);
232 reset_control_assert(rstpcie0);
233
234 /* disable power and all clocks */
235 rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
236 rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
237
238 /* bring core out of reset */
239 reset_control_deassert(rstpcie0);
240 rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
241 mdelay(100);
242
243 if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
244 dev_err(&pdev->dev, "pcie PLL not locked, aborting init\n");
245 reset_control_assert(rstpcie0);
246 rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
247 return -1;
248 }
249
250 /* power up the bus */
251 rt_sysc_m32(LC_CKDRVHZ | LC_CKDRVOHZ, LC_CKDRVPD | PDRV_SW_SET,
252 PPLL_DRV);
253
254 return 0;
255 }
256
mt7628_pci_hw_init(struct platform_device * pdev)257 static int mt7628_pci_hw_init(struct platform_device *pdev)
258 {
259 u32 val = 0;
260
261 /* bring the core out of reset */
262 rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
263 reset_control_deassert(rstpcie0);
264
265 /* enable the pci clk */
266 rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
267 mdelay(100);
268
269 /* voodoo from the SDK driver */
270 pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
271
272 pci_config_read(NULL, 0, 0x70c, 4, &val);
273 val &= ~(0xff) << 8;
274 val |= 0x50 << 8;
275 pci_config_write(NULL, 0, 0x70c, 4, val);
276
277 return 0;
278 }
279
mt7620_pci_probe(struct platform_device * pdev)280 static int mt7620_pci_probe(struct platform_device *pdev)
281 {
282 u32 val = 0;
283
284 rstpcie0 = devm_reset_control_get_exclusive(&pdev->dev, "pcie0");
285 if (IS_ERR(rstpcie0))
286 return PTR_ERR(rstpcie0);
287
288 bridge_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
289 if (IS_ERR(bridge_base))
290 return PTR_ERR(bridge_base);
291
292 pcie_base = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
293 if (IS_ERR(pcie_base))
294 return PTR_ERR(pcie_base);
295
296 iomem_resource.start = 0;
297 iomem_resource.end = ~0;
298 ioport_resource.start = 0;
299 ioport_resource.end = ~0;
300
301 /* bring up the pci core */
302 switch (ralink_soc) {
303 case MT762X_SOC_MT7620A:
304 if (mt7620_pci_hw_init(pdev))
305 return -1;
306 break;
307
308 case MT762X_SOC_MT7628AN:
309 case MT762X_SOC_MT7688:
310 if (mt7628_pci_hw_init(pdev))
311 return -1;
312 break;
313
314 default:
315 dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
316 return -1;
317 }
318 mdelay(50);
319
320 /* enable write access */
321 pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
322 mdelay(100);
323
324 /* check if there is a card present */
325 if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) {
326 reset_control_assert(rstpcie0);
327 rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
328 if (ralink_soc == MT762X_SOC_MT7620A)
329 rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
330 dev_info(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
331 return -1;
332 }
333
334 /* setup ranges */
335 bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
336 bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
337
338 pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
339 pcie_w32(RALINK_PCI_MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
340 pcie_w32(0x06040001, RALINK_PCI0_CLASS);
341
342 /* enable interrupts */
343 pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);
344
345 /* voodoo from the SDK driver */
346 pci_config_read(NULL, 0, 4, 4, &val);
347 pci_config_write(NULL, 0, 4, 4, val | 0x7);
348
349 pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
350 register_pci_controller(&mt7620_controller);
351
352 return 0;
353 }
354
pcibios_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)355 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
356 {
357 u16 cmd;
358 u32 val;
359 int irq = 0;
360
361 if ((dev->bus->number == 0) && (slot == 0)) {
362 pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
363 pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,
364 RALINK_PCI_MEMORY_BASE);
365 pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
366 } else if ((dev->bus->number == 1) && (slot == 0x0)) {
367 irq = RALINK_INT_PCIE0;
368 } else {
369 dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n",
370 dev->bus->number, slot);
371 return 0;
372 }
373 dev_info(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
374 dev->bus->number, slot, irq);
375
376 /* configure the cache line size to 0x14 */
377 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
378
379 /* configure latency timer to 0xff */
380 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff);
381 pci_read_config_word(dev, PCI_COMMAND, &cmd);
382
383 /* setup the slot */
384 cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
385 pci_write_config_word(dev, PCI_COMMAND, cmd);
386 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
387
388 return irq;
389 }
390
pcibios_plat_dev_init(struct pci_dev * dev)391 int pcibios_plat_dev_init(struct pci_dev *dev)
392 {
393 return 0;
394 }
395
396 static const struct of_device_id mt7620_pci_ids[] = {
397 { .compatible = "mediatek,mt7620-pci" },
398 {},
399 };
400
401 static struct platform_driver mt7620_pci_driver = {
402 .probe = mt7620_pci_probe,
403 .driver = {
404 .name = "mt7620-pci",
405 .of_match_table = of_match_ptr(mt7620_pci_ids),
406 },
407 };
408
mt7620_pci_init(void)409 static int __init mt7620_pci_init(void)
410 {
411 return platform_driver_register(&mt7620_pci_driver);
412 }
413
414 arch_initcall(mt7620_pci_init);
415