1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License as published by the 4 * Free Software Foundation; either version 2 of the License, or (at your 5 * option) any later version. 6 * 7 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 2011 Wind River Systems, 9 * written by Ralf Baechle (ralf@linux-mips.org) 10 */ 11 #include <linux/bug.h> 12 #include <linux/kernel.h> 13 #include <linux/mm.h> 14 #include <linux/memblock.h> 15 #include <linux/export.h> 16 #include <linux/init.h> 17 #include <linux/types.h> 18 #include <linux/pci.h> 19 #include <linux/of_address.h> 20 21 #include <asm/cpu-info.h> 22 23 /* 24 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource 25 * assignments. 26 */ 27 28 /* 29 * The PCI controller list. 30 */ 31 static LIST_HEAD(controllers); 32 33 static int pci_initialized; 34 35 /* 36 * We need to avoid collisions with `mirrored' VGA ports 37 * and other strange ISA hardware, so we always want the 38 * addresses to be allocated in the 0x000-0x0ff region 39 * modulo 0x400. 40 * 41 * Why? Because some silly external IO cards only decode 42 * the low 10 bits of the IO address. The 0x00-0xff region 43 * is reserved for motherboard devices that decode all 16 44 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 45 * but we want to try to avoid allocating at 0x2900-0x2bff 46 * which might have be mirrored at 0x0100-0x03ff.. 47 */ 48 resource_size_t 49 pcibios_align_resource(void *data, const struct resource *res, 50 resource_size_t size, resource_size_t align) 51 { 52 struct pci_dev *dev = data; 53 struct pci_controller *hose = dev->sysdata; 54 resource_size_t start = res->start; 55 56 if (res->flags & IORESOURCE_IO) { 57 /* Make sure we start at our min on all hoses */ 58 if (start < PCIBIOS_MIN_IO + hose->io_resource->start) 59 start = PCIBIOS_MIN_IO + hose->io_resource->start; 60 61 /* 62 * Put everything into 0x00-0xff region modulo 0x400 63 */ 64 if (start & 0x300) 65 start = (start + 0x3ff) & ~0x3ff; 66 } else if (res->flags & IORESOURCE_MEM) { 67 /* Make sure we start at our min on all hoses */ 68 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start) 69 start = PCIBIOS_MIN_MEM + hose->mem_resource->start; 70 } 71 72 return start; 73 } 74 75 static void pcibios_scanbus(struct pci_controller *hose) 76 { 77 static int next_busno; 78 static int need_domain_info; 79 LIST_HEAD(resources); 80 struct pci_bus *bus; 81 struct pci_host_bridge *bridge; 82 int ret; 83 84 bridge = pci_alloc_host_bridge(0); 85 if (!bridge) 86 return; 87 88 if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY)) 89 next_busno = (*hose->get_busno)(); 90 91 pci_add_resource_offset(&resources, 92 hose->mem_resource, hose->mem_offset); 93 pci_add_resource_offset(&resources, 94 hose->io_resource, hose->io_offset); 95 pci_add_resource(&resources, hose->busn_resource); 96 list_splice_init(&resources, &bridge->windows); 97 bridge->dev.parent = NULL; 98 bridge->sysdata = hose; 99 bridge->busnr = next_busno; 100 bridge->ops = hose->pci_ops; 101 bridge->swizzle_irq = pci_common_swizzle; 102 bridge->map_irq = pcibios_map_irq; 103 ret = pci_scan_root_bus_bridge(bridge); 104 if (ret) { 105 pci_free_host_bridge(bridge); 106 return; 107 } 108 109 hose->bus = bus = bridge->bus; 110 111 need_domain_info = need_domain_info || pci_domain_nr(bus); 112 set_pci_need_domain_info(hose, need_domain_info); 113 114 next_busno = bus->busn_res.end + 1; 115 /* Don't allow 8-bit bus number overflow inside the hose - 116 reserve some space for bridges. */ 117 if (next_busno > 224) { 118 next_busno = 0; 119 need_domain_info = 1; 120 } 121 122 /* 123 * We insert PCI resources into the iomem_resource and 124 * ioport_resource trees in either pci_bus_claim_resources() 125 * or pci_bus_assign_resources(). 126 */ 127 if (pci_has_flag(PCI_PROBE_ONLY)) { 128 pci_bus_claim_resources(bus); 129 } else { 130 struct pci_bus *child; 131 132 pci_bus_size_bridges(bus); 133 pci_bus_assign_resources(bus); 134 list_for_each_entry(child, &bus->children, node) 135 pcie_bus_configure_settings(child); 136 } 137 pci_bus_add_devices(bus); 138 } 139 140 #ifdef CONFIG_OF 141 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node) 142 { 143 struct of_pci_range range; 144 struct of_pci_range_parser parser; 145 146 pr_info("PCI host bridge %pOF ranges:\n", node); 147 hose->of_node = node; 148 149 if (of_pci_range_parser_init(&parser, node)) 150 return; 151 152 for_each_of_pci_range(&parser, &range) { 153 struct resource *res = NULL; 154 155 switch (range.flags & IORESOURCE_TYPE_BITS) { 156 case IORESOURCE_IO: 157 pr_info(" IO 0x%016llx..0x%016llx\n", 158 range.cpu_addr, 159 range.cpu_addr + range.size - 1); 160 hose->io_map_base = 161 (unsigned long)ioremap(range.cpu_addr, 162 range.size); 163 res = hose->io_resource; 164 break; 165 case IORESOURCE_MEM: 166 pr_info(" MEM 0x%016llx..0x%016llx\n", 167 range.cpu_addr, 168 range.cpu_addr + range.size - 1); 169 res = hose->mem_resource; 170 break; 171 } 172 if (res != NULL) 173 of_pci_range_to_resource(&range, node, res); 174 } 175 } 176 177 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 178 { 179 struct pci_controller *hose = bus->sysdata; 180 181 return of_node_get(hose->of_node); 182 } 183 #endif 184 185 static DEFINE_MUTEX(pci_scan_mutex); 186 187 void register_pci_controller(struct pci_controller *hose) 188 { 189 struct resource *parent; 190 191 parent = hose->mem_resource->parent; 192 if (!parent) 193 parent = &iomem_resource; 194 195 if (request_resource(parent, hose->mem_resource) < 0) 196 goto out; 197 198 parent = hose->io_resource->parent; 199 if (!parent) 200 parent = &ioport_resource; 201 202 if (request_resource(parent, hose->io_resource) < 0) { 203 release_resource(hose->mem_resource); 204 goto out; 205 } 206 207 INIT_LIST_HEAD(&hose->list); 208 list_add_tail(&hose->list, &controllers); 209 210 /* 211 * Do not panic here but later - this might happen before console init. 212 */ 213 if (!hose->io_map_base) { 214 printk(KERN_WARNING 215 "registering PCI controller with io_map_base unset\n"); 216 } 217 218 /* 219 * Scan the bus if it is register after the PCI subsystem 220 * initialization. 221 */ 222 if (pci_initialized) { 223 mutex_lock(&pci_scan_mutex); 224 pcibios_scanbus(hose); 225 mutex_unlock(&pci_scan_mutex); 226 } 227 228 return; 229 230 out: 231 printk(KERN_WARNING 232 "Skipping PCI bus scan due to resource conflict\n"); 233 } 234 235 static int __init pcibios_init(void) 236 { 237 struct pci_controller *hose; 238 239 /* Scan all of the recorded PCI controllers. */ 240 list_for_each_entry(hose, &controllers, list) 241 pcibios_scanbus(hose); 242 243 pci_initialized = 1; 244 245 return 0; 246 } 247 248 subsys_initcall(pcibios_init); 249 250 static int pcibios_enable_resources(struct pci_dev *dev, int mask) 251 { 252 u16 cmd, old_cmd; 253 int idx; 254 struct resource *r; 255 256 pci_read_config_word(dev, PCI_COMMAND, &cmd); 257 old_cmd = cmd; 258 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { 259 /* Only set up the requested stuff */ 260 if (!(mask & (1<<idx))) 261 continue; 262 263 r = &dev->resource[idx]; 264 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 265 continue; 266 if ((idx == PCI_ROM_RESOURCE) && 267 (!(r->flags & IORESOURCE_ROM_ENABLE))) 268 continue; 269 if (!r->start && r->end) { 270 pci_err(dev, 271 "can't enable device: resource collisions\n"); 272 return -EINVAL; 273 } 274 if (r->flags & IORESOURCE_IO) 275 cmd |= PCI_COMMAND_IO; 276 if (r->flags & IORESOURCE_MEM) 277 cmd |= PCI_COMMAND_MEMORY; 278 } 279 if (cmd != old_cmd) { 280 pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd); 281 pci_write_config_word(dev, PCI_COMMAND, cmd); 282 } 283 return 0; 284 } 285 286 int pcibios_enable_device(struct pci_dev *dev, int mask) 287 { 288 int err; 289 290 if ((err = pcibios_enable_resources(dev, mask)) < 0) 291 return err; 292 293 return pcibios_plat_dev_init(dev); 294 } 295 296 void pcibios_fixup_bus(struct pci_bus *bus) 297 { 298 struct pci_dev *dev = bus->self; 299 300 if (pci_has_flag(PCI_PROBE_ONLY) && dev && 301 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 302 pci_read_bridge_bases(bus); 303 } 304 } 305 306 char * (*pcibios_plat_setup)(char *str) __initdata; 307 308 char *__init pcibios_setup(char *str) 309 { 310 if (pcibios_plat_setup) 311 return pcibios_plat_setup(str); 312 return str; 313 } 314