1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org) 5 * Copyright (C) 2011 Wind River Systems, 6 * written by Ralf Baechle (ralf@linux-mips.org) 7 */ 8 #include <linux/bug.h> 9 #include <linux/kernel.h> 10 #include <linux/mm.h> 11 #include <linux/memblock.h> 12 #include <linux/export.h> 13 #include <linux/init.h> 14 #include <linux/types.h> 15 #include <linux/pci.h> 16 #include <linux/of_address.h> 17 18 #include <asm/cpu-info.h> 19 20 /* 21 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource 22 * assignments. 23 */ 24 25 /* 26 * The PCI controller list. 27 */ 28 static LIST_HEAD(controllers); 29 30 static int pci_initialized; 31 32 /* 33 * We need to avoid collisions with `mirrored' VGA ports 34 * and other strange ISA hardware, so we always want the 35 * addresses to be allocated in the 0x000-0x0ff region 36 * modulo 0x400. 37 * 38 * Why? Because some silly external IO cards only decode 39 * the low 10 bits of the IO address. The 0x00-0xff region 40 * is reserved for motherboard devices that decode all 16 41 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 42 * but we want to try to avoid allocating at 0x2900-0x2bff 43 * which might have be mirrored at 0x0100-0x03ff.. 44 */ 45 resource_size_t 46 pcibios_align_resource(void *data, const struct resource *res, 47 resource_size_t size, resource_size_t align) 48 { 49 struct pci_dev *dev = data; 50 struct pci_controller *hose = dev->sysdata; 51 resource_size_t start = res->start; 52 53 if (res->flags & IORESOURCE_IO) { 54 /* Make sure we start at our min on all hoses */ 55 if (start < PCIBIOS_MIN_IO + hose->io_resource->start) 56 start = PCIBIOS_MIN_IO + hose->io_resource->start; 57 58 /* 59 * Put everything into 0x00-0xff region modulo 0x400 60 */ 61 if (start & 0x300) 62 start = (start + 0x3ff) & ~0x3ff; 63 } else if (res->flags & IORESOURCE_MEM) { 64 /* Make sure we start at our min on all hoses */ 65 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start) 66 start = PCIBIOS_MIN_MEM + hose->mem_resource->start; 67 } 68 69 return start; 70 } 71 72 static void pcibios_scanbus(struct pci_controller *hose) 73 { 74 static int next_busno; 75 static int need_domain_info; 76 LIST_HEAD(resources); 77 struct pci_bus *bus; 78 struct pci_host_bridge *bridge; 79 int ret; 80 81 bridge = pci_alloc_host_bridge(0); 82 if (!bridge) 83 return; 84 85 if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY)) 86 next_busno = (*hose->get_busno)(); 87 88 pci_add_resource_offset(&resources, 89 hose->mem_resource, hose->mem_offset); 90 pci_add_resource_offset(&resources, 91 hose->io_resource, hose->io_offset); 92 pci_add_resource(&resources, hose->busn_resource); 93 list_splice_init(&resources, &bridge->windows); 94 bridge->dev.parent = NULL; 95 bridge->sysdata = hose; 96 bridge->busnr = next_busno; 97 bridge->ops = hose->pci_ops; 98 bridge->swizzle_irq = pci_common_swizzle; 99 bridge->map_irq = pcibios_map_irq; 100 ret = pci_scan_root_bus_bridge(bridge); 101 if (ret) { 102 pci_free_host_bridge(bridge); 103 return; 104 } 105 106 hose->bus = bus = bridge->bus; 107 108 need_domain_info = need_domain_info || pci_domain_nr(bus); 109 set_pci_need_domain_info(hose, need_domain_info); 110 111 next_busno = bus->busn_res.end + 1; 112 /* Don't allow 8-bit bus number overflow inside the hose - 113 reserve some space for bridges. */ 114 if (next_busno > 224) { 115 next_busno = 0; 116 need_domain_info = 1; 117 } 118 119 /* 120 * We insert PCI resources into the iomem_resource and 121 * ioport_resource trees in either pci_bus_claim_resources() 122 * or pci_bus_assign_resources(). 123 */ 124 if (pci_has_flag(PCI_PROBE_ONLY)) { 125 pci_bus_claim_resources(bus); 126 } else { 127 struct pci_bus *child; 128 129 pci_bus_size_bridges(bus); 130 pci_bus_assign_resources(bus); 131 list_for_each_entry(child, &bus->children, node) 132 pcie_bus_configure_settings(child); 133 } 134 pci_bus_add_devices(bus); 135 } 136 137 #ifdef CONFIG_OF 138 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node) 139 { 140 struct of_pci_range range; 141 struct of_pci_range_parser parser; 142 143 pr_info("PCI host bridge %pOF ranges:\n", node); 144 hose->of_node = node; 145 146 if (of_pci_range_parser_init(&parser, node)) 147 return; 148 149 for_each_of_pci_range(&parser, &range) { 150 struct resource *res = NULL; 151 152 switch (range.flags & IORESOURCE_TYPE_BITS) { 153 case IORESOURCE_IO: 154 pr_info(" IO 0x%016llx..0x%016llx\n", 155 range.cpu_addr, 156 range.cpu_addr + range.size - 1); 157 hose->io_map_base = 158 (unsigned long)ioremap(range.cpu_addr, 159 range.size); 160 res = hose->io_resource; 161 break; 162 case IORESOURCE_MEM: 163 pr_info(" MEM 0x%016llx..0x%016llx\n", 164 range.cpu_addr, 165 range.cpu_addr + range.size - 1); 166 res = hose->mem_resource; 167 break; 168 } 169 if (res != NULL) 170 of_pci_range_to_resource(&range, node, res); 171 } 172 } 173 174 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 175 { 176 struct pci_controller *hose = bus->sysdata; 177 178 return of_node_get(hose->of_node); 179 } 180 #endif 181 182 static DEFINE_MUTEX(pci_scan_mutex); 183 184 void register_pci_controller(struct pci_controller *hose) 185 { 186 struct resource *parent; 187 188 parent = hose->mem_resource->parent; 189 if (!parent) 190 parent = &iomem_resource; 191 192 if (request_resource(parent, hose->mem_resource) < 0) 193 goto out; 194 195 parent = hose->io_resource->parent; 196 if (!parent) 197 parent = &ioport_resource; 198 199 if (request_resource(parent, hose->io_resource) < 0) { 200 release_resource(hose->mem_resource); 201 goto out; 202 } 203 204 INIT_LIST_HEAD(&hose->list); 205 list_add_tail(&hose->list, &controllers); 206 207 /* 208 * Do not panic here but later - this might happen before console init. 209 */ 210 if (!hose->io_map_base) { 211 printk(KERN_WARNING 212 "registering PCI controller with io_map_base unset\n"); 213 } 214 215 /* 216 * Scan the bus if it is register after the PCI subsystem 217 * initialization. 218 */ 219 if (pci_initialized) { 220 mutex_lock(&pci_scan_mutex); 221 pcibios_scanbus(hose); 222 mutex_unlock(&pci_scan_mutex); 223 } 224 225 return; 226 227 out: 228 printk(KERN_WARNING 229 "Skipping PCI bus scan due to resource conflict\n"); 230 } 231 232 static int __init pcibios_init(void) 233 { 234 struct pci_controller *hose; 235 236 /* Scan all of the recorded PCI controllers. */ 237 list_for_each_entry(hose, &controllers, list) 238 pcibios_scanbus(hose); 239 240 pci_initialized = 1; 241 242 return 0; 243 } 244 245 subsys_initcall(pcibios_init); 246 247 static int pcibios_enable_resources(struct pci_dev *dev, int mask) 248 { 249 u16 cmd, old_cmd; 250 int idx; 251 struct resource *r; 252 253 pci_read_config_word(dev, PCI_COMMAND, &cmd); 254 old_cmd = cmd; 255 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { 256 /* Only set up the requested stuff */ 257 if (!(mask & (1<<idx))) 258 continue; 259 260 r = &dev->resource[idx]; 261 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 262 continue; 263 if ((idx == PCI_ROM_RESOURCE) && 264 (!(r->flags & IORESOURCE_ROM_ENABLE))) 265 continue; 266 if (!r->start && r->end) { 267 pci_err(dev, 268 "can't enable device: resource collisions\n"); 269 return -EINVAL; 270 } 271 if (r->flags & IORESOURCE_IO) 272 cmd |= PCI_COMMAND_IO; 273 if (r->flags & IORESOURCE_MEM) 274 cmd |= PCI_COMMAND_MEMORY; 275 } 276 if (cmd != old_cmd) { 277 pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd); 278 pci_write_config_word(dev, PCI_COMMAND, cmd); 279 } 280 return 0; 281 } 282 283 int pcibios_enable_device(struct pci_dev *dev, int mask) 284 { 285 int err; 286 287 if ((err = pcibios_enable_resources(dev, mask)) < 0) 288 return err; 289 290 return pcibios_plat_dev_init(dev); 291 } 292 293 void pcibios_fixup_bus(struct pci_bus *bus) 294 { 295 struct pci_dev *dev = bus->self; 296 297 if (pci_has_flag(PCI_PROBE_ONLY) && dev && 298 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 299 pci_read_bridge_bases(bus); 300 } 301 } 302 303 char * (*pcibios_plat_setup)(char *str) __initdata; 304 305 char *__init pcibios_setup(char *str) 306 { 307 if (pcibios_plat_setup) 308 return pcibios_plat_setup(str); 309 return str; 310 } 311