1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License as published by the 4 * Free Software Foundation; either version 2 of the License, or (at your 5 * option) any later version. 6 * 7 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 2011 Wind River Systems, 9 * written by Ralf Baechle (ralf@linux-mips.org) 10 */ 11 #include <linux/bug.h> 12 #include <linux/kernel.h> 13 #include <linux/mm.h> 14 #include <linux/bootmem.h> 15 #include <linux/export.h> 16 #include <linux/init.h> 17 #include <linux/types.h> 18 #include <linux/pci.h> 19 #include <linux/of_address.h> 20 21 #include <asm/cpu-info.h> 22 23 /* 24 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource 25 * assignments. 26 */ 27 28 /* 29 * The PCI controller list. 30 */ 31 static LIST_HEAD(controllers); 32 33 static int pci_initialized; 34 35 /* 36 * We need to avoid collisions with `mirrored' VGA ports 37 * and other strange ISA hardware, so we always want the 38 * addresses to be allocated in the 0x000-0x0ff region 39 * modulo 0x400. 40 * 41 * Why? Because some silly external IO cards only decode 42 * the low 10 bits of the IO address. The 0x00-0xff region 43 * is reserved for motherboard devices that decode all 16 44 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 45 * but we want to try to avoid allocating at 0x2900-0x2bff 46 * which might have be mirrored at 0x0100-0x03ff.. 47 */ 48 resource_size_t 49 pcibios_align_resource(void *data, const struct resource *res, 50 resource_size_t size, resource_size_t align) 51 { 52 struct pci_dev *dev = data; 53 struct pci_controller *hose = dev->sysdata; 54 resource_size_t start = res->start; 55 56 if (res->flags & IORESOURCE_IO) { 57 /* Make sure we start at our min on all hoses */ 58 if (start < PCIBIOS_MIN_IO + hose->io_resource->start) 59 start = PCIBIOS_MIN_IO + hose->io_resource->start; 60 61 /* 62 * Put everything into 0x00-0xff region modulo 0x400 63 */ 64 if (start & 0x300) 65 start = (start + 0x3ff) & ~0x3ff; 66 } else if (res->flags & IORESOURCE_MEM) { 67 /* Make sure we start at our min on all hoses */ 68 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start) 69 start = PCIBIOS_MIN_MEM + hose->mem_resource->start; 70 } 71 72 return start; 73 } 74 75 static void pcibios_scanbus(struct pci_controller *hose) 76 { 77 static int next_busno; 78 static int need_domain_info; 79 LIST_HEAD(resources); 80 struct pci_bus *bus; 81 82 if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY)) 83 next_busno = (*hose->get_busno)(); 84 85 pci_add_resource_offset(&resources, 86 hose->mem_resource, hose->mem_offset); 87 pci_add_resource_offset(&resources, 88 hose->io_resource, hose->io_offset); 89 pci_add_resource_offset(&resources, 90 hose->busn_resource, hose->busn_offset); 91 bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose, 92 &resources); 93 hose->bus = bus; 94 95 need_domain_info = need_domain_info || pci_domain_nr(bus); 96 set_pci_need_domain_info(hose, need_domain_info); 97 98 if (!bus) { 99 pci_free_resource_list(&resources); 100 return; 101 } 102 103 next_busno = bus->busn_res.end + 1; 104 /* Don't allow 8-bit bus number overflow inside the hose - 105 reserve some space for bridges. */ 106 if (next_busno > 224) { 107 next_busno = 0; 108 need_domain_info = 1; 109 } 110 111 /* 112 * We insert PCI resources into the iomem_resource and 113 * ioport_resource trees in either pci_bus_claim_resources() 114 * or pci_bus_assign_resources(). 115 */ 116 if (pci_has_flag(PCI_PROBE_ONLY)) { 117 pci_bus_claim_resources(bus); 118 } else { 119 pci_bus_size_bridges(bus); 120 pci_bus_assign_resources(bus); 121 } 122 pci_bus_add_devices(bus); 123 } 124 125 #ifdef CONFIG_OF 126 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node) 127 { 128 struct of_pci_range range; 129 struct of_pci_range_parser parser; 130 131 pr_info("PCI host bridge %s ranges:\n", node->full_name); 132 hose->of_node = node; 133 134 if (of_pci_range_parser_init(&parser, node)) 135 return; 136 137 for_each_of_pci_range(&parser, &range) { 138 struct resource *res = NULL; 139 140 switch (range.flags & IORESOURCE_TYPE_BITS) { 141 case IORESOURCE_IO: 142 pr_info(" IO 0x%016llx..0x%016llx\n", 143 range.cpu_addr, 144 range.cpu_addr + range.size - 1); 145 hose->io_map_base = 146 (unsigned long)ioremap(range.cpu_addr, 147 range.size); 148 res = hose->io_resource; 149 break; 150 case IORESOURCE_MEM: 151 pr_info(" MEM 0x%016llx..0x%016llx\n", 152 range.cpu_addr, 153 range.cpu_addr + range.size - 1); 154 res = hose->mem_resource; 155 break; 156 } 157 if (res != NULL) 158 of_pci_range_to_resource(&range, node, res); 159 } 160 } 161 162 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 163 { 164 struct pci_controller *hose = bus->sysdata; 165 166 return of_node_get(hose->of_node); 167 } 168 #endif 169 170 static DEFINE_MUTEX(pci_scan_mutex); 171 172 void register_pci_controller(struct pci_controller *hose) 173 { 174 struct resource *parent; 175 176 parent = hose->mem_resource->parent; 177 if (!parent) 178 parent = &iomem_resource; 179 180 if (request_resource(parent, hose->mem_resource) < 0) 181 goto out; 182 183 parent = hose->io_resource->parent; 184 if (!parent) 185 parent = &ioport_resource; 186 187 if (request_resource(parent, hose->io_resource) < 0) { 188 release_resource(hose->mem_resource); 189 goto out; 190 } 191 192 INIT_LIST_HEAD(&hose->list); 193 list_add(&hose->list, &controllers); 194 195 /* 196 * Do not panic here but later - this might happen before console init. 197 */ 198 if (!hose->io_map_base) { 199 printk(KERN_WARNING 200 "registering PCI controller with io_map_base unset\n"); 201 } 202 203 /* 204 * Scan the bus if it is register after the PCI subsystem 205 * initialization. 206 */ 207 if (pci_initialized) { 208 mutex_lock(&pci_scan_mutex); 209 pcibios_scanbus(hose); 210 mutex_unlock(&pci_scan_mutex); 211 } 212 213 return; 214 215 out: 216 printk(KERN_WARNING 217 "Skipping PCI bus scan due to resource conflict\n"); 218 } 219 220 static int __init pcibios_init(void) 221 { 222 struct pci_controller *hose; 223 224 /* Scan all of the recorded PCI controllers. */ 225 list_for_each_entry(hose, &controllers, list) 226 pcibios_scanbus(hose); 227 228 pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq); 229 230 pci_initialized = 1; 231 232 return 0; 233 } 234 235 subsys_initcall(pcibios_init); 236 237 static int pcibios_enable_resources(struct pci_dev *dev, int mask) 238 { 239 u16 cmd, old_cmd; 240 int idx; 241 struct resource *r; 242 243 pci_read_config_word(dev, PCI_COMMAND, &cmd); 244 old_cmd = cmd; 245 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { 246 /* Only set up the requested stuff */ 247 if (!(mask & (1<<idx))) 248 continue; 249 250 r = &dev->resource[idx]; 251 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 252 continue; 253 if ((idx == PCI_ROM_RESOURCE) && 254 (!(r->flags & IORESOURCE_ROM_ENABLE))) 255 continue; 256 if (!r->start && r->end) { 257 printk(KERN_ERR "PCI: Device %s not available " 258 "because of resource collisions\n", 259 pci_name(dev)); 260 return -EINVAL; 261 } 262 if (r->flags & IORESOURCE_IO) 263 cmd |= PCI_COMMAND_IO; 264 if (r->flags & IORESOURCE_MEM) 265 cmd |= PCI_COMMAND_MEMORY; 266 } 267 if (cmd != old_cmd) { 268 printk("PCI: Enabling device %s (%04x -> %04x)\n", 269 pci_name(dev), old_cmd, cmd); 270 pci_write_config_word(dev, PCI_COMMAND, cmd); 271 } 272 return 0; 273 } 274 275 int pcibios_enable_device(struct pci_dev *dev, int mask) 276 { 277 int err; 278 279 if ((err = pcibios_enable_resources(dev, mask)) < 0) 280 return err; 281 282 return pcibios_plat_dev_init(dev); 283 } 284 285 void pcibios_fixup_bus(struct pci_bus *bus) 286 { 287 struct pci_dev *dev = bus->self; 288 289 if (pci_has_flag(PCI_PROBE_ONLY) && dev && 290 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 291 pci_read_bridge_bases(bus); 292 } 293 } 294 295 char * (*pcibios_plat_setup)(char *str) __initdata; 296 297 char *__init pcibios_setup(char *str) 298 { 299 if (pcibios_plat_setup) 300 return pcibios_plat_setup(str); 301 return str; 302 } 303