1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org> 7 */ 8 9 #include <linux/types.h> 10 #include <linux/pci.h> 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/delay.h> 14 #include <linux/mm.h> 15 #include <linux/vmalloc.h> 16 #include <linux/export.h> 17 #include <linux/platform_device.h> 18 19 #include <asm/pci.h> 20 #include <asm/gpio.h> 21 #include <asm/addrspace.h> 22 23 #include <lantiq_soc.h> 24 #include <lantiq_irq.h> 25 #include <lantiq_platform.h> 26 27 #include "pci-lantiq.h" 28 29 #define LTQ_PCI_CFG_BASE 0x17000000 30 #define LTQ_PCI_CFG_SIZE 0x00008000 31 #define LTQ_PCI_MEM_BASE 0x18000000 32 #define LTQ_PCI_MEM_SIZE 0x02000000 33 #define LTQ_PCI_IO_BASE 0x1AE00000 34 #define LTQ_PCI_IO_SIZE 0x00200000 35 36 #define PCI_CR_FCI_ADDR_MAP0 0x00C0 37 #define PCI_CR_FCI_ADDR_MAP1 0x00C4 38 #define PCI_CR_FCI_ADDR_MAP2 0x00C8 39 #define PCI_CR_FCI_ADDR_MAP3 0x00CC 40 #define PCI_CR_FCI_ADDR_MAP4 0x00D0 41 #define PCI_CR_FCI_ADDR_MAP5 0x00D4 42 #define PCI_CR_FCI_ADDR_MAP6 0x00D8 43 #define PCI_CR_FCI_ADDR_MAP7 0x00DC 44 #define PCI_CR_CLK_CTRL 0x0000 45 #define PCI_CR_PCI_MOD 0x0030 46 #define PCI_CR_PC_ARB 0x0080 47 #define PCI_CR_FCI_ADDR_MAP11hg 0x00E4 48 #define PCI_CR_BAR11MASK 0x0044 49 #define PCI_CR_BAR12MASK 0x0048 50 #define PCI_CR_BAR13MASK 0x004C 51 #define PCI_CS_BASE_ADDR1 0x0010 52 #define PCI_CR_PCI_ADDR_MAP11 0x0064 53 #define PCI_CR_FCI_BURST_LENGTH 0x00E8 54 #define PCI_CR_PCI_EOI 0x002C 55 #define PCI_CS_STS_CMD 0x0004 56 57 #define PCI_MASTER0_REQ_MASK_2BITS 8 58 #define PCI_MASTER1_REQ_MASK_2BITS 10 59 #define PCI_MASTER2_REQ_MASK_2BITS 12 60 #define INTERNAL_ARB_ENABLE_BIT 0 61 62 #define LTQ_CGU_IFCCR 0x0018 63 #define LTQ_CGU_PCICR 0x0034 64 65 #define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y)) 66 #define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x)) 67 68 #define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) 69 #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) 70 71 struct ltq_pci_gpio_map { 72 int pin; 73 int alt0; 74 int alt1; 75 int dir; 76 char *name; 77 }; 78 79 /* the pci core can make use of the following gpios */ 80 static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = { 81 { 0, 1, 0, 0, "pci-exin0" }, 82 { 1, 1, 0, 0, "pci-exin1" }, 83 { 2, 1, 0, 0, "pci-exin2" }, 84 { 39, 1, 0, 0, "pci-exin3" }, 85 { 10, 1, 0, 0, "pci-exin4" }, 86 { 9, 1, 0, 0, "pci-exin5" }, 87 { 30, 1, 0, 1, "pci-gnt1" }, 88 { 23, 1, 0, 1, "pci-gnt2" }, 89 { 19, 1, 0, 1, "pci-gnt3" }, 90 { 38, 1, 0, 1, "pci-gnt4" }, 91 { 29, 1, 0, 0, "pci-req1" }, 92 { 31, 1, 0, 0, "pci-req2" }, 93 { 3, 1, 0, 0, "pci-req3" }, 94 { 37, 1, 0, 0, "pci-req4" }, 95 }; 96 97 __iomem void *ltq_pci_mapped_cfg; 98 static __iomem void *ltq_pci_membase; 99 100 int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL; 101 102 /* Since the PCI REQ pins can be reused for other functionality, make it 103 possible to exclude those from interpretation by the PCI controller */ 104 static int ltq_pci_req_mask = 0xf; 105 106 static int *ltq_pci_irq_map; 107 108 struct pci_ops ltq_pci_ops = { 109 .read = ltq_pci_read_config_dword, 110 .write = ltq_pci_write_config_dword 111 }; 112 113 static struct resource pci_io_resource = { 114 .name = "pci io space", 115 .start = LTQ_PCI_IO_BASE, 116 .end = LTQ_PCI_IO_BASE + LTQ_PCI_IO_SIZE - 1, 117 .flags = IORESOURCE_IO 118 }; 119 120 static struct resource pci_mem_resource = { 121 .name = "pci memory space", 122 .start = LTQ_PCI_MEM_BASE, 123 .end = LTQ_PCI_MEM_BASE + LTQ_PCI_MEM_SIZE - 1, 124 .flags = IORESOURCE_MEM 125 }; 126 127 static struct pci_controller ltq_pci_controller = { 128 .pci_ops = <q_pci_ops, 129 .mem_resource = &pci_mem_resource, 130 .mem_offset = 0x00000000UL, 131 .io_resource = &pci_io_resource, 132 .io_offset = 0x00000000UL, 133 }; 134 135 int pcibios_plat_dev_init(struct pci_dev *dev) 136 { 137 if (ltqpci_plat_dev_init) 138 return ltqpci_plat_dev_init(dev); 139 140 return 0; 141 } 142 143 static u32 ltq_calc_bar11mask(void) 144 { 145 u32 mem, bar11mask; 146 147 /* BAR11MASK value depends on available memory on system. */ 148 mem = num_physpages * PAGE_SIZE; 149 bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8; 150 151 return bar11mask; 152 } 153 154 static void ltq_pci_setup_gpio(int gpio) 155 { 156 int i; 157 for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) { 158 if (gpio & (1 << i)) { 159 ltq_gpio_request(ltq_pci_gpio_map[i].pin, 160 ltq_pci_gpio_map[i].alt0, 161 ltq_pci_gpio_map[i].alt1, 162 ltq_pci_gpio_map[i].dir, 163 ltq_pci_gpio_map[i].name); 164 } 165 } 166 ltq_gpio_request(21, 0, 0, 1, "pci-reset"); 167 ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; 168 } 169 170 static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) 171 { 172 u32 temp_buffer; 173 174 /* set clock to 33Mhz */ 175 if (ltq_is_ar9()) { 176 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0x1f00000, LTQ_CGU_IFCCR); 177 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0xe00000, LTQ_CGU_IFCCR); 178 } else { 179 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR); 180 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR); 181 } 182 183 /* external or internal clock ? */ 184 if (conf->clock) { 185 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~(1 << 16), 186 LTQ_CGU_IFCCR); 187 ltq_cgu_w32((1 << 30), LTQ_CGU_PCICR); 188 } else { 189 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | (1 << 16), 190 LTQ_CGU_IFCCR); 191 ltq_cgu_w32((1 << 31) | (1 << 30), LTQ_CGU_PCICR); 192 } 193 194 /* setup pci clock and gpis used by pci */ 195 ltq_pci_setup_gpio(conf->gpio); 196 197 /* enable auto-switching between PCI and EBU */ 198 ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); 199 200 /* busy, i.e. configuration is not done, PCI access has to be retried */ 201 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD); 202 wmb(); 203 /* BUS Master/IO/MEM access */ 204 ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD); 205 206 /* enable external 2 PCI masters */ 207 temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB); 208 temp_buffer &= (~(ltq_pci_req_mask << 16)); 209 /* enable internal arbiter */ 210 temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT); 211 /* enable internal PCI master reqest */ 212 temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS)); 213 214 /* enable EBU request */ 215 temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS)); 216 217 /* enable all external masters request */ 218 temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS)); 219 ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB); 220 wmb(); 221 222 /* setup BAR memory regions */ 223 ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0); 224 ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1); 225 ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2); 226 ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3); 227 ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4); 228 ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5); 229 ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6); 230 ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7); 231 ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg); 232 ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK); 233 ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11); 234 ltq_pci_w32(0, PCI_CS_BASE_ADDR1); 235 /* both TX and RX endian swap are enabled */ 236 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI); 237 wmb(); 238 ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000, 239 PCI_CR_BAR12MASK); 240 ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000, 241 PCI_CR_BAR13MASK); 242 /*use 8 dw burst length */ 243 ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH); 244 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD); 245 wmb(); 246 247 /* setup irq line */ 248 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON); 249 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN); 250 251 /* toggle reset pin */ 252 __gpio_set_value(21, 0); 253 wmb(); 254 mdelay(1); 255 __gpio_set_value(21, 1); 256 return 0; 257 } 258 259 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 260 { 261 if (ltq_pci_irq_map[slot]) 262 return ltq_pci_irq_map[slot]; 263 printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n", 264 slot); 265 266 return 0; 267 } 268 269 static int __devinit ltq_pci_probe(struct platform_device *pdev) 270 { 271 struct ltq_pci_data *ltq_pci_data = 272 (struct ltq_pci_data *) pdev->dev.platform_data; 273 274 pci_clear_flags(PCI_PROBE_ONLY); 275 ltq_pci_irq_map = ltq_pci_data->irq; 276 ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE); 277 ltq_pci_mapped_cfg = 278 ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE); 279 ltq_pci_controller.io_map_base = 280 (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1); 281 ltq_pci_startup(ltq_pci_data); 282 register_pci_controller(<q_pci_controller); 283 284 return 0; 285 } 286 287 static struct platform_driver 288 ltq_pci_driver = { 289 .probe = ltq_pci_probe, 290 .driver = { 291 .name = "ltq_pci", 292 .owner = THIS_MODULE, 293 }, 294 }; 295 296 int __init pcibios_init(void) 297 { 298 int ret = platform_driver_register(<q_pci_driver); 299 if (ret) 300 printk(KERN_INFO "ltq_pci: Error registering platfom driver!"); 301 return ret; 302 } 303 304 arch_initcall(pcibios_init); 305