1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003 Christoph Hellwig (hch@lst.de) 7 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 */ 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/pci.h> 13 #include <asm/sn/arch.h> 14 #include <asm/pci/bridge.h> 15 #include <asm/paccess.h> 16 #include <asm/sn/intr.h> 17 #include <asm/sn/sn0/hub.h> 18 19 /* 20 * Max #PCI busses we can handle; ie, max #PCI bridges. 21 */ 22 #define MAX_PCI_BUSSES 40 23 24 /* 25 * Max #PCI devices (like scsi controllers) we handle on a bus. 26 */ 27 #define MAX_DEVICES_PER_PCIBUS 8 28 29 /* 30 * XXX: No kmalloc available when we do our crosstalk scan, 31 * we should try to move it later in the boot process. 32 */ 33 static struct bridge_controller bridges[MAX_PCI_BUSSES]; 34 35 /* 36 * Translate from irq to software PCI bus number and PCI slot. 37 */ 38 struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS]; 39 int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS]; 40 41 extern struct pci_ops bridge_pci_ops; 42 43 int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid) 44 { 45 unsigned long offset = NODE_OFFSET(nasid); 46 struct bridge_controller *bc; 47 static int num_bridges = 0; 48 bridge_t *bridge; 49 int slot; 50 51 printk("a bridge\n"); 52 53 /* XXX: kludge alert.. */ 54 if (!num_bridges) 55 ioport_resource.end = ~0UL; 56 57 bc = &bridges[num_bridges]; 58 59 bc->pc.pci_ops = &bridge_pci_ops; 60 bc->pc.mem_resource = &bc->mem; 61 bc->pc.io_resource = &bc->io; 62 63 bc->pc.index = num_bridges; 64 65 bc->mem.name = "Bridge PCI MEM"; 66 bc->pc.mem_offset = offset; 67 bc->mem.start = 0; 68 bc->mem.end = ~0UL; 69 bc->mem.flags = IORESOURCE_MEM; 70 71 bc->io.name = "Bridge IO MEM"; 72 bc->pc.io_offset = offset; 73 bc->io.start = 0UL; 74 bc->io.end = ~0UL; 75 bc->io.flags = IORESOURCE_IO; 76 77 bc->irq_cpu = smp_processor_id(); 78 bc->widget_id = widget_id; 79 bc->nasid = nasid; 80 81 bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR; 82 83 /* 84 * point to this bridge 85 */ 86 bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id); 87 88 /* 89 * Clear all pending interrupts. 90 */ 91 bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR; 92 93 /* 94 * Until otherwise set up, assume all interrupts are from slot 0 95 */ 96 bridge->b_int_device = 0x0; 97 98 /* 99 * swap pio's to pci mem and io space (big windows) 100 */ 101 bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP | 102 BRIDGE_CTRL_MEM_SWAP; 103 104 /* 105 * Hmm... IRIX sets additional bits in the address which 106 * are documented as reserved in the bridge docs. 107 */ 108 bridge->b_wid_int_upper = 0x8000 | (masterwid << 16); 109 bridge->b_wid_int_lower = 0x01800090; /* PI_INT_PEND_MOD off*/ 110 bridge->b_dir_map = (masterwid << 20); /* DMA */ 111 bridge->b_int_enable = 0; 112 113 for (slot = 0; slot < 8; slot ++) { 114 bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR; 115 bc->pci_int[slot] = -1; 116 } 117 bridge->b_wid_tflush; /* wait until Bridge PIO complete */ 118 119 bc->base = bridge; 120 121 register_pci_controller(&bc->pc); 122 123 num_bridges++; 124 125 return 0; 126 } 127 128 /* 129 * All observed requests have pin == 1. We could have a global here, that 130 * gets incremented and returned every time - unfortunately, pci_map_irq 131 * may be called on the same device over and over, and need to return the 132 * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7]. 133 * 134 * A given PCI device, in general, should be able to intr any of the cpus 135 * on any one of the hubs connected to its xbow. 136 */ 137 int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 138 { 139 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 140 int irq = bc->pci_int[slot]; 141 142 if (irq == -1) { 143 irq = bc->pci_int[slot] = request_bridge_irq(bc); 144 if (irq < 0) 145 panic("Can't allocate interrupt for PCI device %s\n", 146 pci_name(dev)); 147 } 148 149 irq_to_bridge[irq] = bc; 150 irq_to_slot[irq] = slot; 151 152 return irq; 153 } 154 155 /* Do platform specific device initialization at pci_enable_device() time */ 156 int pcibios_plat_dev_init(struct pci_dev *dev) 157 { 158 return 0; 159 } 160 161 /* 162 * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses 163 * to find the slot number in sense of the bridge device register. 164 * XXX This also means multiple devices might rely on conflicting bridge 165 * settings. 166 */ 167 168 static inline void pci_disable_swapping(struct pci_dev *dev) 169 { 170 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 171 bridge_t *bridge = bc->base; 172 int slot = PCI_SLOT(dev->devfn); 173 174 /* Turn off byte swapping */ 175 bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR; 176 bridge->b_widget.w_tflush; /* Flush */ 177 } 178 179 static inline void pci_enable_swapping(struct pci_dev *dev) 180 { 181 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 182 bridge_t *bridge = bc->base; 183 int slot = PCI_SLOT(dev->devfn); 184 185 /* Turn on byte swapping */ 186 bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR; 187 bridge->b_widget.w_tflush; /* Flush */ 188 } 189 190 static void __init pci_fixup_ioc3(struct pci_dev *d) 191 { 192 pci_disable_swapping(d); 193 } 194 195 int pcibus_to_node(struct pci_bus *bus) 196 { 197 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 198 199 return bc->nasid; 200 } 201 202 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 203 pci_fixup_ioc3); 204