11ccea77eSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 23ed7a2a7SSergey Ryazanov /* 33ed7a2a7SSergey Ryazanov */ 43ed7a2a7SSergey Ryazanov 53ed7a2a7SSergey Ryazanov /** 63ed7a2a7SSergey Ryazanov * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA 73ed7a2a7SSergey Ryazanov * and interrupt. PCI interface supports MMIO access method, but does not 83ed7a2a7SSergey Ryazanov * seem to support I/O ports. 93ed7a2a7SSergey Ryazanov * 103ed7a2a7SSergey Ryazanov * Read/write operation in the region 0x80000000-0xBFFFFFFF causes 113ed7a2a7SSergey Ryazanov * a memory read/write command on the PCI bus. 30 LSBs of address on 123ed7a2a7SSergey Ryazanov * the bus are taken from memory read/write request and 2 MSBs are 133ed7a2a7SSergey Ryazanov * determined by PCI unit configuration. 143ed7a2a7SSergey Ryazanov * 153ed7a2a7SSergey Ryazanov * To work with the configuration space instead of memory is necessary set 163ed7a2a7SSergey Ryazanov * the CFG_SEL bit in the PCI_MISC_CONFIG register. 173ed7a2a7SSergey Ryazanov * 183ed7a2a7SSergey Ryazanov * Devices on the bus can perform DMA requests via chip BAR1. PCI host 193ed7a2a7SSergey Ryazanov * controller BARs are programmend as if an external device is programmed. 203ed7a2a7SSergey Ryazanov * Which means that during configuration, IDSEL pin of the chip should be 213ed7a2a7SSergey Ryazanov * asserted. 223ed7a2a7SSergey Ryazanov * 233ed7a2a7SSergey Ryazanov * We know (and support) only one board that uses the PCI interface - 243ed7a2a7SSergey Ryazanov * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the 253ed7a2a7SSergey Ryazanov * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line 263ed7a2a7SSergey Ryazanov * and IDSEL pin of AR2315 is connected to AD[16] line. 273ed7a2a7SSergey Ryazanov */ 283ed7a2a7SSergey Ryazanov 293ed7a2a7SSergey Ryazanov #include <linux/types.h> 303ed7a2a7SSergey Ryazanov #include <linux/pci.h> 313ed7a2a7SSergey Ryazanov #include <linux/platform_device.h> 323ed7a2a7SSergey Ryazanov #include <linux/kernel.h> 333ed7a2a7SSergey Ryazanov #include <linux/init.h> 343ed7a2a7SSergey Ryazanov #include <linux/mm.h> 353ed7a2a7SSergey Ryazanov #include <linux/delay.h> 363ed7a2a7SSergey Ryazanov #include <linux/bitops.h> 373ed7a2a7SSergey Ryazanov #include <linux/irq.h> 383ed7a2a7SSergey Ryazanov #include <linux/irqdomain.h> 393ed7a2a7SSergey Ryazanov #include <linux/io.h> 403ed7a2a7SSergey Ryazanov #include <asm/paccess.h> 413ed7a2a7SSergey Ryazanov 423ed7a2a7SSergey Ryazanov /* 433ed7a2a7SSergey Ryazanov * PCI Bus Interface Registers 443ed7a2a7SSergey Ryazanov */ 453ed7a2a7SSergey Ryazanov #define AR2315_PCI_1MS_REG 0x0008 463ed7a2a7SSergey Ryazanov 473ed7a2a7SSergey Ryazanov #define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ 483ed7a2a7SSergey Ryazanov 493ed7a2a7SSergey Ryazanov #define AR2315_PCI_MISC_CONFIG 0x000c 503ed7a2a7SSergey Ryazanov 513ed7a2a7SSergey Ryazanov #define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */ 523ed7a2a7SSergey Ryazanov #define AR2315_PCIMISC_CFG_SEL 0x00000002 /* Mem or Config cycles */ 533ed7a2a7SSergey Ryazanov #define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */ 543ed7a2a7SSergey Ryazanov #define AR2315_PCIMISC_RST_MODE 0x00000030 553ed7a2a7SSergey Ryazanov #define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */ 563ed7a2a7SSergey Ryazanov #define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */ 573ed7a2a7SSergey Ryazanov #define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */ 583ed7a2a7SSergey Ryazanov #define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */ 593ed7a2a7SSergey Ryazanov #define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */ 603ed7a2a7SSergey Ryazanov #define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */ 613ed7a2a7SSergey Ryazanov #define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */ 623ed7a2a7SSergey Ryazanov #define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache 633ed7a2a7SSergey Ryazanov * disable */ 643ed7a2a7SSergey Ryazanov 653ed7a2a7SSergey Ryazanov #define AR2315_PCI_OUT_TSTAMP 0x0010 663ed7a2a7SSergey Ryazanov 673ed7a2a7SSergey Ryazanov #define AR2315_PCI_UNCACHE_CFG 0x0014 683ed7a2a7SSergey Ryazanov 693ed7a2a7SSergey Ryazanov #define AR2315_PCI_IN_EN 0x0100 703ed7a2a7SSergey Ryazanov 713ed7a2a7SSergey Ryazanov #define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */ 723ed7a2a7SSergey Ryazanov #define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */ 733ed7a2a7SSergey Ryazanov #define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */ 743ed7a2a7SSergey Ryazanov #define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */ 753ed7a2a7SSergey Ryazanov 763ed7a2a7SSergey Ryazanov #define AR2315_PCI_IN_DIS 0x0104 773ed7a2a7SSergey Ryazanov 783ed7a2a7SSergey Ryazanov #define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */ 793ed7a2a7SSergey Ryazanov #define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */ 803ed7a2a7SSergey Ryazanov #define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */ 813ed7a2a7SSergey Ryazanov #define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */ 823ed7a2a7SSergey Ryazanov 833ed7a2a7SSergey Ryazanov #define AR2315_PCI_IN_PTR 0x0200 843ed7a2a7SSergey Ryazanov 853ed7a2a7SSergey Ryazanov #define AR2315_PCI_OUT_EN 0x0400 863ed7a2a7SSergey Ryazanov 873ed7a2a7SSergey Ryazanov #define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */ 883ed7a2a7SSergey Ryazanov 893ed7a2a7SSergey Ryazanov #define AR2315_PCI_OUT_DIS 0x0404 903ed7a2a7SSergey Ryazanov 913ed7a2a7SSergey Ryazanov #define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */ 923ed7a2a7SSergey Ryazanov 933ed7a2a7SSergey Ryazanov #define AR2315_PCI_OUT_PTR 0x0408 943ed7a2a7SSergey Ryazanov 953ed7a2a7SSergey Ryazanov /* PCI interrupt status (write one to clear) */ 963ed7a2a7SSergey Ryazanov #define AR2315_PCI_ISR 0x0500 973ed7a2a7SSergey Ryazanov 983ed7a2a7SSergey Ryazanov #define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */ 993ed7a2a7SSergey Ryazanov #define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */ 1003ed7a2a7SSergey Ryazanov #define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */ 1013ed7a2a7SSergey Ryazanov #define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */ 1023ed7a2a7SSergey Ryazanov #define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */ 1033ed7a2a7SSergey Ryazanov #define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */ 1043ed7a2a7SSergey Ryazanov #define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */ 1053ed7a2a7SSergey Ryazanov #define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */ 1063ed7a2a7SSergey Ryazanov #define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */ 1073ed7a2a7SSergey Ryazanov #define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */ 1083ed7a2a7SSergey Ryazanov #define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */ 1093ed7a2a7SSergey Ryazanov #define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */ 1103ed7a2a7SSergey Ryazanov 1113ed7a2a7SSergey Ryazanov /* PCI interrupt mask */ 1123ed7a2a7SSergey Ryazanov #define AR2315_PCI_IMR 0x0504 1133ed7a2a7SSergey Ryazanov 1143ed7a2a7SSergey Ryazanov /* Global PCI interrupt enable */ 1153ed7a2a7SSergey Ryazanov #define AR2315_PCI_IER 0x0508 1163ed7a2a7SSergey Ryazanov 1173ed7a2a7SSergey Ryazanov #define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */ 1183ed7a2a7SSergey Ryazanov #define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */ 1193ed7a2a7SSergey Ryazanov 1203ed7a2a7SSergey Ryazanov #define AR2315_PCI_HOST_IN_EN 0x0800 1213ed7a2a7SSergey Ryazanov #define AR2315_PCI_HOST_IN_DIS 0x0804 1223ed7a2a7SSergey Ryazanov #define AR2315_PCI_HOST_IN_PTR 0x0810 1233ed7a2a7SSergey Ryazanov #define AR2315_PCI_HOST_OUT_EN 0x0900 1243ed7a2a7SSergey Ryazanov #define AR2315_PCI_HOST_OUT_DIS 0x0904 1253ed7a2a7SSergey Ryazanov #define AR2315_PCI_HOST_OUT_PTR 0x0908 1263ed7a2a7SSergey Ryazanov 1273ed7a2a7SSergey Ryazanov /* 1283ed7a2a7SSergey Ryazanov * PCI interrupts, which share IP5 1293ed7a2a7SSergey Ryazanov * Keep ordered according to AR2315_PCI_INT_XXX bits 1303ed7a2a7SSergey Ryazanov */ 1313ed7a2a7SSergey Ryazanov #define AR2315_PCI_IRQ_EXT 25 1323ed7a2a7SSergey Ryazanov #define AR2315_PCI_IRQ_ABORT 26 1333ed7a2a7SSergey Ryazanov #define AR2315_PCI_IRQ_COUNT 27 1343ed7a2a7SSergey Ryazanov 1353ed7a2a7SSergey Ryazanov /* Arbitrary size of memory region to access the configuration space */ 1363ed7a2a7SSergey Ryazanov #define AR2315_PCI_CFG_SIZE 0x00100000 1373ed7a2a7SSergey Ryazanov 1383ed7a2a7SSergey Ryazanov #define AR2315_PCI_HOST_SLOT 3 1393ed7a2a7SSergey Ryazanov #define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS) 1403ed7a2a7SSergey Ryazanov 141d1f2564aSChristoph Hellwig /* 142d1f2564aSChristoph Hellwig * We need some arbitrary non-zero value to be programmed to the BAR1 register 143d1f2564aSChristoph Hellwig * of PCI host controller to enable DMA. The same value should be used as the 144d1f2564aSChristoph Hellwig * offset to calculate the physical address of DMA buffer for PCI devices. 145d1f2564aSChristoph Hellwig */ 146d1f2564aSChristoph Hellwig #define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000 147d1f2564aSChristoph Hellwig 1483ed7a2a7SSergey Ryazanov /* ??? access BAR */ 1493ed7a2a7SSergey Ryazanov #define AR2315_PCI_HOST_MBAR0 0x10000000 1503ed7a2a7SSergey Ryazanov /* RAM access BAR */ 1513ed7a2a7SSergey Ryazanov #define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR 1523ed7a2a7SSergey Ryazanov /* ??? access BAR */ 1533ed7a2a7SSergey Ryazanov #define AR2315_PCI_HOST_MBAR2 0x30000000 1543ed7a2a7SSergey Ryazanov 1553ed7a2a7SSergey Ryazanov struct ar2315_pci_ctrl { 1563ed7a2a7SSergey Ryazanov void __iomem *cfg_mem; 1573ed7a2a7SSergey Ryazanov void __iomem *mmr_mem; 1583ed7a2a7SSergey Ryazanov unsigned irq; 1593ed7a2a7SSergey Ryazanov unsigned irq_ext; 1603ed7a2a7SSergey Ryazanov struct irq_domain *domain; 1613ed7a2a7SSergey Ryazanov struct pci_controller pci_ctrl; 1623ed7a2a7SSergey Ryazanov struct resource mem_res; 1633ed7a2a7SSergey Ryazanov struct resource io_res; 1643ed7a2a7SSergey Ryazanov }; 1653ed7a2a7SSergey Ryazanov 166d1f2564aSChristoph Hellwig static inline dma_addr_t ar2315_dev_offset(struct device *dev) 167d1f2564aSChristoph Hellwig { 168d1f2564aSChristoph Hellwig if (dev && dev_is_pci(dev)) 169d1f2564aSChristoph Hellwig return AR2315_PCI_HOST_SDRAM_BASEADDR; 170d1f2564aSChristoph Hellwig return 0; 171d1f2564aSChristoph Hellwig } 172d1f2564aSChristoph Hellwig 173d1f2564aSChristoph Hellwig dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr) 174d1f2564aSChristoph Hellwig { 175d1f2564aSChristoph Hellwig return paddr + ar2315_dev_offset(dev); 176d1f2564aSChristoph Hellwig } 177d1f2564aSChristoph Hellwig 178d1f2564aSChristoph Hellwig phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr) 179d1f2564aSChristoph Hellwig { 180d1f2564aSChristoph Hellwig return dma_addr - ar2315_dev_offset(dev); 181d1f2564aSChristoph Hellwig } 182d1f2564aSChristoph Hellwig 1833ed7a2a7SSergey Ryazanov static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus) 1843ed7a2a7SSergey Ryazanov { 1853ed7a2a7SSergey Ryazanov struct pci_controller *hose = bus->sysdata; 1863ed7a2a7SSergey Ryazanov 1873ed7a2a7SSergey Ryazanov return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl); 1883ed7a2a7SSergey Ryazanov } 1893ed7a2a7SSergey Ryazanov 1903ed7a2a7SSergey Ryazanov static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg) 1913ed7a2a7SSergey Ryazanov { 1923ed7a2a7SSergey Ryazanov return __raw_readl(apc->mmr_mem + reg); 1933ed7a2a7SSergey Ryazanov } 1943ed7a2a7SSergey Ryazanov 1953ed7a2a7SSergey Ryazanov static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg, 1963ed7a2a7SSergey Ryazanov u32 val) 1973ed7a2a7SSergey Ryazanov { 1983ed7a2a7SSergey Ryazanov __raw_writel(val, apc->mmr_mem + reg); 1993ed7a2a7SSergey Ryazanov } 2003ed7a2a7SSergey Ryazanov 2013ed7a2a7SSergey Ryazanov static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg, 2023ed7a2a7SSergey Ryazanov u32 mask, u32 val) 2033ed7a2a7SSergey Ryazanov { 2043ed7a2a7SSergey Ryazanov u32 ret = ar2315_pci_reg_read(apc, reg); 2053ed7a2a7SSergey Ryazanov 2063ed7a2a7SSergey Ryazanov ret &= ~mask; 2073ed7a2a7SSergey Ryazanov ret |= val; 2083ed7a2a7SSergey Ryazanov ar2315_pci_reg_write(apc, reg, ret); 2093ed7a2a7SSergey Ryazanov } 2103ed7a2a7SSergey Ryazanov 2113ed7a2a7SSergey Ryazanov static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn, 2123ed7a2a7SSergey Ryazanov int where, int size, u32 *ptr, bool write) 2133ed7a2a7SSergey Ryazanov { 2143ed7a2a7SSergey Ryazanov int func = PCI_FUNC(devfn); 2153ed7a2a7SSergey Ryazanov int dev = PCI_SLOT(devfn); 2163ed7a2a7SSergey Ryazanov u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3); 2173ed7a2a7SSergey Ryazanov u32 mask = 0xffffffff >> 8 * (4 - size); 2183ed7a2a7SSergey Ryazanov u32 sh = (where & 3) * 8; 2193ed7a2a7SSergey Ryazanov u32 value, isr; 2203ed7a2a7SSergey Ryazanov 2213ed7a2a7SSergey Ryazanov /* Prevent access past the remapped area */ 2223ed7a2a7SSergey Ryazanov if (addr >= AR2315_PCI_CFG_SIZE || dev > 18) 2233ed7a2a7SSergey Ryazanov return PCIBIOS_DEVICE_NOT_FOUND; 2243ed7a2a7SSergey Ryazanov 2253ed7a2a7SSergey Ryazanov /* Clear pending errors */ 2263ed7a2a7SSergey Ryazanov ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT); 2273ed7a2a7SSergey Ryazanov /* Select Configuration access */ 2283ed7a2a7SSergey Ryazanov ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0, 2293ed7a2a7SSergey Ryazanov AR2315_PCIMISC_CFG_SEL); 2303ed7a2a7SSergey Ryazanov 2313ed7a2a7SSergey Ryazanov mb(); /* PCI must see space change before we begin */ 2323ed7a2a7SSergey Ryazanov 2333ed7a2a7SSergey Ryazanov value = __raw_readl(apc->cfg_mem + addr); 2343ed7a2a7SSergey Ryazanov 2353ed7a2a7SSergey Ryazanov isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR); 2363ed7a2a7SSergey Ryazanov 2373ed7a2a7SSergey Ryazanov if (isr & AR2315_PCI_INT_ABORT) 2383ed7a2a7SSergey Ryazanov goto exit_err; 2393ed7a2a7SSergey Ryazanov 2403ed7a2a7SSergey Ryazanov if (write) { 2413ed7a2a7SSergey Ryazanov value = (value & ~(mask << sh)) | *ptr << sh; 2423ed7a2a7SSergey Ryazanov __raw_writel(value, apc->cfg_mem + addr); 2433ed7a2a7SSergey Ryazanov isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR); 2443ed7a2a7SSergey Ryazanov if (isr & AR2315_PCI_INT_ABORT) 2453ed7a2a7SSergey Ryazanov goto exit_err; 2463ed7a2a7SSergey Ryazanov } else { 2473ed7a2a7SSergey Ryazanov *ptr = (value >> sh) & mask; 2483ed7a2a7SSergey Ryazanov } 2493ed7a2a7SSergey Ryazanov 2503ed7a2a7SSergey Ryazanov goto exit; 2513ed7a2a7SSergey Ryazanov 2523ed7a2a7SSergey Ryazanov exit_err: 2533ed7a2a7SSergey Ryazanov ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT); 2543ed7a2a7SSergey Ryazanov if (!write) 2553ed7a2a7SSergey Ryazanov *ptr = 0xffffffff; 2563ed7a2a7SSergey Ryazanov 2573ed7a2a7SSergey Ryazanov exit: 2583ed7a2a7SSergey Ryazanov /* Select Memory access */ 2593ed7a2a7SSergey Ryazanov ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 2603ed7a2a7SSergey Ryazanov 0); 2613ed7a2a7SSergey Ryazanov 2623ed7a2a7SSergey Ryazanov return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND : 2633ed7a2a7SSergey Ryazanov PCIBIOS_SUCCESSFUL; 2643ed7a2a7SSergey Ryazanov } 2653ed7a2a7SSergey Ryazanov 2663ed7a2a7SSergey Ryazanov static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc, 2673ed7a2a7SSergey Ryazanov unsigned devfn, int where, u32 *val) 2683ed7a2a7SSergey Ryazanov { 2693ed7a2a7SSergey Ryazanov return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val, 2703ed7a2a7SSergey Ryazanov false); 2713ed7a2a7SSergey Ryazanov } 2723ed7a2a7SSergey Ryazanov 2733ed7a2a7SSergey Ryazanov static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc, 2743ed7a2a7SSergey Ryazanov unsigned devfn, int where, u32 val) 2753ed7a2a7SSergey Ryazanov { 2763ed7a2a7SSergey Ryazanov return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val, 2773ed7a2a7SSergey Ryazanov true); 2783ed7a2a7SSergey Ryazanov } 2793ed7a2a7SSergey Ryazanov 2803ed7a2a7SSergey Ryazanov static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where, 2813ed7a2a7SSergey Ryazanov int size, u32 *value) 2823ed7a2a7SSergey Ryazanov { 2833ed7a2a7SSergey Ryazanov struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus); 2843ed7a2a7SSergey Ryazanov 2853ed7a2a7SSergey Ryazanov if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT) 2863ed7a2a7SSergey Ryazanov return PCIBIOS_DEVICE_NOT_FOUND; 2873ed7a2a7SSergey Ryazanov 2883ed7a2a7SSergey Ryazanov return ar2315_pci_cfg_access(apc, devfn, where, size, value, false); 2893ed7a2a7SSergey Ryazanov } 2903ed7a2a7SSergey Ryazanov 2913ed7a2a7SSergey Ryazanov static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where, 2923ed7a2a7SSergey Ryazanov int size, u32 value) 2933ed7a2a7SSergey Ryazanov { 2943ed7a2a7SSergey Ryazanov struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus); 2953ed7a2a7SSergey Ryazanov 2963ed7a2a7SSergey Ryazanov if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT) 2973ed7a2a7SSergey Ryazanov return PCIBIOS_DEVICE_NOT_FOUND; 2983ed7a2a7SSergey Ryazanov 2993ed7a2a7SSergey Ryazanov return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true); 3003ed7a2a7SSergey Ryazanov } 3013ed7a2a7SSergey Ryazanov 3023ed7a2a7SSergey Ryazanov static struct pci_ops ar2315_pci_ops = { 3033ed7a2a7SSergey Ryazanov .read = ar2315_pci_cfg_read, 3043ed7a2a7SSergey Ryazanov .write = ar2315_pci_cfg_write, 3053ed7a2a7SSergey Ryazanov }; 3063ed7a2a7SSergey Ryazanov 3073ed7a2a7SSergey Ryazanov static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc) 3083ed7a2a7SSergey Ryazanov { 3093ed7a2a7SSergey Ryazanov unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0); 3103ed7a2a7SSergey Ryazanov int res; 3113ed7a2a7SSergey Ryazanov u32 id; 3123ed7a2a7SSergey Ryazanov 3133ed7a2a7SSergey Ryazanov res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id); 3143ed7a2a7SSergey Ryazanov if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID) 3153ed7a2a7SSergey Ryazanov return -ENODEV; 3163ed7a2a7SSergey Ryazanov 3173ed7a2a7SSergey Ryazanov /* Program MBARs */ 3183ed7a2a7SSergey Ryazanov ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0, 3193ed7a2a7SSergey Ryazanov AR2315_PCI_HOST_MBAR0); 3203ed7a2a7SSergey Ryazanov ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1, 3213ed7a2a7SSergey Ryazanov AR2315_PCI_HOST_MBAR1); 3223ed7a2a7SSergey Ryazanov ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2, 3233ed7a2a7SSergey Ryazanov AR2315_PCI_HOST_MBAR2); 3243ed7a2a7SSergey Ryazanov 3253ed7a2a7SSergey Ryazanov /* Run */ 3263ed7a2a7SSergey Ryazanov ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY | 3273ed7a2a7SSergey Ryazanov PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | 3283ed7a2a7SSergey Ryazanov PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | 3293ed7a2a7SSergey Ryazanov PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK); 3303ed7a2a7SSergey Ryazanov 3313ed7a2a7SSergey Ryazanov return 0; 3323ed7a2a7SSergey Ryazanov } 3333ed7a2a7SSergey Ryazanov 334bd0b9ac4SThomas Gleixner static void ar2315_pci_irq_handler(struct irq_desc *desc) 3353ed7a2a7SSergey Ryazanov { 33625aae561SJiang Liu struct ar2315_pci_ctrl *apc = irq_desc_get_handler_data(desc); 3373ed7a2a7SSergey Ryazanov u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) & 3383ed7a2a7SSergey Ryazanov ar2315_pci_reg_read(apc, AR2315_PCI_IMR); 3393ed7a2a7SSergey Ryazanov unsigned pci_irq = 0; 3403ed7a2a7SSergey Ryazanov 3413ed7a2a7SSergey Ryazanov if (pending) 3423ed7a2a7SSergey Ryazanov pci_irq = irq_find_mapping(apc->domain, __ffs(pending)); 3433ed7a2a7SSergey Ryazanov 3443ed7a2a7SSergey Ryazanov if (pci_irq) 3453ed7a2a7SSergey Ryazanov generic_handle_irq(pci_irq); 3463ed7a2a7SSergey Ryazanov else 3473ed7a2a7SSergey Ryazanov spurious_interrupt(); 3483ed7a2a7SSergey Ryazanov } 3493ed7a2a7SSergey Ryazanov 3503ed7a2a7SSergey Ryazanov static void ar2315_pci_irq_mask(struct irq_data *d) 3513ed7a2a7SSergey Ryazanov { 3523ed7a2a7SSergey Ryazanov struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d); 3533ed7a2a7SSergey Ryazanov 3543ed7a2a7SSergey Ryazanov ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0); 3553ed7a2a7SSergey Ryazanov } 3563ed7a2a7SSergey Ryazanov 3573ed7a2a7SSergey Ryazanov static void ar2315_pci_irq_mask_ack(struct irq_data *d) 3583ed7a2a7SSergey Ryazanov { 3593ed7a2a7SSergey Ryazanov struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d); 3603ed7a2a7SSergey Ryazanov u32 m = BIT(d->hwirq); 3613ed7a2a7SSergey Ryazanov 3623ed7a2a7SSergey Ryazanov ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0); 3633ed7a2a7SSergey Ryazanov ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m); 3643ed7a2a7SSergey Ryazanov } 3653ed7a2a7SSergey Ryazanov 3663ed7a2a7SSergey Ryazanov static void ar2315_pci_irq_unmask(struct irq_data *d) 3673ed7a2a7SSergey Ryazanov { 3683ed7a2a7SSergey Ryazanov struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d); 3693ed7a2a7SSergey Ryazanov 3703ed7a2a7SSergey Ryazanov ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq)); 3713ed7a2a7SSergey Ryazanov } 3723ed7a2a7SSergey Ryazanov 3733ed7a2a7SSergey Ryazanov static struct irq_chip ar2315_pci_irq_chip = { 3743ed7a2a7SSergey Ryazanov .name = "AR2315-PCI", 3753ed7a2a7SSergey Ryazanov .irq_mask = ar2315_pci_irq_mask, 3763ed7a2a7SSergey Ryazanov .irq_mask_ack = ar2315_pci_irq_mask_ack, 3773ed7a2a7SSergey Ryazanov .irq_unmask = ar2315_pci_irq_unmask, 3783ed7a2a7SSergey Ryazanov }; 3793ed7a2a7SSergey Ryazanov 3803ed7a2a7SSergey Ryazanov static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq, 3813ed7a2a7SSergey Ryazanov irq_hw_number_t hw) 3823ed7a2a7SSergey Ryazanov { 3833ed7a2a7SSergey Ryazanov irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq); 3843ed7a2a7SSergey Ryazanov irq_set_chip_data(irq, d->host_data); 3853ed7a2a7SSergey Ryazanov return 0; 3863ed7a2a7SSergey Ryazanov } 3873ed7a2a7SSergey Ryazanov 3883ed7a2a7SSergey Ryazanov static struct irq_domain_ops ar2315_pci_irq_domain_ops = { 3893ed7a2a7SSergey Ryazanov .map = ar2315_pci_irq_map, 3903ed7a2a7SSergey Ryazanov }; 3913ed7a2a7SSergey Ryazanov 3923ed7a2a7SSergey Ryazanov static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc) 3933ed7a2a7SSergey Ryazanov { 3943ed7a2a7SSergey Ryazanov ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0); 3953ed7a2a7SSergey Ryazanov ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT | 3963ed7a2a7SSergey Ryazanov AR2315_PCI_INT_EXT), 0); 3973ed7a2a7SSergey Ryazanov 3983ed7a2a7SSergey Ryazanov apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT); 3993ed7a2a7SSergey Ryazanov 400746ad9a7SThomas Gleixner irq_set_chained_handler_and_data(apc->irq, ar2315_pci_irq_handler, 401746ad9a7SThomas Gleixner apc); 4023ed7a2a7SSergey Ryazanov 4033ed7a2a7SSergey Ryazanov /* Clear any pending Abort or external Interrupts 4043ed7a2a7SSergey Ryazanov * and enable interrupt processing */ 4053ed7a2a7SSergey Ryazanov ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT | 4063ed7a2a7SSergey Ryazanov AR2315_PCI_INT_EXT); 4073ed7a2a7SSergey Ryazanov ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE); 4083ed7a2a7SSergey Ryazanov } 4093ed7a2a7SSergey Ryazanov 4103ed7a2a7SSergey Ryazanov static int ar2315_pci_probe(struct platform_device *pdev) 4113ed7a2a7SSergey Ryazanov { 4123ed7a2a7SSergey Ryazanov struct ar2315_pci_ctrl *apc; 4133ed7a2a7SSergey Ryazanov struct device *dev = &pdev->dev; 4143ed7a2a7SSergey Ryazanov struct resource *res; 4153ed7a2a7SSergey Ryazanov int irq, err; 4163ed7a2a7SSergey Ryazanov 4173ed7a2a7SSergey Ryazanov apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL); 4183ed7a2a7SSergey Ryazanov if (!apc) 4193ed7a2a7SSergey Ryazanov return -ENOMEM; 4203ed7a2a7SSergey Ryazanov 4213ed7a2a7SSergey Ryazanov irq = platform_get_irq(pdev, 0); 4223ed7a2a7SSergey Ryazanov if (irq < 0) 4233ed7a2a7SSergey Ryazanov return -EINVAL; 4243ed7a2a7SSergey Ryazanov apc->irq = irq; 4253ed7a2a7SSergey Ryazanov 4263ed7a2a7SSergey Ryazanov res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 4273ed7a2a7SSergey Ryazanov "ar2315-pci-ctrl"); 4283ed7a2a7SSergey Ryazanov apc->mmr_mem = devm_ioremap_resource(dev, res); 4293ed7a2a7SSergey Ryazanov if (IS_ERR(apc->mmr_mem)) 4303ed7a2a7SSergey Ryazanov return PTR_ERR(apc->mmr_mem); 4313ed7a2a7SSergey Ryazanov 4323ed7a2a7SSergey Ryazanov res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 4333ed7a2a7SSergey Ryazanov "ar2315-pci-ext"); 4343ed7a2a7SSergey Ryazanov if (!res) 4353ed7a2a7SSergey Ryazanov return -EINVAL; 4363ed7a2a7SSergey Ryazanov 4373ed7a2a7SSergey Ryazanov apc->mem_res.name = "AR2315 PCI mem space"; 4383ed7a2a7SSergey Ryazanov apc->mem_res.parent = res; 4393ed7a2a7SSergey Ryazanov apc->mem_res.start = res->start; 4403ed7a2a7SSergey Ryazanov apc->mem_res.end = res->end; 4413ed7a2a7SSergey Ryazanov apc->mem_res.flags = IORESOURCE_MEM; 4423ed7a2a7SSergey Ryazanov 4433ed7a2a7SSergey Ryazanov /* Remap PCI config space */ 4444bdc0d67SChristoph Hellwig apc->cfg_mem = devm_ioremap(dev, res->start, 4453ed7a2a7SSergey Ryazanov AR2315_PCI_CFG_SIZE); 4463ed7a2a7SSergey Ryazanov if (!apc->cfg_mem) { 4473ed7a2a7SSergey Ryazanov dev_err(dev, "failed to remap PCI config space\n"); 4483ed7a2a7SSergey Ryazanov return -ENOMEM; 4493ed7a2a7SSergey Ryazanov } 4503ed7a2a7SSergey Ryazanov 4513ed7a2a7SSergey Ryazanov /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */ 4523ed7a2a7SSergey Ryazanov ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 4533ed7a2a7SSergey Ryazanov AR2315_PCIMISC_RST_MODE, 4543ed7a2a7SSergey Ryazanov AR2315_PCIRST_LOW); 4553ed7a2a7SSergey Ryazanov msleep(100); 4563ed7a2a7SSergey Ryazanov 4573ed7a2a7SSergey Ryazanov /* Bring the PCI out of reset */ 4583ed7a2a7SSergey Ryazanov ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 4593ed7a2a7SSergey Ryazanov AR2315_PCIMISC_RST_MODE, 4603ed7a2a7SSergey Ryazanov AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8); 4613ed7a2a7SSergey Ryazanov 4623ed7a2a7SSergey Ryazanov ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG, 4633ed7a2a7SSergey Ryazanov 0x1E | /* 1GB uncached */ 4643ed7a2a7SSergey Ryazanov (1 << 5) | /* Enable uncached */ 4653ed7a2a7SSergey Ryazanov (0x2 << 30) /* Base: 0x80000000 */); 4663ed7a2a7SSergey Ryazanov ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG); 4673ed7a2a7SSergey Ryazanov 4683ed7a2a7SSergey Ryazanov msleep(500); 4693ed7a2a7SSergey Ryazanov 4703ed7a2a7SSergey Ryazanov err = ar2315_pci_host_setup(apc); 4713ed7a2a7SSergey Ryazanov if (err) 4723ed7a2a7SSergey Ryazanov return err; 4733ed7a2a7SSergey Ryazanov 4743ed7a2a7SSergey Ryazanov apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT, 4753ed7a2a7SSergey Ryazanov &ar2315_pci_irq_domain_ops, apc); 4763ed7a2a7SSergey Ryazanov if (!apc->domain) { 4773ed7a2a7SSergey Ryazanov dev_err(dev, "failed to add IRQ domain\n"); 4783ed7a2a7SSergey Ryazanov return -ENOMEM; 4793ed7a2a7SSergey Ryazanov } 4803ed7a2a7SSergey Ryazanov 4813ed7a2a7SSergey Ryazanov ar2315_pci_irq_init(apc); 4823ed7a2a7SSergey Ryazanov 4833ed7a2a7SSergey Ryazanov /* PCI controller does not support I/O ports */ 4843ed7a2a7SSergey Ryazanov apc->io_res.name = "AR2315 IO space"; 4853ed7a2a7SSergey Ryazanov apc->io_res.start = 0; 4863ed7a2a7SSergey Ryazanov apc->io_res.end = 0; 4873ed7a2a7SSergey Ryazanov apc->io_res.flags = IORESOURCE_IO, 4883ed7a2a7SSergey Ryazanov 4893ed7a2a7SSergey Ryazanov apc->pci_ctrl.pci_ops = &ar2315_pci_ops; 4903ed7a2a7SSergey Ryazanov apc->pci_ctrl.mem_resource = &apc->mem_res, 4913ed7a2a7SSergey Ryazanov apc->pci_ctrl.io_resource = &apc->io_res, 4923ed7a2a7SSergey Ryazanov 4933ed7a2a7SSergey Ryazanov register_pci_controller(&apc->pci_ctrl); 4943ed7a2a7SSergey Ryazanov 4953ed7a2a7SSergey Ryazanov dev_info(dev, "register PCI controller\n"); 4963ed7a2a7SSergey Ryazanov 4973ed7a2a7SSergey Ryazanov return 0; 4983ed7a2a7SSergey Ryazanov } 4993ed7a2a7SSergey Ryazanov 5003ed7a2a7SSergey Ryazanov static struct platform_driver ar2315_pci_driver = { 5013ed7a2a7SSergey Ryazanov .probe = ar2315_pci_probe, 5023ed7a2a7SSergey Ryazanov .driver = { 5033ed7a2a7SSergey Ryazanov .name = "ar2315-pci", 5043ed7a2a7SSergey Ryazanov }, 5053ed7a2a7SSergey Ryazanov }; 5063ed7a2a7SSergey Ryazanov 5073ed7a2a7SSergey Ryazanov static int __init ar2315_pci_init(void) 5083ed7a2a7SSergey Ryazanov { 5093ed7a2a7SSergey Ryazanov return platform_driver_register(&ar2315_pci_driver); 5103ed7a2a7SSergey Ryazanov } 5113ed7a2a7SSergey Ryazanov arch_initcall(ar2315_pci_init); 5123ed7a2a7SSergey Ryazanov 5133ed7a2a7SSergey Ryazanov int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 5143ed7a2a7SSergey Ryazanov { 5153ed7a2a7SSergey Ryazanov struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus); 5163ed7a2a7SSergey Ryazanov 5173ed7a2a7SSergey Ryazanov return slot ? 0 : apc->irq_ext; 5183ed7a2a7SSergey Ryazanov } 5193ed7a2a7SSergey Ryazanov 5203ed7a2a7SSergey Ryazanov int pcibios_plat_dev_init(struct pci_dev *dev) 5213ed7a2a7SSergey Ryazanov { 5223ed7a2a7SSergey Ryazanov return 0; 5233ed7a2a7SSergey Ryazanov } 524