1 /* 2 * Alchemy PCI host mode support. 3 * 4 * Copyright 2001-2003, 2007-2008 MontaVista Software Inc. 5 * Author: MontaVista Software, Inc. <source@mvista.com> 6 * 7 * Support for all devices (greater than 16) added by David Gathright. 8 */ 9 10 #include <linux/export.h> 11 #include <linux/types.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 #include <linux/syscore_ops.h> 17 #include <linux/vmalloc.h> 18 19 #include <asm/dma-coherence.h> 20 #include <asm/mach-au1x00/au1000.h> 21 #include <asm/tlbmisc.h> 22 23 #ifdef CONFIG_PCI_DEBUG 24 #define DBG(x...) printk(KERN_DEBUG x) 25 #else 26 #define DBG(x...) do {} while (0) 27 #endif 28 29 #define PCI_ACCESS_READ 0 30 #define PCI_ACCESS_WRITE 1 31 32 struct alchemy_pci_context { 33 struct pci_controller alchemy_pci_ctrl; /* leave as first member! */ 34 void __iomem *regs; /* ctrl base */ 35 /* tools for wired entry for config space access */ 36 unsigned long last_elo0; 37 unsigned long last_elo1; 38 int wired_entry; 39 struct vm_struct *pci_cfg_vm; 40 41 unsigned long pm[12]; 42 43 int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin); 44 int (*board_pci_idsel)(unsigned int devsel, int assert); 45 }; 46 47 /* for syscore_ops. There's only one PCI controller on Alchemy chips, so this 48 * should suffice for now. 49 */ 50 static struct alchemy_pci_context *__alchemy_pci_ctx; 51 52 53 /* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr 54 * in arch/mips/alchemy/common/setup.c 55 */ 56 static struct resource alchemy_pci_def_memres = { 57 .start = ALCHEMY_PCI_MEMWIN_START, 58 .end = ALCHEMY_PCI_MEMWIN_END, 59 .name = "PCI memory space", 60 .flags = IORESOURCE_MEM 61 }; 62 63 static struct resource alchemy_pci_def_iores = { 64 .start = ALCHEMY_PCI_IOWIN_START, 65 .end = ALCHEMY_PCI_IOWIN_END, 66 .name = "PCI IO space", 67 .flags = IORESOURCE_IO 68 }; 69 70 static void mod_wired_entry(int entry, unsigned long entrylo0, 71 unsigned long entrylo1, unsigned long entryhi, 72 unsigned long pagemask) 73 { 74 unsigned long old_pagemask; 75 unsigned long old_ctx; 76 77 /* Save old context and create impossible VPN2 value */ 78 old_ctx = read_c0_entryhi() & 0xff; 79 old_pagemask = read_c0_pagemask(); 80 write_c0_index(entry); 81 write_c0_pagemask(pagemask); 82 write_c0_entryhi(entryhi); 83 write_c0_entrylo0(entrylo0); 84 write_c0_entrylo1(entrylo1); 85 tlb_write_indexed(); 86 write_c0_entryhi(old_ctx); 87 write_c0_pagemask(old_pagemask); 88 } 89 90 static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx) 91 { 92 ctx->wired_entry = read_c0_wired(); 93 add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K); 94 ctx->last_elo0 = ctx->last_elo1 = ~0; 95 } 96 97 static int config_access(unsigned char access_type, struct pci_bus *bus, 98 unsigned int dev_fn, unsigned char where, u32 *data) 99 { 100 struct alchemy_pci_context *ctx = bus->sysdata; 101 unsigned int device = PCI_SLOT(dev_fn); 102 unsigned int function = PCI_FUNC(dev_fn); 103 unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r; 104 int error = PCIBIOS_SUCCESSFUL; 105 106 if (device > 19) { 107 *data = 0xffffffff; 108 return -1; 109 } 110 111 local_irq_save(flags); 112 r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; 113 r |= PCI_STATCMD_STATUS(0x2000); 114 __raw_writel(r, ctx->regs + PCI_REG_STATCMD); 115 wmb(); 116 117 /* Allow board vendors to implement their own off-chip IDSEL. 118 * If it doesn't succeed, may as well bail out at this point. 119 */ 120 if (ctx->board_pci_idsel(device, 1) == 0) { 121 *data = 0xffffffff; 122 local_irq_restore(flags); 123 return -1; 124 } 125 126 /* Setup the config window */ 127 if (bus->number == 0) 128 cfg_base = (1 << device) << 11; 129 else 130 cfg_base = 0x80000000 | (bus->number << 16) | (device << 11); 131 132 /* Setup the lower bits of the 36-bit address */ 133 offset = (function << 8) | (where & ~0x3); 134 /* Pick up any address that falls below the page mask */ 135 offset |= cfg_base & ~PAGE_MASK; 136 137 /* Page boundary */ 138 cfg_base = cfg_base & PAGE_MASK; 139 140 /* To improve performance, if the current device is the same as 141 * the last device accessed, we don't touch the TLB. 142 */ 143 entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; 144 entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; 145 if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) { 146 mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1, 147 (unsigned long)ctx->pci_cfg_vm->addr, PM_4K); 148 ctx->last_elo0 = entryLo0; 149 ctx->last_elo1 = entryLo1; 150 } 151 152 if (access_type == PCI_ACCESS_WRITE) 153 __raw_writel(*data, ctx->pci_cfg_vm->addr + offset); 154 else 155 *data = __raw_readl(ctx->pci_cfg_vm->addr + offset); 156 wmb(); 157 158 DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n", 159 access_type, bus->number, device, where, *data, offset); 160 161 /* check for errors, master abort */ 162 status = __raw_readl(ctx->regs + PCI_REG_STATCMD); 163 if (status & (1 << 29)) { 164 *data = 0xffffffff; 165 error = -1; 166 DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n", 167 access_type, bus->number, device); 168 } else if ((status >> 28) & 0xf) { 169 DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n", 170 device, (status >> 28) & 0xf); 171 172 /* clear errors */ 173 __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD); 174 175 *data = 0xffffffff; 176 error = -1; 177 } 178 179 /* Take away the IDSEL. */ 180 (void)ctx->board_pci_idsel(device, 0); 181 182 local_irq_restore(flags); 183 return error; 184 } 185 186 static int read_config_byte(struct pci_bus *bus, unsigned int devfn, 187 int where, u8 *val) 188 { 189 u32 data; 190 int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); 191 192 if (where & 1) 193 data >>= 8; 194 if (where & 2) 195 data >>= 16; 196 *val = data & 0xff; 197 return ret; 198 } 199 200 static int read_config_word(struct pci_bus *bus, unsigned int devfn, 201 int where, u16 *val) 202 { 203 u32 data; 204 int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); 205 206 if (where & 2) 207 data >>= 16; 208 *val = data & 0xffff; 209 return ret; 210 } 211 212 static int read_config_dword(struct pci_bus *bus, unsigned int devfn, 213 int where, u32 *val) 214 { 215 return config_access(PCI_ACCESS_READ, bus, devfn, where, val); 216 } 217 218 static int write_config_byte(struct pci_bus *bus, unsigned int devfn, 219 int where, u8 val) 220 { 221 u32 data = 0; 222 223 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) 224 return -1; 225 226 data = (data & ~(0xff << ((where & 3) << 3))) | 227 (val << ((where & 3) << 3)); 228 229 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) 230 return -1; 231 232 return PCIBIOS_SUCCESSFUL; 233 } 234 235 static int write_config_word(struct pci_bus *bus, unsigned int devfn, 236 int where, u16 val) 237 { 238 u32 data = 0; 239 240 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) 241 return -1; 242 243 data = (data & ~(0xffff << ((where & 3) << 3))) | 244 (val << ((where & 3) << 3)); 245 246 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) 247 return -1; 248 249 return PCIBIOS_SUCCESSFUL; 250 } 251 252 static int write_config_dword(struct pci_bus *bus, unsigned int devfn, 253 int where, u32 val) 254 { 255 return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val); 256 } 257 258 static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn, 259 int where, int size, u32 *val) 260 { 261 switch (size) { 262 case 1: { 263 u8 _val; 264 int rc = read_config_byte(bus, devfn, where, &_val); 265 266 *val = _val; 267 return rc; 268 } 269 case 2: { 270 u16 _val; 271 int rc = read_config_word(bus, devfn, where, &_val); 272 273 *val = _val; 274 return rc; 275 } 276 default: 277 return read_config_dword(bus, devfn, where, val); 278 } 279 } 280 281 static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn, 282 int where, int size, u32 val) 283 { 284 switch (size) { 285 case 1: 286 return write_config_byte(bus, devfn, where, (u8) val); 287 case 2: 288 return write_config_word(bus, devfn, where, (u16) val); 289 default: 290 return write_config_dword(bus, devfn, where, val); 291 } 292 } 293 294 static struct pci_ops alchemy_pci_ops = { 295 .read = alchemy_pci_read, 296 .write = alchemy_pci_write, 297 }; 298 299 static int alchemy_pci_def_idsel(unsigned int devsel, int assert) 300 { 301 return 1; /* success */ 302 } 303 304 /* save PCI controller register contents. */ 305 static int alchemy_pci_suspend(void) 306 { 307 struct alchemy_pci_context *ctx = __alchemy_pci_ctx; 308 if (!ctx) 309 return 0; 310 311 ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); 312 ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; 313 ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); 314 ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); 315 ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); 316 ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); 317 ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); 318 ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID); 319 ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV); 320 ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM); 321 ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR); 322 ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT); 323 324 return 0; 325 } 326 327 static void alchemy_pci_resume(void) 328 { 329 struct alchemy_pci_context *ctx = __alchemy_pci_ctx; 330 if (!ctx) 331 return; 332 333 __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); 334 __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); 335 __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID); 336 __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID); 337 __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV); 338 __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL); 339 __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID); 340 __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV); 341 __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM); 342 __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR); 343 __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT); 344 wmb(); 345 __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG); 346 wmb(); 347 348 /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired 349 * on resume, making it necessary to recreate it as soon as possible. 350 */ 351 ctx->wired_entry = 8191; /* impossibly high value */ 352 alchemy_pci_wired_entry(ctx); /* install it */ 353 } 354 355 static struct syscore_ops alchemy_pci_pmops = { 356 .suspend = alchemy_pci_suspend, 357 .resume = alchemy_pci_resume, 358 }; 359 360 static int alchemy_pci_probe(struct platform_device *pdev) 361 { 362 struct alchemy_pci_platdata *pd = pdev->dev.platform_data; 363 struct alchemy_pci_context *ctx; 364 void __iomem *virt_io; 365 unsigned long val; 366 struct resource *r; 367 int ret; 368 369 /* need at least PCI IRQ mapping table */ 370 if (!pd) { 371 dev_err(&pdev->dev, "need platform data for PCI setup\n"); 372 ret = -ENODEV; 373 goto out; 374 } 375 376 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 377 if (!ctx) { 378 dev_err(&pdev->dev, "no memory for pcictl context\n"); 379 ret = -ENOMEM; 380 goto out; 381 } 382 383 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 384 if (!r) { 385 dev_err(&pdev->dev, "no pcictl ctrl regs resource\n"); 386 ret = -ENODEV; 387 goto out1; 388 } 389 390 if (!request_mem_region(r->start, resource_size(r), pdev->name)) { 391 dev_err(&pdev->dev, "cannot claim pci regs\n"); 392 ret = -ENODEV; 393 goto out1; 394 } 395 396 ctx->regs = ioremap_nocache(r->start, resource_size(r)); 397 if (!ctx->regs) { 398 dev_err(&pdev->dev, "cannot map pci regs\n"); 399 ret = -ENODEV; 400 goto out2; 401 } 402 403 /* map parts of the PCI IO area */ 404 /* REVISIT: if this changes with a newer variant (doubt it) make this 405 * a platform resource. 406 */ 407 virt_io = ioremap(AU1500_PCI_IO_PHYS_ADDR, 0x00100000); 408 if (!virt_io) { 409 dev_err(&pdev->dev, "cannot remap pci io space\n"); 410 ret = -ENODEV; 411 goto out3; 412 } 413 ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io; 414 415 /* Au1500 revisions older than AD have borked coherent PCI */ 416 if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) && 417 (read_c0_prid() < 0x01030202) && !coherentio) { 418 val = __raw_readl(ctx->regs + PCI_REG_CONFIG); 419 val |= PCI_CONFIG_NC; 420 __raw_writel(val, ctx->regs + PCI_REG_CONFIG); 421 wmb(); 422 dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n"); 423 } 424 425 if (pd->board_map_irq) 426 ctx->board_map_irq = pd->board_map_irq; 427 428 if (pd->board_pci_idsel) 429 ctx->board_pci_idsel = pd->board_pci_idsel; 430 else 431 ctx->board_pci_idsel = alchemy_pci_def_idsel; 432 433 /* fill in relevant pci_controller members */ 434 ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops; 435 ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres; 436 ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores; 437 438 /* we can't ioremap the entire pci config space because it's too large, 439 * nor can we dynamically ioremap it because some drivers use the 440 * PCI config routines from within atomic contex and that becomes a 441 * problem in get_vm_area(). Instead we use one wired TLB entry to 442 * handle all config accesses for all busses. 443 */ 444 ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); 445 if (!ctx->pci_cfg_vm) { 446 dev_err(&pdev->dev, "unable to get vm area\n"); 447 ret = -ENOMEM; 448 goto out4; 449 } 450 ctx->wired_entry = 8191; /* impossibly high value */ 451 alchemy_pci_wired_entry(ctx); /* install it */ 452 453 set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base); 454 455 /* board may want to modify bits in the config register, do it now */ 456 val = __raw_readl(ctx->regs + PCI_REG_CONFIG); 457 val &= ~pd->pci_cfg_clr; 458 val |= pd->pci_cfg_set; 459 val &= ~PCI_CONFIG_PD; /* clear disable bit */ 460 __raw_writel(val, ctx->regs + PCI_REG_CONFIG); 461 wmb(); 462 463 __alchemy_pci_ctx = ctx; 464 platform_set_drvdata(pdev, ctx); 465 register_syscore_ops(&alchemy_pci_pmops); 466 register_pci_controller(&ctx->alchemy_pci_ctrl); 467 468 return 0; 469 470 out4: 471 iounmap(virt_io); 472 out3: 473 iounmap(ctx->regs); 474 out2: 475 release_mem_region(r->start, resource_size(r)); 476 out1: 477 kfree(ctx); 478 out: 479 return ret; 480 } 481 482 static struct platform_driver alchemy_pcictl_driver = { 483 .probe = alchemy_pci_probe, 484 .driver = { 485 .name = "alchemy-pci", 486 .owner = THIS_MODULE, 487 }, 488 }; 489 490 static int __init alchemy_pci_init(void) 491 { 492 /* Au1500/Au1550 have PCI */ 493 switch (alchemy_get_cputype()) { 494 case ALCHEMY_CPU_AU1500: 495 case ALCHEMY_CPU_AU1550: 496 return platform_driver_register(&alchemy_pcictl_driver); 497 } 498 return 0; 499 } 500 arch_initcall(alchemy_pci_init); 501 502 503 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 504 { 505 struct alchemy_pci_context *ctx = dev->sysdata; 506 if (ctx && ctx->board_map_irq) 507 return ctx->board_map_irq(dev, slot, pin); 508 return -1; 509 } 510 511 int pcibios_plat_dev_init(struct pci_dev *dev) 512 { 513 return 0; 514 } 515