1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc. 4 * 5 * Based on linux/arch/mips/pci/ops-tx4938.c, 6 * linux/arch/mips/pci/fixup-rbtx4938.c, 7 * linux/arch/mips/txx9/rbtx4938/setup.c, 8 * and RBTX49xx patch from CELF patch archive. 9 * 10 * 2003-2005 (c) MontaVista Software, Inc. 11 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 12 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 13 */ 14 #include <linux/kernel.h> 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <asm/txx9/pci.h> 18 #include <asm/txx9/tx4927pcic.h> 19 20 static struct { 21 struct pci_controller *channel; 22 struct tx4927_pcic_reg __iomem *pcicptr; 23 } pcicptrs[2]; /* TX4938 has 2 pcic */ 24 25 static void __init set_tx4927_pcicptr(struct pci_controller *channel, 26 struct tx4927_pcic_reg __iomem *pcicptr) 27 { 28 int i; 29 30 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { 31 if (pcicptrs[i].channel == channel) { 32 pcicptrs[i].pcicptr = pcicptr; 33 return; 34 } 35 } 36 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { 37 if (!pcicptrs[i].channel) { 38 pcicptrs[i].channel = channel; 39 pcicptrs[i].pcicptr = pcicptr; 40 return; 41 } 42 } 43 BUG(); 44 } 45 46 struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( 47 struct pci_controller *channel) 48 { 49 int i; 50 51 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { 52 if (pcicptrs[i].channel == channel) 53 return pcicptrs[i].pcicptr; 54 } 55 return NULL; 56 } 57 58 static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where, 59 struct tx4927_pcic_reg __iomem *pcicptr) 60 { 61 if (bus->parent == NULL && 62 devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0)) 63 return -1; 64 __raw_writel(((bus->number & 0xff) << 0x10) 65 | ((devfn & 0xff) << 0x08) | (where & 0xfc) 66 | (bus->parent ? 1 : 0), 67 &pcicptr->g2pcfgadrs); 68 /* clear M_ABORT and Disable M_ABORT Int. */ 69 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) 70 | (PCI_STATUS_REC_MASTER_ABORT << 16), 71 &pcicptr->pcistatus); 72 return 0; 73 } 74 75 static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr) 76 { 77 int code = PCIBIOS_SUCCESSFUL; 78 79 /* wait write cycle completion before checking error status */ 80 while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB) 81 ; 82 if (__raw_readl(&pcicptr->pcistatus) 83 & (PCI_STATUS_REC_MASTER_ABORT << 16)) { 84 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) 85 | (PCI_STATUS_REC_MASTER_ABORT << 16), 86 &pcicptr->pcistatus); 87 /* flush write buffer */ 88 iob(); 89 code = PCIBIOS_DEVICE_NOT_FOUND; 90 } 91 return code; 92 } 93 94 static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr) 95 { 96 #ifdef __BIG_ENDIAN 97 offset ^= 3; 98 #endif 99 return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset); 100 } 101 static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr) 102 { 103 #ifdef __BIG_ENDIAN 104 offset ^= 2; 105 #endif 106 return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset); 107 } 108 static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr) 109 { 110 return __raw_readl(&pcicptr->g2pcfgdata); 111 } 112 static void icd_writeb(u8 val, int offset, 113 struct tx4927_pcic_reg __iomem *pcicptr) 114 { 115 #ifdef __BIG_ENDIAN 116 offset ^= 3; 117 #endif 118 __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); 119 } 120 static void icd_writew(u16 val, int offset, 121 struct tx4927_pcic_reg __iomem *pcicptr) 122 { 123 #ifdef __BIG_ENDIAN 124 offset ^= 2; 125 #endif 126 __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); 127 } 128 static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr) 129 { 130 __raw_writel(val, &pcicptr->g2pcfgdata); 131 } 132 133 static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus) 134 { 135 struct pci_controller *channel = bus->sysdata; 136 return get_tx4927_pcicptr(channel); 137 } 138 139 static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn, 140 int where, int size, u32 *val) 141 { 142 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); 143 144 if (mkaddr(bus, devfn, where, pcicptr)) { 145 *val = 0xffffffff; 146 return -1; 147 } 148 switch (size) { 149 case 1: 150 *val = icd_readb(where & 3, pcicptr); 151 break; 152 case 2: 153 *val = icd_readw(where & 3, pcicptr); 154 break; 155 default: 156 *val = icd_readl(pcicptr); 157 } 158 return check_abort(pcicptr); 159 } 160 161 static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn, 162 int where, int size, u32 val) 163 { 164 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); 165 166 if (mkaddr(bus, devfn, where, pcicptr)) 167 return -1; 168 switch (size) { 169 case 1: 170 icd_writeb(val, where & 3, pcicptr); 171 break; 172 case 2: 173 icd_writew(val, where & 3, pcicptr); 174 break; 175 default: 176 icd_writel(val, pcicptr); 177 } 178 return check_abort(pcicptr); 179 } 180 181 static struct pci_ops tx4927_pci_ops = { 182 .read = tx4927_pci_config_read, 183 .write = tx4927_pci_config_write, 184 }; 185 186 static struct { 187 u8 trdyto; 188 u8 retryto; 189 u16 gbwc; 190 } tx4927_pci_opts = { 191 .trdyto = 0, 192 .retryto = 0, 193 .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */ 194 }; 195 196 char *tx4927_pcibios_setup(char *str) 197 { 198 if (!strncmp(str, "trdyto=", 7)) { 199 u8 val = 0; 200 if (kstrtou8(str + 7, 0, &val) == 0) 201 tx4927_pci_opts.trdyto = val; 202 return NULL; 203 } 204 if (!strncmp(str, "retryto=", 8)) { 205 u8 val = 0; 206 if (kstrtou8(str + 8, 0, &val) == 0) 207 tx4927_pci_opts.retryto = val; 208 return NULL; 209 } 210 if (!strncmp(str, "gbwc=", 5)) { 211 u16 val; 212 if (kstrtou16(str + 5, 0, &val) == 0) 213 tx4927_pci_opts.gbwc = val; 214 return NULL; 215 } 216 return str; 217 } 218 219 void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, 220 struct pci_controller *channel, int extarb) 221 { 222 int i; 223 unsigned long flags; 224 225 set_tx4927_pcicptr(channel, pcicptr); 226 227 if (!channel->pci_ops) 228 printk(KERN_INFO 229 "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", 230 __raw_readl(&pcicptr->pciid) >> 16, 231 __raw_readl(&pcicptr->pciid) & 0xffff, 232 __raw_readl(&pcicptr->pciccrev) & 0xff, 233 extarb ? "External" : "Internal"); 234 channel->pci_ops = &tx4927_pci_ops; 235 236 local_irq_save(flags); 237 238 /* Disable All Initiator Space */ 239 __raw_writel(__raw_readl(&pcicptr->pciccfg) 240 & ~(TX4927_PCIC_PCICCFG_G2PMEN(0) 241 | TX4927_PCIC_PCICCFG_G2PMEN(1) 242 | TX4927_PCIC_PCICCFG_G2PMEN(2) 243 | TX4927_PCIC_PCICCFG_G2PIOEN), 244 &pcicptr->pciccfg); 245 246 /* GB->PCI mappings */ 247 __raw_writel((channel->io_resource->end - channel->io_resource->start) 248 >> 4, 249 &pcicptr->g2piomask); 250 ____raw_writeq((channel->io_resource->start + 251 channel->io_map_base - IO_BASE) | 252 #ifdef __BIG_ENDIAN 253 TX4927_PCIC_G2PIOGBASE_ECHG 254 #else 255 TX4927_PCIC_G2PIOGBASE_BSDIS 256 #endif 257 , &pcicptr->g2piogbase); 258 ____raw_writeq(channel->io_resource->start - channel->io_offset, 259 &pcicptr->g2piopbase); 260 for (i = 0; i < 3; i++) { 261 __raw_writel(0, &pcicptr->g2pmmask[i]); 262 ____raw_writeq(0, &pcicptr->g2pmgbase[i]); 263 ____raw_writeq(0, &pcicptr->g2pmpbase[i]); 264 } 265 if (channel->mem_resource->end) { 266 __raw_writel((channel->mem_resource->end 267 - channel->mem_resource->start) >> 4, 268 &pcicptr->g2pmmask[0]); 269 ____raw_writeq(channel->mem_resource->start | 270 #ifdef __BIG_ENDIAN 271 TX4927_PCIC_G2PMnGBASE_ECHG 272 #else 273 TX4927_PCIC_G2PMnGBASE_BSDIS 274 #endif 275 , &pcicptr->g2pmgbase[0]); 276 ____raw_writeq(channel->mem_resource->start - 277 channel->mem_offset, 278 &pcicptr->g2pmpbase[0]); 279 } 280 /* PCI->GB mappings (I/O 256B) */ 281 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ 282 ____raw_writeq(0, &pcicptr->p2giogbase); 283 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ 284 __raw_writel(0, &pcicptr->p2gm0plbase); 285 __raw_writel(0, &pcicptr->p2gm0pubase); 286 ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN | 287 #ifdef __BIG_ENDIAN 288 TX4927_PCIC_P2GMnGBASE_TECHG 289 #else 290 TX4927_PCIC_P2GMnGBASE_TBSDIS 291 #endif 292 , &pcicptr->p2gmgbase[0]); 293 /* PCI->GB mappings (MEM 16MB) */ 294 __raw_writel(0xffffffff, &pcicptr->p2gm1plbase); 295 __raw_writel(0xffffffff, &pcicptr->p2gm1pubase); 296 ____raw_writeq(0, &pcicptr->p2gmgbase[1]); 297 /* PCI->GB mappings (MEM 1MB) */ 298 __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */ 299 ____raw_writeq(0, &pcicptr->p2gmgbase[2]); 300 301 /* Clear all (including IRBER) except for GBWC */ 302 __raw_writel((tx4927_pci_opts.gbwc << 16) 303 & TX4927_PCIC_PCICCFG_GBWC_MASK, 304 &pcicptr->pciccfg); 305 /* Enable Initiator Memory Space */ 306 if (channel->mem_resource->end) 307 __raw_writel(__raw_readl(&pcicptr->pciccfg) 308 | TX4927_PCIC_PCICCFG_G2PMEN(0), 309 &pcicptr->pciccfg); 310 /* Enable Initiator I/O Space */ 311 if (channel->io_resource->end) 312 __raw_writel(__raw_readl(&pcicptr->pciccfg) 313 | TX4927_PCIC_PCICCFG_G2PIOEN, 314 &pcicptr->pciccfg); 315 /* Enable Initiator Config */ 316 __raw_writel(__raw_readl(&pcicptr->pciccfg) 317 | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR, 318 &pcicptr->pciccfg); 319 320 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ 321 __raw_writel(0, &pcicptr->pcicfg1); 322 323 __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff) 324 | (tx4927_pci_opts.trdyto & 0xff) 325 | ((tx4927_pci_opts.retryto & 0xff) << 8), 326 &pcicptr->g2ptocnt); 327 328 /* Clear All Local Bus Status */ 329 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus); 330 /* Enable All Local Bus Interrupts */ 331 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask); 332 /* Clear All Initiator Status */ 333 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus); 334 /* Enable All Initiator Interrupts */ 335 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask); 336 /* Clear All PCI Status Error */ 337 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) 338 | (TX4927_PCIC_PCISTATUS_ALL << 16), 339 &pcicptr->pcistatus); 340 /* Enable All PCI Status Error Interrupts */ 341 __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask); 342 343 if (!extarb) { 344 /* Reset Bus Arbiter */ 345 __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg); 346 __raw_writel(0, &pcicptr->pbabm); 347 /* Enable Bus Arbiter */ 348 __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg); 349 } 350 351 __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 352 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR, 353 &pcicptr->pcistatus); 354 local_irq_restore(flags); 355 356 printk(KERN_DEBUG 357 "PCI: COMMAND=%04x,PCIMASK=%04x," 358 "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n", 359 __raw_readl(&pcicptr->pcistatus) & 0xffff, 360 __raw_readl(&pcicptr->pcimask) & 0xffff, 361 __raw_readl(&pcicptr->g2ptocnt) & 0xff, 362 (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8, 363 (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff); 364 } 365 366 static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr) 367 { 368 __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16); 369 __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus); 370 __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus); 371 static struct { 372 __u32 flag; 373 const char *str; 374 } pcistat_tbl[] = { 375 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, 376 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, 377 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, 378 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, 379 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, 380 { PCI_STATUS_PARITY, "MasterParityError" }, 381 }, g2pstat_tbl[] = { 382 { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" }, 383 { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" }, 384 }, pcicstat_tbl[] = { 385 { TX4927_PCIC_PCICSTATUS_PME, "PME" }, 386 { TX4927_PCIC_PCICSTATUS_TLB, "TLB" }, 387 { TX4927_PCIC_PCICSTATUS_NIB, "NIB" }, 388 { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" }, 389 { TX4927_PCIC_PCICSTATUS_PERR, "PERR" }, 390 { TX4927_PCIC_PCICSTATUS_SERR, "SERR" }, 391 { TX4927_PCIC_PCICSTATUS_GBE, "GBE" }, 392 { TX4927_PCIC_PCICSTATUS_IWB, "IWB" }, 393 }; 394 int i, cont; 395 396 printk(KERN_ERR ""); 397 if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) { 398 printk(KERN_CONT "pcistat:%04x(", pcistatus); 399 for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++) 400 if (pcistatus & pcistat_tbl[i].flag) 401 printk(KERN_CONT "%s%s", 402 cont++ ? " " : "", pcistat_tbl[i].str); 403 printk(KERN_CONT ") "); 404 } 405 if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) { 406 printk(KERN_CONT "g2pstatus:%08x(", g2pstatus); 407 for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) 408 if (g2pstatus & g2pstat_tbl[i].flag) 409 printk(KERN_CONT "%s%s", 410 cont++ ? " " : "", g2pstat_tbl[i].str); 411 printk(KERN_CONT ") "); 412 } 413 if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) { 414 printk(KERN_CONT "pcicstatus:%08x(", pcicstatus); 415 for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) 416 if (pcicstatus & pcicstat_tbl[i].flag) 417 printk(KERN_CONT "%s%s", 418 cont++ ? " " : "", pcicstat_tbl[i].str); 419 printk(KERN_CONT ")"); 420 } 421 printk(KERN_CONT "\n"); 422 } 423 424 void tx4927_report_pcic_status(void) 425 { 426 int i; 427 428 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { 429 if (pcicptrs[i].pcicptr) 430 tx4927_report_pcic_status1(pcicptrs[i].pcicptr); 431 } 432 } 433 434 static void tx4927_dump_pcic_settings1(struct tx4927_pcic_reg __iomem *pcicptr) 435 { 436 int i; 437 __u32 __iomem *preg = (__u32 __iomem *)pcicptr; 438 439 printk(KERN_INFO "tx4927 pcic (0x%p) settings:", pcicptr); 440 for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4, preg++) { 441 if (i % 32 == 0) { 442 printk(KERN_CONT "\n"); 443 printk(KERN_INFO "%04x:", i); 444 } 445 /* skip registers with side-effects */ 446 if (i == offsetof(struct tx4927_pcic_reg, g2pintack) 447 || i == offsetof(struct tx4927_pcic_reg, g2pspc) 448 || i == offsetof(struct tx4927_pcic_reg, g2pcfgadrs) 449 || i == offsetof(struct tx4927_pcic_reg, g2pcfgdata)) { 450 printk(KERN_CONT " XXXXXXXX"); 451 continue; 452 } 453 printk(KERN_CONT " %08x", __raw_readl(preg)); 454 } 455 printk(KERN_CONT "\n"); 456 } 457 458 void tx4927_dump_pcic_settings(void) 459 { 460 int i; 461 462 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { 463 if (pcicptrs[i].pcicptr) 464 tx4927_dump_pcic_settings1(pcicptrs[i].pcicptr); 465 } 466 } 467 468 irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id) 469 { 470 struct pt_regs *regs = get_irq_regs(); 471 struct tx4927_pcic_reg __iomem *pcicptr = 472 (struct tx4927_pcic_reg __iomem *)(unsigned long)dev_id; 473 474 if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) { 475 printk(KERN_WARNING "PCIERR interrupt at 0x%0*lx\n", 476 (int)(2 * sizeof(unsigned long)), regs->cp0_epc); 477 tx4927_report_pcic_status1(pcicptr); 478 } 479 if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) { 480 /* clear all pci errors */ 481 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) 482 | (TX4927_PCIC_PCISTATUS_ALL << 16), 483 &pcicptr->pcistatus); 484 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus); 485 __raw_writel(TX4927_PCIC_PBASTATUS_ALL, &pcicptr->pbastatus); 486 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus); 487 return IRQ_HANDLED; 488 } 489 console_verbose(); 490 tx4927_dump_pcic_settings1(pcicptr); 491 panic("PCI error."); 492 } 493 494 #ifdef CONFIG_TOSHIBA_FPCIB0 495 static void tx4927_quirk_slc90e66_bridge(struct pci_dev *dev) 496 { 497 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus); 498 499 if (!pcicptr) 500 return; 501 if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) { 502 /* Reset Bus Arbiter */ 503 __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg); 504 /* 505 * swap reqBP and reqXP (raise priority of SLC90E66). 506 * SLC90E66(PCI-ISA bridge) is connected to REQ2 on 507 * PCI Backplane board. 508 */ 509 __raw_writel(0x72543610, &pcicptr->pbareqport); 510 __raw_writel(0, &pcicptr->pbabm); 511 /* Use Fixed ParkMaster (required by SLC90E66) */ 512 __raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg); 513 /* Enable Bus Arbiter */ 514 __raw_writel(TX4927_PCIC_PBACFG_FIXPA | 515 TX4927_PCIC_PBACFG_PBAEN, 516 &pcicptr->pbacfg); 517 printk(KERN_INFO "PCI: Use Fixed Park Master (REQPORT %08x)\n", 518 __raw_readl(&pcicptr->pbareqport)); 519 } 520 } 521 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 522 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0, 523 tx4927_quirk_slc90e66_bridge); 524 #endif 525