1 /* 2 * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc. 3 * 4 * Based on linux/arch/mips/pci/ops-tx4938.c, 5 * linux/arch/mips/pci/fixup-rbtx4938.c, 6 * linux/arch/mips/txx9/rbtx4938/setup.c, 7 * and RBTX49xx patch from CELF patch archive. 8 * 9 * 2003-2005 (c) MontaVista Software, Inc. 10 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 11 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 */ 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <asm/txx9/pci.h> 22 #include <asm/txx9/tx4927pcic.h> 23 24 static struct { 25 struct pci_controller *channel; 26 struct tx4927_pcic_reg __iomem *pcicptr; 27 } pcicptrs[2]; /* TX4938 has 2 pcic */ 28 29 static void __init set_tx4927_pcicptr(struct pci_controller *channel, 30 struct tx4927_pcic_reg __iomem *pcicptr) 31 { 32 int i; 33 34 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { 35 if (pcicptrs[i].channel == channel) { 36 pcicptrs[i].pcicptr = pcicptr; 37 return; 38 } 39 } 40 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { 41 if (!pcicptrs[i].channel) { 42 pcicptrs[i].channel = channel; 43 pcicptrs[i].pcicptr = pcicptr; 44 return; 45 } 46 } 47 BUG(); 48 } 49 50 struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( 51 struct pci_controller *channel) 52 { 53 int i; 54 55 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { 56 if (pcicptrs[i].channel == channel) 57 return pcicptrs[i].pcicptr; 58 } 59 return NULL; 60 } 61 62 static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where, 63 struct tx4927_pcic_reg __iomem *pcicptr) 64 { 65 if (bus->parent == NULL && 66 devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0)) 67 return -1; 68 __raw_writel(((bus->number & 0xff) << 0x10) 69 | ((devfn & 0xff) << 0x08) | (where & 0xfc) 70 | (bus->parent ? 1 : 0), 71 &pcicptr->g2pcfgadrs); 72 /* clear M_ABORT and Disable M_ABORT Int. */ 73 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) 74 | (PCI_STATUS_REC_MASTER_ABORT << 16), 75 &pcicptr->pcistatus); 76 return 0; 77 } 78 79 static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr) 80 { 81 int code = PCIBIOS_SUCCESSFUL; 82 83 /* wait write cycle completion before checking error status */ 84 while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB) 85 ; 86 if (__raw_readl(&pcicptr->pcistatus) 87 & (PCI_STATUS_REC_MASTER_ABORT << 16)) { 88 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) 89 | (PCI_STATUS_REC_MASTER_ABORT << 16), 90 &pcicptr->pcistatus); 91 /* flush write buffer */ 92 iob(); 93 code = PCIBIOS_DEVICE_NOT_FOUND; 94 } 95 return code; 96 } 97 98 static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr) 99 { 100 #ifdef __BIG_ENDIAN 101 offset ^= 3; 102 #endif 103 return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset); 104 } 105 static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr) 106 { 107 #ifdef __BIG_ENDIAN 108 offset ^= 2; 109 #endif 110 return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset); 111 } 112 static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr) 113 { 114 return __raw_readl(&pcicptr->g2pcfgdata); 115 } 116 static void icd_writeb(u8 val, int offset, 117 struct tx4927_pcic_reg __iomem *pcicptr) 118 { 119 #ifdef __BIG_ENDIAN 120 offset ^= 3; 121 #endif 122 __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); 123 } 124 static void icd_writew(u16 val, int offset, 125 struct tx4927_pcic_reg __iomem *pcicptr) 126 { 127 #ifdef __BIG_ENDIAN 128 offset ^= 2; 129 #endif 130 __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); 131 } 132 static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr) 133 { 134 __raw_writel(val, &pcicptr->g2pcfgdata); 135 } 136 137 static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus) 138 { 139 struct pci_controller *channel = bus->sysdata; 140 return get_tx4927_pcicptr(channel); 141 } 142 143 static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn, 144 int where, int size, u32 *val) 145 { 146 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); 147 148 if (mkaddr(bus, devfn, where, pcicptr)) { 149 *val = 0xffffffff; 150 return -1; 151 } 152 switch (size) { 153 case 1: 154 *val = icd_readb(where & 3, pcicptr); 155 break; 156 case 2: 157 *val = icd_readw(where & 3, pcicptr); 158 break; 159 default: 160 *val = icd_readl(pcicptr); 161 } 162 return check_abort(pcicptr); 163 } 164 165 static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn, 166 int where, int size, u32 val) 167 { 168 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); 169 170 if (mkaddr(bus, devfn, where, pcicptr)) 171 return -1; 172 switch (size) { 173 case 1: 174 icd_writeb(val, where & 3, pcicptr); 175 break; 176 case 2: 177 icd_writew(val, where & 3, pcicptr); 178 break; 179 default: 180 icd_writel(val, pcicptr); 181 } 182 return check_abort(pcicptr); 183 } 184 185 static struct pci_ops tx4927_pci_ops = { 186 .read = tx4927_pci_config_read, 187 .write = tx4927_pci_config_write, 188 }; 189 190 static struct { 191 u8 trdyto; 192 u8 retryto; 193 u16 gbwc; 194 } tx4927_pci_opts = { 195 .trdyto = 0, 196 .retryto = 0, 197 .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */ 198 }; 199 200 char *tx4927_pcibios_setup(char *str) 201 { 202 unsigned long val; 203 204 if (!strncmp(str, "trdyto=", 7)) { 205 u8 val = 0; 206 if (kstrtou8(str + 7, 0, &val) == 0) 207 tx4927_pci_opts.trdyto = val; 208 return NULL; 209 } 210 if (!strncmp(str, "retryto=", 8)) { 211 u8 val = 0; 212 if (kstrtou8(str + 8, 0, &val) == 0) 213 tx4927_pci_opts.retryto = val; 214 return NULL; 215 } 216 if (!strncmp(str, "gbwc=", 5)) { 217 u16 val; 218 if (kstrtou16(str + 5, 0, &val) == 0) 219 tx4927_pci_opts.gbwc = val; 220 return NULL; 221 } 222 return str; 223 } 224 225 void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, 226 struct pci_controller *channel, int extarb) 227 { 228 int i; 229 unsigned long flags; 230 231 set_tx4927_pcicptr(channel, pcicptr); 232 233 if (!channel->pci_ops) 234 printk(KERN_INFO 235 "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", 236 __raw_readl(&pcicptr->pciid) >> 16, 237 __raw_readl(&pcicptr->pciid) & 0xffff, 238 __raw_readl(&pcicptr->pciccrev) & 0xff, 239 extarb ? "External" : "Internal"); 240 channel->pci_ops = &tx4927_pci_ops; 241 242 local_irq_save(flags); 243 244 /* Disable All Initiator Space */ 245 __raw_writel(__raw_readl(&pcicptr->pciccfg) 246 & ~(TX4927_PCIC_PCICCFG_G2PMEN(0) 247 | TX4927_PCIC_PCICCFG_G2PMEN(1) 248 | TX4927_PCIC_PCICCFG_G2PMEN(2) 249 | TX4927_PCIC_PCICCFG_G2PIOEN), 250 &pcicptr->pciccfg); 251 252 /* GB->PCI mappings */ 253 __raw_writel((channel->io_resource->end - channel->io_resource->start) 254 >> 4, 255 &pcicptr->g2piomask); 256 ____raw_writeq((channel->io_resource->start + 257 channel->io_map_base - IO_BASE) | 258 #ifdef __BIG_ENDIAN 259 TX4927_PCIC_G2PIOGBASE_ECHG 260 #else 261 TX4927_PCIC_G2PIOGBASE_BSDIS 262 #endif 263 , &pcicptr->g2piogbase); 264 ____raw_writeq(channel->io_resource->start - channel->io_offset, 265 &pcicptr->g2piopbase); 266 for (i = 0; i < 3; i++) { 267 __raw_writel(0, &pcicptr->g2pmmask[i]); 268 ____raw_writeq(0, &pcicptr->g2pmgbase[i]); 269 ____raw_writeq(0, &pcicptr->g2pmpbase[i]); 270 } 271 if (channel->mem_resource->end) { 272 __raw_writel((channel->mem_resource->end 273 - channel->mem_resource->start) >> 4, 274 &pcicptr->g2pmmask[0]); 275 ____raw_writeq(channel->mem_resource->start | 276 #ifdef __BIG_ENDIAN 277 TX4927_PCIC_G2PMnGBASE_ECHG 278 #else 279 TX4927_PCIC_G2PMnGBASE_BSDIS 280 #endif 281 , &pcicptr->g2pmgbase[0]); 282 ____raw_writeq(channel->mem_resource->start - 283 channel->mem_offset, 284 &pcicptr->g2pmpbase[0]); 285 } 286 /* PCI->GB mappings (I/O 256B) */ 287 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ 288 ____raw_writeq(0, &pcicptr->p2giogbase); 289 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ 290 __raw_writel(0, &pcicptr->p2gm0plbase); 291 __raw_writel(0, &pcicptr->p2gm0pubase); 292 ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN | 293 #ifdef __BIG_ENDIAN 294 TX4927_PCIC_P2GMnGBASE_TECHG 295 #else 296 TX4927_PCIC_P2GMnGBASE_TBSDIS 297 #endif 298 , &pcicptr->p2gmgbase[0]); 299 /* PCI->GB mappings (MEM 16MB) */ 300 __raw_writel(0xffffffff, &pcicptr->p2gm1plbase); 301 __raw_writel(0xffffffff, &pcicptr->p2gm1pubase); 302 ____raw_writeq(0, &pcicptr->p2gmgbase[1]); 303 /* PCI->GB mappings (MEM 1MB) */ 304 __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */ 305 ____raw_writeq(0, &pcicptr->p2gmgbase[2]); 306 307 /* Clear all (including IRBER) except for GBWC */ 308 __raw_writel((tx4927_pci_opts.gbwc << 16) 309 & TX4927_PCIC_PCICCFG_GBWC_MASK, 310 &pcicptr->pciccfg); 311 /* Enable Initiator Memory Space */ 312 if (channel->mem_resource->end) 313 __raw_writel(__raw_readl(&pcicptr->pciccfg) 314 | TX4927_PCIC_PCICCFG_G2PMEN(0), 315 &pcicptr->pciccfg); 316 /* Enable Initiator I/O Space */ 317 if (channel->io_resource->end) 318 __raw_writel(__raw_readl(&pcicptr->pciccfg) 319 | TX4927_PCIC_PCICCFG_G2PIOEN, 320 &pcicptr->pciccfg); 321 /* Enable Initiator Config */ 322 __raw_writel(__raw_readl(&pcicptr->pciccfg) 323 | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR, 324 &pcicptr->pciccfg); 325 326 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ 327 __raw_writel(0, &pcicptr->pcicfg1); 328 329 __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff) 330 | (tx4927_pci_opts.trdyto & 0xff) 331 | ((tx4927_pci_opts.retryto & 0xff) << 8), 332 &pcicptr->g2ptocnt); 333 334 /* Clear All Local Bus Status */ 335 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus); 336 /* Enable All Local Bus Interrupts */ 337 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask); 338 /* Clear All Initiator Status */ 339 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus); 340 /* Enable All Initiator Interrupts */ 341 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask); 342 /* Clear All PCI Status Error */ 343 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) 344 | (TX4927_PCIC_PCISTATUS_ALL << 16), 345 &pcicptr->pcistatus); 346 /* Enable All PCI Status Error Interrupts */ 347 __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask); 348 349 if (!extarb) { 350 /* Reset Bus Arbiter */ 351 __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg); 352 __raw_writel(0, &pcicptr->pbabm); 353 /* Enable Bus Arbiter */ 354 __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg); 355 } 356 357 __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 358 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR, 359 &pcicptr->pcistatus); 360 local_irq_restore(flags); 361 362 printk(KERN_DEBUG 363 "PCI: COMMAND=%04x,PCIMASK=%04x," 364 "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n", 365 __raw_readl(&pcicptr->pcistatus) & 0xffff, 366 __raw_readl(&pcicptr->pcimask) & 0xffff, 367 __raw_readl(&pcicptr->g2ptocnt) & 0xff, 368 (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8, 369 (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff); 370 } 371 372 static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr) 373 { 374 __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16); 375 __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus); 376 __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus); 377 static struct { 378 __u32 flag; 379 const char *str; 380 } pcistat_tbl[] = { 381 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, 382 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, 383 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, 384 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, 385 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, 386 { PCI_STATUS_PARITY, "MasterParityError" }, 387 }, g2pstat_tbl[] = { 388 { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" }, 389 { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" }, 390 }, pcicstat_tbl[] = { 391 { TX4927_PCIC_PCICSTATUS_PME, "PME" }, 392 { TX4927_PCIC_PCICSTATUS_TLB, "TLB" }, 393 { TX4927_PCIC_PCICSTATUS_NIB, "NIB" }, 394 { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" }, 395 { TX4927_PCIC_PCICSTATUS_PERR, "PERR" }, 396 { TX4927_PCIC_PCICSTATUS_SERR, "SERR" }, 397 { TX4927_PCIC_PCICSTATUS_GBE, "GBE" }, 398 { TX4927_PCIC_PCICSTATUS_IWB, "IWB" }, 399 }; 400 int i, cont; 401 402 printk(KERN_ERR ""); 403 if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) { 404 printk(KERN_CONT "pcistat:%04x(", pcistatus); 405 for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++) 406 if (pcistatus & pcistat_tbl[i].flag) 407 printk(KERN_CONT "%s%s", 408 cont++ ? " " : "", pcistat_tbl[i].str); 409 printk(KERN_CONT ") "); 410 } 411 if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) { 412 printk(KERN_CONT "g2pstatus:%08x(", g2pstatus); 413 for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) 414 if (g2pstatus & g2pstat_tbl[i].flag) 415 printk(KERN_CONT "%s%s", 416 cont++ ? " " : "", g2pstat_tbl[i].str); 417 printk(KERN_CONT ") "); 418 } 419 if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) { 420 printk(KERN_CONT "pcicstatus:%08x(", pcicstatus); 421 for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) 422 if (pcicstatus & pcicstat_tbl[i].flag) 423 printk(KERN_CONT "%s%s", 424 cont++ ? " " : "", pcicstat_tbl[i].str); 425 printk(KERN_CONT ")"); 426 } 427 printk(KERN_CONT "\n"); 428 } 429 430 void tx4927_report_pcic_status(void) 431 { 432 int i; 433 434 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { 435 if (pcicptrs[i].pcicptr) 436 tx4927_report_pcic_status1(pcicptrs[i].pcicptr); 437 } 438 } 439 440 static void tx4927_dump_pcic_settings1(struct tx4927_pcic_reg __iomem *pcicptr) 441 { 442 int i; 443 __u32 __iomem *preg = (__u32 __iomem *)pcicptr; 444 445 printk(KERN_INFO "tx4927 pcic (0x%p) settings:", pcicptr); 446 for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4, preg++) { 447 if (i % 32 == 0) { 448 printk(KERN_CONT "\n"); 449 printk(KERN_INFO "%04x:", i); 450 } 451 /* skip registers with side-effects */ 452 if (i == offsetof(struct tx4927_pcic_reg, g2pintack) 453 || i == offsetof(struct tx4927_pcic_reg, g2pspc) 454 || i == offsetof(struct tx4927_pcic_reg, g2pcfgadrs) 455 || i == offsetof(struct tx4927_pcic_reg, g2pcfgdata)) { 456 printk(KERN_CONT " XXXXXXXX"); 457 continue; 458 } 459 printk(KERN_CONT " %08x", __raw_readl(preg)); 460 } 461 printk(KERN_CONT "\n"); 462 } 463 464 void tx4927_dump_pcic_settings(void) 465 { 466 int i; 467 468 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { 469 if (pcicptrs[i].pcicptr) 470 tx4927_dump_pcic_settings1(pcicptrs[i].pcicptr); 471 } 472 } 473 474 irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id) 475 { 476 struct pt_regs *regs = get_irq_regs(); 477 struct tx4927_pcic_reg __iomem *pcicptr = 478 (struct tx4927_pcic_reg __iomem *)(unsigned long)dev_id; 479 480 if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) { 481 printk(KERN_WARNING "PCIERR interrupt at 0x%0*lx\n", 482 (int)(2 * sizeof(unsigned long)), regs->cp0_epc); 483 tx4927_report_pcic_status1(pcicptr); 484 } 485 if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) { 486 /* clear all pci errors */ 487 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) 488 | (TX4927_PCIC_PCISTATUS_ALL << 16), 489 &pcicptr->pcistatus); 490 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus); 491 __raw_writel(TX4927_PCIC_PBASTATUS_ALL, &pcicptr->pbastatus); 492 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus); 493 return IRQ_HANDLED; 494 } 495 console_verbose(); 496 tx4927_dump_pcic_settings1(pcicptr); 497 panic("PCI error."); 498 } 499 500 #ifdef CONFIG_TOSHIBA_FPCIB0 501 static void tx4927_quirk_slc90e66_bridge(struct pci_dev *dev) 502 { 503 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus); 504 505 if (!pcicptr) 506 return; 507 if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) { 508 /* Reset Bus Arbiter */ 509 __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg); 510 /* 511 * swap reqBP and reqXP (raise priority of SLC90E66). 512 * SLC90E66(PCI-ISA bridge) is connected to REQ2 on 513 * PCI Backplane board. 514 */ 515 __raw_writel(0x72543610, &pcicptr->pbareqport); 516 __raw_writel(0, &pcicptr->pbabm); 517 /* Use Fixed ParkMaster (required by SLC90E66) */ 518 __raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg); 519 /* Enable Bus Arbiter */ 520 __raw_writel(TX4927_PCIC_PBACFG_FIXPA | 521 TX4927_PCIC_PBACFG_PBAEN, 522 &pcicptr->pbacfg); 523 printk(KERN_INFO "PCI: Use Fixed Park Master (REQPORT %08x)\n", 524 __raw_readl(&pcicptr->pbareqport)); 525 } 526 } 527 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 528 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0, 529 tx4927_quirk_slc90e66_bridge); 530 #endif 531