1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2000, 2001 Keith M Wesolowski 7 */ 8 #include <linux/kernel.h> 9 #include <linux/pci.h> 10 #include <linux/types.h> 11 #include <asm/pci.h> 12 #include <asm/ip32/mace.h> 13 14 #if 0 15 # define DPRINTK(args...) printk(args); 16 #else 17 # define DPRINTK(args...) 18 #endif 19 20 /* 21 * O2 has up to 5 PCI devices connected into the MACE bridge. The device 22 * map looks like this: 23 * 24 * 0 aic7xxx 0 25 * 1 aic7xxx 1 26 * 2 expansion slot 27 * 3 N/C 28 * 4 N/C 29 */ 30 31 static inline int mkaddr(struct pci_bus *bus, unsigned int devfn, 32 unsigned int reg) 33 { 34 return ((bus->number & 0xff) << 16) | 35 ((devfn & 0xff) << 8) | 36 (reg & 0xfc); 37 } 38 39 40 static int 41 mace_pci_read_config(struct pci_bus *bus, unsigned int devfn, 42 int reg, int size, u32 *val) 43 { 44 u32 control = mace->pci.control; 45 46 /* disable master aborts interrupts during config read */ 47 mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT; 48 mace->pci.config_addr = mkaddr(bus, devfn, reg); 49 switch (size) { 50 case 1: 51 *val = mace->pci.config_data.b[(reg & 3) ^ 3]; 52 break; 53 case 2: 54 *val = mace->pci.config_data.w[((reg >> 1) & 1) ^ 1]; 55 break; 56 case 4: 57 *val = mace->pci.config_data.l; 58 break; 59 } 60 /* ack possible master abort */ 61 mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT; 62 mace->pci.control = control; 63 /* 64 * someone forgot to set the ultra bit for the onboard 65 * scsi chips; we fake it here 66 */ 67 if (bus->number == 0 && reg == 0x40 && size == 4 && 68 (devfn == (1 << 3) || devfn == (2 << 3))) 69 *val |= 0x1000; 70 71 DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val); 72 73 return PCIBIOS_SUCCESSFUL; 74 } 75 76 static int 77 mace_pci_write_config(struct pci_bus *bus, unsigned int devfn, 78 int reg, int size, u32 val) 79 { 80 mace->pci.config_addr = mkaddr(bus, devfn, reg); 81 switch (size) { 82 case 1: 83 mace->pci.config_data.b[(reg & 3) ^ 3] = val; 84 break; 85 case 2: 86 mace->pci.config_data.w[((reg >> 1) & 1) ^ 1] = val; 87 break; 88 case 4: 89 mace->pci.config_data.l = val; 90 break; 91 } 92 93 DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val); 94 95 return PCIBIOS_SUCCESSFUL; 96 } 97 98 struct pci_ops mace_pci_ops = { 99 .read = mace_pci_read_config, 100 .write = mace_pci_write_config, 101 }; 102