1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2005-2009, 2010 Cavium Networks 7 */ 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/msi.h> 11 #include <linux/spinlock.h> 12 #include <linux/interrupt.h> 13 14 #include <asm/octeon/octeon.h> 15 #include <asm/octeon/cvmx-npi-defs.h> 16 #include <asm/octeon/cvmx-pci-defs.h> 17 #include <asm/octeon/cvmx-npei-defs.h> 18 #include <asm/octeon/cvmx-sli-defs.h> 19 #include <asm/octeon/cvmx-pexp-defs.h> 20 #include <asm/octeon/pci-octeon.h> 21 22 /* 23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is 24 * in use. 25 */ 26 static u64 msi_free_irq_bitmask[4]; 27 28 /* 29 * Each bit in msi_multiple_irq_bitmask tells that the device using 30 * this bit in msi_free_irq_bitmask is also using the next bit. This 31 * is used so we can disable all of the MSI interrupts when a device 32 * uses multiple. 33 */ 34 static u64 msi_multiple_irq_bitmask[4]; 35 36 /* 37 * This lock controls updates to msi_free_irq_bitmask and 38 * msi_multiple_irq_bitmask. 39 */ 40 static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock); 41 42 /* 43 * Number of MSI IRQs used. This variable is set up in 44 * the module init time. 45 */ 46 static int msi_irq_size; 47 48 /** 49 * Called when a driver request MSI interrupts instead of the 50 * legacy INT A-D. This routine will allocate multiple interrupts 51 * for MSI devices that support them. A device can override this by 52 * programming the MSI control bits [6:4] before calling 53 * pci_enable_msi(). 54 * 55 * @dev: Device requesting MSI interrupts 56 * @desc: MSI descriptor 57 * 58 * Returns 0 on success. 59 */ 60 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) 61 { 62 struct msi_msg msg; 63 u16 control; 64 int configured_private_bits; 65 int request_private_bits; 66 int irq = 0; 67 int irq_step; 68 u64 search_mask; 69 int index; 70 71 if (desc->pci.msi_attrib.is_msix) 72 return -EINVAL; 73 74 /* 75 * Read the MSI config to figure out how many IRQs this device 76 * wants. Most devices only want 1, which will give 77 * configured_private_bits and request_private_bits equal 0. 78 */ 79 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 80 81 /* 82 * If the number of private bits has been configured then use 83 * that value instead of the requested number. This gives the 84 * driver the chance to override the number of interrupts 85 * before calling pci_enable_msi(). 86 */ 87 configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; 88 if (configured_private_bits == 0) { 89 /* Nothing is configured, so use the hardware requested size */ 90 request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; 91 } else { 92 /* 93 * Use the number of configured bits, assuming the 94 * driver wanted to override the hardware request 95 * value. 96 */ 97 request_private_bits = configured_private_bits; 98 } 99 100 /* 101 * The PCI 2.3 spec mandates that there are at most 32 102 * interrupts. If this device asks for more, only give it one. 103 */ 104 if (request_private_bits > 5) 105 request_private_bits = 0; 106 107 try_only_one: 108 /* 109 * The IRQs have to be aligned on a power of two based on the 110 * number being requested. 111 */ 112 irq_step = 1 << request_private_bits; 113 114 /* Mask with one bit for each IRQ */ 115 search_mask = (1 << irq_step) - 1; 116 117 /* 118 * We're going to search msi_free_irq_bitmask_lock for zero 119 * bits. This represents an MSI interrupt number that isn't in 120 * use. 121 */ 122 spin_lock(&msi_free_irq_bitmask_lock); 123 for (index = 0; index < msi_irq_size/64; index++) { 124 for (irq = 0; irq < 64; irq += irq_step) { 125 if ((msi_free_irq_bitmask[index] & (search_mask << irq)) == 0) { 126 msi_free_irq_bitmask[index] |= search_mask << irq; 127 msi_multiple_irq_bitmask[index] |= (search_mask >> 1) << irq; 128 goto msi_irq_allocated; 129 } 130 } 131 } 132 msi_irq_allocated: 133 spin_unlock(&msi_free_irq_bitmask_lock); 134 135 /* Make sure the search for available interrupts didn't fail */ 136 if (irq >= 64) { 137 if (request_private_bits) { 138 pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one", 139 1 << request_private_bits); 140 request_private_bits = 0; 141 goto try_only_one; 142 } else 143 panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); 144 } 145 146 /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */ 147 irq += index*64; 148 irq += OCTEON_IRQ_MSI_BIT0; 149 150 switch (octeon_dma_bar_type) { 151 case OCTEON_DMA_BAR_TYPE_SMALL: 152 /* When not using big bar, Bar 0 is based at 128MB */ 153 msg.address_lo = 154 ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff; 155 msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32; 156 break; 157 case OCTEON_DMA_BAR_TYPE_BIG: 158 /* When using big bar, Bar 0 is based at 0 */ 159 msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff; 160 msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32; 161 break; 162 case OCTEON_DMA_BAR_TYPE_PCIE: 163 /* When using PCIe, Bar 0 is based at 0 */ 164 /* FIXME CVMX_NPEI_MSI_RCV* other than 0? */ 165 msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff; 166 msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32; 167 break; 168 case OCTEON_DMA_BAR_TYPE_PCIE2: 169 /* When using PCIe2, Bar 0 is based at 0 */ 170 msg.address_lo = (0 + CVMX_SLI_PCIE_MSI_RCV) & 0xffffffff; 171 msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32; 172 break; 173 default: 174 panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type"); 175 } 176 msg.data = irq - OCTEON_IRQ_MSI_BIT0; 177 178 /* Update the number of IRQs the device has available to it */ 179 control &= ~PCI_MSI_FLAGS_QSIZE; 180 control |= request_private_bits << 4; 181 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 182 183 irq_set_msi_desc(irq, desc); 184 pci_write_msi_msg(irq, &msg); 185 return 0; 186 } 187 188 /** 189 * Called when a device no longer needs its MSI interrupts. All 190 * MSI interrupts for the device are freed. 191 * 192 * @irq: The devices first irq number. There may be multple in sequence. 193 */ 194 void arch_teardown_msi_irq(unsigned int irq) 195 { 196 int number_irqs; 197 u64 bitmask; 198 int index = 0; 199 int irq0; 200 201 if ((irq < OCTEON_IRQ_MSI_BIT0) 202 || (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0)) 203 panic("arch_teardown_msi_irq: Attempted to teardown illegal " 204 "MSI interrupt (%d)", irq); 205 206 irq -= OCTEON_IRQ_MSI_BIT0; 207 index = irq / 64; 208 irq0 = irq % 64; 209 210 /* 211 * Count the number of IRQs we need to free by looking at the 212 * msi_multiple_irq_bitmask. Each bit set means that the next 213 * IRQ is also owned by this device. 214 */ 215 number_irqs = 0; 216 while ((irq0 + number_irqs < 64) && 217 (msi_multiple_irq_bitmask[index] 218 & (1ull << (irq0 + number_irqs)))) 219 number_irqs++; 220 number_irqs++; 221 /* Mask with one bit for each IRQ */ 222 bitmask = (1 << number_irqs) - 1; 223 /* Shift the mask to the correct bit location */ 224 bitmask <<= irq0; 225 if ((msi_free_irq_bitmask[index] & bitmask) != bitmask) 226 panic("arch_teardown_msi_irq: Attempted to teardown MSI " 227 "interrupt (%d) not in use", irq); 228 229 /* Checks are done, update the in use bitmask */ 230 spin_lock(&msi_free_irq_bitmask_lock); 231 msi_free_irq_bitmask[index] &= ~bitmask; 232 msi_multiple_irq_bitmask[index] &= ~bitmask; 233 spin_unlock(&msi_free_irq_bitmask_lock); 234 } 235 236 static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); 237 238 static u64 msi_rcv_reg[4]; 239 static u64 mis_ena_reg[4]; 240 241 static void octeon_irq_msi_enable_pcie(struct irq_data *data) 242 { 243 u64 en; 244 unsigned long flags; 245 int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0; 246 int irq_index = msi_number >> 6; 247 int irq_bit = msi_number & 0x3f; 248 249 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags); 250 en = cvmx_read_csr(mis_ena_reg[irq_index]); 251 en |= 1ull << irq_bit; 252 cvmx_write_csr(mis_ena_reg[irq_index], en); 253 cvmx_read_csr(mis_ena_reg[irq_index]); 254 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); 255 } 256 257 static void octeon_irq_msi_disable_pcie(struct irq_data *data) 258 { 259 u64 en; 260 unsigned long flags; 261 int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0; 262 int irq_index = msi_number >> 6; 263 int irq_bit = msi_number & 0x3f; 264 265 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags); 266 en = cvmx_read_csr(mis_ena_reg[irq_index]); 267 en &= ~(1ull << irq_bit); 268 cvmx_write_csr(mis_ena_reg[irq_index], en); 269 cvmx_read_csr(mis_ena_reg[irq_index]); 270 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); 271 } 272 273 static struct irq_chip octeon_irq_chip_msi_pcie = { 274 .name = "MSI", 275 .irq_enable = octeon_irq_msi_enable_pcie, 276 .irq_disable = octeon_irq_msi_disable_pcie, 277 }; 278 279 static void octeon_irq_msi_enable_pci(struct irq_data *data) 280 { 281 /* 282 * Octeon PCI doesn't have the ability to mask/unmask MSI 283 * interrupts individually. Instead of masking/unmasking them 284 * in groups of 16, we simple assume MSI devices are well 285 * behaved. MSI interrupts are always enable and the ACK is 286 * assumed to be enough 287 */ 288 } 289 290 static void octeon_irq_msi_disable_pci(struct irq_data *data) 291 { 292 /* See comment in enable */ 293 } 294 295 static struct irq_chip octeon_irq_chip_msi_pci = { 296 .name = "MSI", 297 .irq_enable = octeon_irq_msi_enable_pci, 298 .irq_disable = octeon_irq_msi_disable_pci, 299 }; 300 301 /* 302 * Called by the interrupt handling code when an MSI interrupt 303 * occurs. 304 */ 305 static irqreturn_t __octeon_msi_do_interrupt(int index, u64 msi_bits) 306 { 307 int irq; 308 int bit; 309 310 bit = fls64(msi_bits); 311 if (bit) { 312 bit--; 313 /* Acknowledge it first. */ 314 cvmx_write_csr(msi_rcv_reg[index], 1ull << bit); 315 316 irq = bit + OCTEON_IRQ_MSI_BIT0 + 64 * index; 317 do_IRQ(irq); 318 return IRQ_HANDLED; 319 } 320 return IRQ_NONE; 321 } 322 323 #define OCTEON_MSI_INT_HANDLER_X(x) \ 324 static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id) \ 325 { \ 326 u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \ 327 return __octeon_msi_do_interrupt((x), msi_bits); \ 328 } 329 330 /* 331 * Create octeon_msi_interrupt{0-3} function body 332 */ 333 OCTEON_MSI_INT_HANDLER_X(0); 334 OCTEON_MSI_INT_HANDLER_X(1); 335 OCTEON_MSI_INT_HANDLER_X(2); 336 OCTEON_MSI_INT_HANDLER_X(3); 337 338 /* 339 * Initializes the MSI interrupt handling code 340 */ 341 int __init octeon_msi_initialize(void) 342 { 343 int irq; 344 struct irq_chip *msi; 345 346 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_INVALID) { 347 return 0; 348 } else if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) { 349 msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0; 350 msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1; 351 msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2; 352 msi_rcv_reg[3] = CVMX_PEXP_NPEI_MSI_RCV3; 353 mis_ena_reg[0] = CVMX_PEXP_NPEI_MSI_ENB0; 354 mis_ena_reg[1] = CVMX_PEXP_NPEI_MSI_ENB1; 355 mis_ena_reg[2] = CVMX_PEXP_NPEI_MSI_ENB2; 356 mis_ena_reg[3] = CVMX_PEXP_NPEI_MSI_ENB3; 357 msi = &octeon_irq_chip_msi_pcie; 358 } else { 359 msi_rcv_reg[0] = CVMX_NPI_NPI_MSI_RCV; 360 #define INVALID_GENERATE_ADE 0x8700000000000000ULL; 361 msi_rcv_reg[1] = INVALID_GENERATE_ADE; 362 msi_rcv_reg[2] = INVALID_GENERATE_ADE; 363 msi_rcv_reg[3] = INVALID_GENERATE_ADE; 364 mis_ena_reg[0] = INVALID_GENERATE_ADE; 365 mis_ena_reg[1] = INVALID_GENERATE_ADE; 366 mis_ena_reg[2] = INVALID_GENERATE_ADE; 367 mis_ena_reg[3] = INVALID_GENERATE_ADE; 368 msi = &octeon_irq_chip_msi_pci; 369 } 370 371 for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) 372 irq_set_chip_and_handler(irq, msi, handle_simple_irq); 373 374 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { 375 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0, 376 0, "MSI[0:63]", octeon_msi_interrupt0)) 377 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); 378 379 if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt1, 380 0, "MSI[64:127]", octeon_msi_interrupt1)) 381 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed"); 382 383 if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt2, 384 0, "MSI[127:191]", octeon_msi_interrupt2)) 385 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed"); 386 387 if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt3, 388 0, "MSI[192:255]", octeon_msi_interrupt3)) 389 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed"); 390 391 msi_irq_size = 256; 392 } else if (octeon_is_pci_host()) { 393 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0, 394 0, "MSI[0:15]", octeon_msi_interrupt0)) 395 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); 396 397 if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt0, 398 0, "MSI[16:31]", octeon_msi_interrupt0)) 399 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed"); 400 401 if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt0, 402 0, "MSI[32:47]", octeon_msi_interrupt0)) 403 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed"); 404 405 if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt0, 406 0, "MSI[48:63]", octeon_msi_interrupt0)) 407 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed"); 408 msi_irq_size = 64; 409 } 410 return 0; 411 } 412 subsys_initcall(octeon_msi_initialize); 413