101a6221aSDavid Daney /*
201a6221aSDavid Daney * This file is subject to the terms and conditions of the GNU General Public
301a6221aSDavid Daney * License. See the file "COPYING" in the main directory of this archive
401a6221aSDavid Daney * for more details.
501a6221aSDavid Daney *
61aa2b278SDavid Daney * Copyright (C) 2005-2009, 2010 Cavium Networks
701a6221aSDavid Daney */
801a6221aSDavid Daney #include <linux/kernel.h>
901a6221aSDavid Daney #include <linux/init.h>
1001a6221aSDavid Daney #include <linux/msi.h>
1101a6221aSDavid Daney #include <linux/spinlock.h>
1201a6221aSDavid Daney #include <linux/interrupt.h>
1301a6221aSDavid Daney
1401a6221aSDavid Daney #include <asm/octeon/octeon.h>
1501a6221aSDavid Daney #include <asm/octeon/cvmx-npi-defs.h>
1601a6221aSDavid Daney #include <asm/octeon/cvmx-pci-defs.h>
1701a6221aSDavid Daney #include <asm/octeon/cvmx-npei-defs.h>
18d19648d7SEunbong Song #include <asm/octeon/cvmx-sli-defs.h>
1901a6221aSDavid Daney #include <asm/octeon/cvmx-pexp-defs.h>
2001a6221aSDavid Daney #include <asm/octeon/pci-octeon.h>
2101a6221aSDavid Daney
2201a6221aSDavid Daney /*
2301a6221aSDavid Daney * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
2401a6221aSDavid Daney * in use.
2501a6221aSDavid Daney */
261aa2b278SDavid Daney static u64 msi_free_irq_bitmask[4];
2701a6221aSDavid Daney
2801a6221aSDavid Daney /*
2901a6221aSDavid Daney * Each bit in msi_multiple_irq_bitmask tells that the device using
3001a6221aSDavid Daney * this bit in msi_free_irq_bitmask is also using the next bit. This
3101a6221aSDavid Daney * is used so we can disable all of the MSI interrupts when a device
3201a6221aSDavid Daney * uses multiple.
3301a6221aSDavid Daney */
341aa2b278SDavid Daney static u64 msi_multiple_irq_bitmask[4];
3501a6221aSDavid Daney
3601a6221aSDavid Daney /*
3701a6221aSDavid Daney * This lock controls updates to msi_free_irq_bitmask and
3801a6221aSDavid Daney * msi_multiple_irq_bitmask.
3901a6221aSDavid Daney */
4001a6221aSDavid Daney static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
4101a6221aSDavid Daney
421aa2b278SDavid Daney /*
431aa2b278SDavid Daney * Number of MSI IRQs used. This variable is set up in
441aa2b278SDavid Daney * the module init time.
451aa2b278SDavid Daney */
461aa2b278SDavid Daney static int msi_irq_size;
4701a6221aSDavid Daney
4801a6221aSDavid Daney /**
49*d3cd4d9fSRandy Dunlap * arch_setup_msi_irq() - setup MSI IRQs for a device
50*d3cd4d9fSRandy Dunlap * @dev: Device requesting MSI interrupts
51*d3cd4d9fSRandy Dunlap * @desc: MSI descriptor
52*d3cd4d9fSRandy Dunlap *
53*d3cd4d9fSRandy Dunlap * Called when a driver requests MSI interrupts instead of the
5401a6221aSDavid Daney * legacy INT A-D. This routine will allocate multiple interrupts
5501a6221aSDavid Daney * for MSI devices that support them. A device can override this by
5601a6221aSDavid Daney * programming the MSI control bits [6:4] before calling
5701a6221aSDavid Daney * pci_enable_msi().
5801a6221aSDavid Daney *
59*d3cd4d9fSRandy Dunlap * Return: %0 on success, non-%0 on error.
6001a6221aSDavid Daney */
arch_setup_msi_irq(struct pci_dev * dev,struct msi_desc * desc)6101a6221aSDavid Daney int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
6201a6221aSDavid Daney {
6301a6221aSDavid Daney struct msi_msg msg;
641aa2b278SDavid Daney u16 control;
6501a6221aSDavid Daney int configured_private_bits;
6601a6221aSDavid Daney int request_private_bits;
671aa2b278SDavid Daney int irq = 0;
6801a6221aSDavid Daney int irq_step;
691aa2b278SDavid Daney u64 search_mask;
701aa2b278SDavid Daney int index;
7101a6221aSDavid Daney
72bec61847SThomas Gleixner if (desc->pci.msi_attrib.is_msix)
73bec61847SThomas Gleixner return -EINVAL;
74bec61847SThomas Gleixner
7501a6221aSDavid Daney /*
7601a6221aSDavid Daney * Read the MSI config to figure out how many IRQs this device
7701a6221aSDavid Daney * wants. Most devices only want 1, which will give
7801a6221aSDavid Daney * configured_private_bits and request_private_bits equal 0.
7901a6221aSDavid Daney */
8048c3c38fSYijing Wang pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
8101a6221aSDavid Daney
8201a6221aSDavid Daney /*
8301a6221aSDavid Daney * If the number of private bits has been configured then use
8401a6221aSDavid Daney * that value instead of the requested number. This gives the
8501a6221aSDavid Daney * driver the chance to override the number of interrupts
8601a6221aSDavid Daney * before calling pci_enable_msi().
8701a6221aSDavid Daney */
8801a6221aSDavid Daney configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
8901a6221aSDavid Daney if (configured_private_bits == 0) {
9001a6221aSDavid Daney /* Nothing is configured, so use the hardware requested size */
9101a6221aSDavid Daney request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
9201a6221aSDavid Daney } else {
9301a6221aSDavid Daney /*
9401a6221aSDavid Daney * Use the number of configured bits, assuming the
9501a6221aSDavid Daney * driver wanted to override the hardware request
9601a6221aSDavid Daney * value.
9701a6221aSDavid Daney */
9801a6221aSDavid Daney request_private_bits = configured_private_bits;
9901a6221aSDavid Daney }
10001a6221aSDavid Daney
10101a6221aSDavid Daney /*
10201a6221aSDavid Daney * The PCI 2.3 spec mandates that there are at most 32
10301a6221aSDavid Daney * interrupts. If this device asks for more, only give it one.
10401a6221aSDavid Daney */
10501a6221aSDavid Daney if (request_private_bits > 5)
10601a6221aSDavid Daney request_private_bits = 0;
10701a6221aSDavid Daney
10801a6221aSDavid Daney try_only_one:
10901a6221aSDavid Daney /*
11001a6221aSDavid Daney * The IRQs have to be aligned on a power of two based on the
11101a6221aSDavid Daney * number being requested.
11201a6221aSDavid Daney */
11301a6221aSDavid Daney irq_step = 1 << request_private_bits;
11401a6221aSDavid Daney
11501a6221aSDavid Daney /* Mask with one bit for each IRQ */
11601a6221aSDavid Daney search_mask = (1 << irq_step) - 1;
11701a6221aSDavid Daney
11801a6221aSDavid Daney /*
11901a6221aSDavid Daney * We're going to search msi_free_irq_bitmask_lock for zero
12001a6221aSDavid Daney * bits. This represents an MSI interrupt number that isn't in
12101a6221aSDavid Daney * use.
12201a6221aSDavid Daney */
12301a6221aSDavid Daney spin_lock(&msi_free_irq_bitmask_lock);
1241aa2b278SDavid Daney for (index = 0; index < msi_irq_size/64; index++) {
12501a6221aSDavid Daney for (irq = 0; irq < 64; irq += irq_step) {
1261aa2b278SDavid Daney if ((msi_free_irq_bitmask[index] & (search_mask << irq)) == 0) {
1271aa2b278SDavid Daney msi_free_irq_bitmask[index] |= search_mask << irq;
1281aa2b278SDavid Daney msi_multiple_irq_bitmask[index] |= (search_mask >> 1) << irq;
1291aa2b278SDavid Daney goto msi_irq_allocated;
13001a6221aSDavid Daney }
13101a6221aSDavid Daney }
1321aa2b278SDavid Daney }
1331aa2b278SDavid Daney msi_irq_allocated:
13401a6221aSDavid Daney spin_unlock(&msi_free_irq_bitmask_lock);
13501a6221aSDavid Daney
13601a6221aSDavid Daney /* Make sure the search for available interrupts didn't fail */
13701a6221aSDavid Daney if (irq >= 64) {
13801a6221aSDavid Daney if (request_private_bits) {
1391aa2b278SDavid Daney pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one",
14001a6221aSDavid Daney 1 << request_private_bits);
14101a6221aSDavid Daney request_private_bits = 0;
14201a6221aSDavid Daney goto try_only_one;
14301a6221aSDavid Daney } else
1441aa2b278SDavid Daney panic("arch_setup_msi_irq: Unable to find a free MSI interrupt");
14501a6221aSDavid Daney }
14601a6221aSDavid Daney
14701a6221aSDavid Daney /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
1481aa2b278SDavid Daney irq += index*64;
14901a6221aSDavid Daney irq += OCTEON_IRQ_MSI_BIT0;
15001a6221aSDavid Daney
15101a6221aSDavid Daney switch (octeon_dma_bar_type) {
15201a6221aSDavid Daney case OCTEON_DMA_BAR_TYPE_SMALL:
15301a6221aSDavid Daney /* When not using big bar, Bar 0 is based at 128MB */
15401a6221aSDavid Daney msg.address_lo =
15501a6221aSDavid Daney ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
15601a6221aSDavid Daney msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
1577f02c463SColin Ian King break;
15801a6221aSDavid Daney case OCTEON_DMA_BAR_TYPE_BIG:
15901a6221aSDavid Daney /* When using big bar, Bar 0 is based at 0 */
16001a6221aSDavid Daney msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
16101a6221aSDavid Daney msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32;
16201a6221aSDavid Daney break;
16301a6221aSDavid Daney case OCTEON_DMA_BAR_TYPE_PCIE:
16401a6221aSDavid Daney /* When using PCIe, Bar 0 is based at 0 */
16501a6221aSDavid Daney /* FIXME CVMX_NPEI_MSI_RCV* other than 0? */
16601a6221aSDavid Daney msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
16701a6221aSDavid Daney msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
16801a6221aSDavid Daney break;
169d19648d7SEunbong Song case OCTEON_DMA_BAR_TYPE_PCIE2:
170d19648d7SEunbong Song /* When using PCIe2, Bar 0 is based at 0 */
171d19648d7SEunbong Song msg.address_lo = (0 + CVMX_SLI_PCIE_MSI_RCV) & 0xffffffff;
172d19648d7SEunbong Song msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32;
173d19648d7SEunbong Song break;
17401a6221aSDavid Daney default:
175ab75dc02SRalf Baechle panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type");
17601a6221aSDavid Daney }
17701a6221aSDavid Daney msg.data = irq - OCTEON_IRQ_MSI_BIT0;
17801a6221aSDavid Daney
17901a6221aSDavid Daney /* Update the number of IRQs the device has available to it */
18001a6221aSDavid Daney control &= ~PCI_MSI_FLAGS_QSIZE;
18101a6221aSDavid Daney control |= request_private_bits << 4;
18248c3c38fSYijing Wang pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
18301a6221aSDavid Daney
184e4ec7989SThomas Gleixner irq_set_msi_desc(irq, desc);
18583a18912SJiang Liu pci_write_msi_msg(irq, &msg);
18601a6221aSDavid Daney return 0;
18701a6221aSDavid Daney }
18801a6221aSDavid Daney
18901a6221aSDavid Daney /**
190*d3cd4d9fSRandy Dunlap * arch_teardown_msi_irq() - release MSI IRQs for a device
191*d3cd4d9fSRandy Dunlap * @irq: The devices first irq number. There may be multiple in sequence.
192*d3cd4d9fSRandy Dunlap *
19301a6221aSDavid Daney * Called when a device no longer needs its MSI interrupts. All
19401a6221aSDavid Daney * MSI interrupts for the device are freed.
19501a6221aSDavid Daney */
arch_teardown_msi_irq(unsigned int irq)19601a6221aSDavid Daney void arch_teardown_msi_irq(unsigned int irq)
19701a6221aSDavid Daney {
19801a6221aSDavid Daney int number_irqs;
1991aa2b278SDavid Daney u64 bitmask;
2001aa2b278SDavid Daney int index = 0;
2011aa2b278SDavid Daney int irq0;
20201a6221aSDavid Daney
2031aa2b278SDavid Daney if ((irq < OCTEON_IRQ_MSI_BIT0)
2041aa2b278SDavid Daney || (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0))
20501a6221aSDavid Daney panic("arch_teardown_msi_irq: Attempted to teardown illegal "
20601a6221aSDavid Daney "MSI interrupt (%d)", irq);
2071aa2b278SDavid Daney
20801a6221aSDavid Daney irq -= OCTEON_IRQ_MSI_BIT0;
2091aa2b278SDavid Daney index = irq / 64;
2101aa2b278SDavid Daney irq0 = irq % 64;
21101a6221aSDavid Daney
21201a6221aSDavid Daney /*
21301a6221aSDavid Daney * Count the number of IRQs we need to free by looking at the
21401a6221aSDavid Daney * msi_multiple_irq_bitmask. Each bit set means that the next
21501a6221aSDavid Daney * IRQ is also owned by this device.
21601a6221aSDavid Daney */
21701a6221aSDavid Daney number_irqs = 0;
2181aa2b278SDavid Daney while ((irq0 + number_irqs < 64) &&
2191aa2b278SDavid Daney (msi_multiple_irq_bitmask[index]
2201aa2b278SDavid Daney & (1ull << (irq0 + number_irqs))))
22101a6221aSDavid Daney number_irqs++;
22201a6221aSDavid Daney number_irqs++;
22301a6221aSDavid Daney /* Mask with one bit for each IRQ */
22401a6221aSDavid Daney bitmask = (1 << number_irqs) - 1;
22501a6221aSDavid Daney /* Shift the mask to the correct bit location */
2261aa2b278SDavid Daney bitmask <<= irq0;
2271aa2b278SDavid Daney if ((msi_free_irq_bitmask[index] & bitmask) != bitmask)
22801a6221aSDavid Daney panic("arch_teardown_msi_irq: Attempted to teardown MSI "
22901a6221aSDavid Daney "interrupt (%d) not in use", irq);
23001a6221aSDavid Daney
23101a6221aSDavid Daney /* Checks are done, update the in use bitmask */
23201a6221aSDavid Daney spin_lock(&msi_free_irq_bitmask_lock);
2331aa2b278SDavid Daney msi_free_irq_bitmask[index] &= ~bitmask;
2341aa2b278SDavid Daney msi_multiple_irq_bitmask[index] &= ~bitmask;
23501a6221aSDavid Daney spin_unlock(&msi_free_irq_bitmask_lock);
23601a6221aSDavid Daney }
23701a6221aSDavid Daney
2381aa2b278SDavid Daney static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
2391aa2b278SDavid Daney
2401aa2b278SDavid Daney static u64 msi_rcv_reg[4];
2411aa2b278SDavid Daney static u64 mis_ena_reg[4];
2421aa2b278SDavid Daney
octeon_irq_msi_enable_pcie(struct irq_data * data)2430c326387SDavid Daney static void octeon_irq_msi_enable_pcie(struct irq_data *data)
2441aa2b278SDavid Daney {
2451aa2b278SDavid Daney u64 en;
2461aa2b278SDavid Daney unsigned long flags;
2470c326387SDavid Daney int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
2481aa2b278SDavid Daney int irq_index = msi_number >> 6;
2491aa2b278SDavid Daney int irq_bit = msi_number & 0x3f;
2501aa2b278SDavid Daney
2511aa2b278SDavid Daney raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
2521aa2b278SDavid Daney en = cvmx_read_csr(mis_ena_reg[irq_index]);
2531aa2b278SDavid Daney en |= 1ull << irq_bit;
2541aa2b278SDavid Daney cvmx_write_csr(mis_ena_reg[irq_index], en);
2551aa2b278SDavid Daney cvmx_read_csr(mis_ena_reg[irq_index]);
2561aa2b278SDavid Daney raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
2571aa2b278SDavid Daney }
2581aa2b278SDavid Daney
octeon_irq_msi_disable_pcie(struct irq_data * data)2590c326387SDavid Daney static void octeon_irq_msi_disable_pcie(struct irq_data *data)
2601aa2b278SDavid Daney {
2611aa2b278SDavid Daney u64 en;
2621aa2b278SDavid Daney unsigned long flags;
2630c326387SDavid Daney int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
2641aa2b278SDavid Daney int irq_index = msi_number >> 6;
2651aa2b278SDavid Daney int irq_bit = msi_number & 0x3f;
2661aa2b278SDavid Daney
2671aa2b278SDavid Daney raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
2681aa2b278SDavid Daney en = cvmx_read_csr(mis_ena_reg[irq_index]);
2691aa2b278SDavid Daney en &= ~(1ull << irq_bit);
2701aa2b278SDavid Daney cvmx_write_csr(mis_ena_reg[irq_index], en);
2711aa2b278SDavid Daney cvmx_read_csr(mis_ena_reg[irq_index]);
2721aa2b278SDavid Daney raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
2731aa2b278SDavid Daney }
2741aa2b278SDavid Daney
2751aa2b278SDavid Daney static struct irq_chip octeon_irq_chip_msi_pcie = {
2761aa2b278SDavid Daney .name = "MSI",
2770c326387SDavid Daney .irq_enable = octeon_irq_msi_enable_pcie,
2780c326387SDavid Daney .irq_disable = octeon_irq_msi_disable_pcie,
2791aa2b278SDavid Daney };
2801aa2b278SDavid Daney
octeon_irq_msi_enable_pci(struct irq_data * data)2810c326387SDavid Daney static void octeon_irq_msi_enable_pci(struct irq_data *data)
2821aa2b278SDavid Daney {
2831aa2b278SDavid Daney /*
2841aa2b278SDavid Daney * Octeon PCI doesn't have the ability to mask/unmask MSI
2851aa2b278SDavid Daney * interrupts individually. Instead of masking/unmasking them
2861aa2b278SDavid Daney * in groups of 16, we simple assume MSI devices are well
2871aa2b278SDavid Daney * behaved. MSI interrupts are always enable and the ACK is
2881aa2b278SDavid Daney * assumed to be enough
2891aa2b278SDavid Daney */
2901aa2b278SDavid Daney }
2911aa2b278SDavid Daney
octeon_irq_msi_disable_pci(struct irq_data * data)2920c326387SDavid Daney static void octeon_irq_msi_disable_pci(struct irq_data *data)
2931aa2b278SDavid Daney {
2941aa2b278SDavid Daney /* See comment in enable */
2951aa2b278SDavid Daney }
2961aa2b278SDavid Daney
2971aa2b278SDavid Daney static struct irq_chip octeon_irq_chip_msi_pci = {
2981aa2b278SDavid Daney .name = "MSI",
2990c326387SDavid Daney .irq_enable = octeon_irq_msi_enable_pci,
3000c326387SDavid Daney .irq_disable = octeon_irq_msi_disable_pci,
3011aa2b278SDavid Daney };
30201a6221aSDavid Daney
30301a6221aSDavid Daney /*
30401a6221aSDavid Daney * Called by the interrupt handling code when an MSI interrupt
30501a6221aSDavid Daney * occurs.
30601a6221aSDavid Daney */
__octeon_msi_do_interrupt(int index,u64 msi_bits)3071aa2b278SDavid Daney static irqreturn_t __octeon_msi_do_interrupt(int index, u64 msi_bits)
30801a6221aSDavid Daney {
30901a6221aSDavid Daney int irq;
3101aa2b278SDavid Daney int bit;
31101a6221aSDavid Daney
3121aa2b278SDavid Daney bit = fls64(msi_bits);
3131aa2b278SDavid Daney if (bit) {
3141aa2b278SDavid Daney bit--;
3151aa2b278SDavid Daney /* Acknowledge it first. */
3161aa2b278SDavid Daney cvmx_write_csr(msi_rcv_reg[index], 1ull << bit);
3171aa2b278SDavid Daney
3181aa2b278SDavid Daney irq = bit + OCTEON_IRQ_MSI_BIT0 + 64 * index;
31901a6221aSDavid Daney do_IRQ(irq);
32001a6221aSDavid Daney return IRQ_HANDLED;
32101a6221aSDavid Daney }
32201a6221aSDavid Daney return IRQ_NONE;
32301a6221aSDavid Daney }
32401a6221aSDavid Daney
3251aa2b278SDavid Daney #define OCTEON_MSI_INT_HANDLER_X(x) \
3261aa2b278SDavid Daney static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id) \
3271aa2b278SDavid Daney { \
3281aa2b278SDavid Daney u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \
3291aa2b278SDavid Daney return __octeon_msi_do_interrupt((x), msi_bits); \
3301aa2b278SDavid Daney }
331a894f14dSDavid Daney
332a894f14dSDavid Daney /*
3331aa2b278SDavid Daney * Create octeon_msi_interrupt{0-3} function body
334a894f14dSDavid Daney */
3351aa2b278SDavid Daney OCTEON_MSI_INT_HANDLER_X(0);
3361aa2b278SDavid Daney OCTEON_MSI_INT_HANDLER_X(1);
3371aa2b278SDavid Daney OCTEON_MSI_INT_HANDLER_X(2);
3381aa2b278SDavid Daney OCTEON_MSI_INT_HANDLER_X(3);
33901a6221aSDavid Daney
34001a6221aSDavid Daney /*
34101a6221aSDavid Daney * Initializes the MSI interrupt handling code
34201a6221aSDavid Daney */
octeon_msi_initialize(void)3431aa2b278SDavid Daney int __init octeon_msi_initialize(void)
34401a6221aSDavid Daney {
345a894f14dSDavid Daney int irq;
3461aa2b278SDavid Daney struct irq_chip *msi;
347a894f14dSDavid Daney
348a214720cSYunQiang Su if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_INVALID) {
349a214720cSYunQiang Su return 0;
350a214720cSYunQiang Su } else if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
3511aa2b278SDavid Daney msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0;
3521aa2b278SDavid Daney msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1;
3531aa2b278SDavid Daney msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2;
3541aa2b278SDavid Daney msi_rcv_reg[3] = CVMX_PEXP_NPEI_MSI_RCV3;
3551aa2b278SDavid Daney mis_ena_reg[0] = CVMX_PEXP_NPEI_MSI_ENB0;
3561aa2b278SDavid Daney mis_ena_reg[1] = CVMX_PEXP_NPEI_MSI_ENB1;
3571aa2b278SDavid Daney mis_ena_reg[2] = CVMX_PEXP_NPEI_MSI_ENB2;
3581aa2b278SDavid Daney mis_ena_reg[3] = CVMX_PEXP_NPEI_MSI_ENB3;
3591aa2b278SDavid Daney msi = &octeon_irq_chip_msi_pcie;
3601aa2b278SDavid Daney } else {
3611aa2b278SDavid Daney msi_rcv_reg[0] = CVMX_NPI_NPI_MSI_RCV;
3621aa2b278SDavid Daney #define INVALID_GENERATE_ADE 0x8700000000000000ULL;
3631aa2b278SDavid Daney msi_rcv_reg[1] = INVALID_GENERATE_ADE;
3641aa2b278SDavid Daney msi_rcv_reg[2] = INVALID_GENERATE_ADE;
3651aa2b278SDavid Daney msi_rcv_reg[3] = INVALID_GENERATE_ADE;
3661aa2b278SDavid Daney mis_ena_reg[0] = INVALID_GENERATE_ADE;
3671aa2b278SDavid Daney mis_ena_reg[1] = INVALID_GENERATE_ADE;
3681aa2b278SDavid Daney mis_ena_reg[2] = INVALID_GENERATE_ADE;
3691aa2b278SDavid Daney mis_ena_reg[3] = INVALID_GENERATE_ADE;
3701aa2b278SDavid Daney msi = &octeon_irq_chip_msi_pci;
371a894f14dSDavid Daney }
372a894f14dSDavid Daney
3731aa2b278SDavid Daney for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++)
374e4ec7989SThomas Gleixner irq_set_chip_and_handler(irq, msi, handle_simple_irq);
3751aa2b278SDavid Daney
37601a6221aSDavid Daney if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
3771aa2b278SDavid Daney if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
3781aa2b278SDavid Daney 0, "MSI[0:63]", octeon_msi_interrupt0))
37901a6221aSDavid Daney panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
38001a6221aSDavid Daney
3811aa2b278SDavid Daney if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt1,
3821aa2b278SDavid Daney 0, "MSI[64:127]", octeon_msi_interrupt1))
38301a6221aSDavid Daney panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
38401a6221aSDavid Daney
3851aa2b278SDavid Daney if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt2,
3861aa2b278SDavid Daney 0, "MSI[127:191]", octeon_msi_interrupt2))
38701a6221aSDavid Daney panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
38801a6221aSDavid Daney
3891aa2b278SDavid Daney if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt3,
3901aa2b278SDavid Daney 0, "MSI[192:255]", octeon_msi_interrupt3))
39101a6221aSDavid Daney panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
39201a6221aSDavid Daney
3931aa2b278SDavid Daney msi_irq_size = 256;
3941aa2b278SDavid Daney } else if (octeon_is_pci_host()) {
3951aa2b278SDavid Daney if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
3961aa2b278SDavid Daney 0, "MSI[0:15]", octeon_msi_interrupt0))
3971aa2b278SDavid Daney panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
3981aa2b278SDavid Daney
3991aa2b278SDavid Daney if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt0,
4001aa2b278SDavid Daney 0, "MSI[16:31]", octeon_msi_interrupt0))
4011aa2b278SDavid Daney panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
4021aa2b278SDavid Daney
4031aa2b278SDavid Daney if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt0,
4041aa2b278SDavid Daney 0, "MSI[32:47]", octeon_msi_interrupt0))
4051aa2b278SDavid Daney panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
4061aa2b278SDavid Daney
4071aa2b278SDavid Daney if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt0,
4081aa2b278SDavid Daney 0, "MSI[48:63]", octeon_msi_interrupt0))
4091aa2b278SDavid Daney panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
4101aa2b278SDavid Daney msi_irq_size = 64;
41101a6221aSDavid Daney }
41201a6221aSDavid Daney return 0;
41301a6221aSDavid Daney }
41401a6221aSDavid Daney subsys_initcall(octeon_msi_initialize);
415