11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * Cobalt Qube/Raq PCI support 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * This file is subject to the terms and conditions of the GNU General Public 51da177e4SLinus Torvalds * License. See the file "COPYING" in the main directory of this archive 61da177e4SLinus Torvalds * for more details. 71da177e4SLinus Torvalds * 81da177e4SLinus Torvalds * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle 91da177e4SLinus Torvalds * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) 101da177e4SLinus Torvalds */ 111da177e4SLinus Torvalds #include <linux/types.h> 121da177e4SLinus Torvalds #include <linux/pci.h> 131da177e4SLinus Torvalds #include <linux/kernel.h> 141da177e4SLinus Torvalds #include <linux/init.h> 151da177e4SLinus Torvalds 161da177e4SLinus Torvalds #include <asm/pci.h> 171da177e4SLinus Torvalds #include <asm/io.h> 181da177e4SLinus Torvalds #include <asm/gt64120.h> 191da177e4SLinus Torvalds 2044320f2bSYoichi Yuasa #include <cobalt.h> 211da177e4SLinus Torvalds 22c4ed38a0SRalf Baechle static void qube_raq_galileo_early_fixup(struct pci_dev *dev) 23c4ed38a0SRalf Baechle { 24c4ed38a0SRalf Baechle if (dev->devfn == PCI_DEVFN(0, 0) && 25c4ed38a0SRalf Baechle (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) { 26c4ed38a0SRalf Baechle 27c4ed38a0SRalf Baechle dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff); 28c4ed38a0SRalf Baechle 29c4ed38a0SRalf Baechle printk(KERN_INFO "Galileo: fixed bridge class\n"); 30c4ed38a0SRalf Baechle } 31c4ed38a0SRalf Baechle } 32c4ed38a0SRalf Baechle 33c4ed38a0SRalf Baechle DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, 34c4ed38a0SRalf Baechle qube_raq_galileo_early_fixup); 35c4ed38a0SRalf Baechle 361da177e4SLinus Torvalds static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) 371da177e4SLinus Torvalds { 381da177e4SLinus Torvalds unsigned short cfgword; 391da177e4SLinus Torvalds unsigned char lt; 401da177e4SLinus Torvalds 411da177e4SLinus Torvalds /* Enable Bus Mastering and fast back to back. */ 421da177e4SLinus Torvalds pci_read_config_word(dev, PCI_COMMAND, &cfgword); 431da177e4SLinus Torvalds cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER); 441da177e4SLinus Torvalds pci_write_config_word(dev, PCI_COMMAND, cfgword); 451da177e4SLinus Torvalds 461da177e4SLinus Torvalds /* Enable both ide interfaces. ROM only enables primary one. */ 471da177e4SLinus Torvalds pci_write_config_byte(dev, 0x40, 0xb); 481da177e4SLinus Torvalds 491da177e4SLinus Torvalds /* Set latency timer to reasonable value. */ 501da177e4SLinus Torvalds pci_read_config_byte(dev, PCI_LATENCY_TIMER, <); 511da177e4SLinus Torvalds if (lt < 64) 521da177e4SLinus Torvalds pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); 5352378445SPeter Horton pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); 541da177e4SLinus Torvalds } 551da177e4SLinus Torvalds 561da177e4SLinus Torvalds DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 571da177e4SLinus Torvalds qube_raq_via_bmIDE_fixup); 581da177e4SLinus Torvalds 591da177e4SLinus Torvalds static void qube_raq_galileo_fixup(struct pci_dev *dev) 601da177e4SLinus Torvalds { 61c4ed38a0SRalf Baechle if (dev->devfn != PCI_DEVFN(0, 0)) 62c4ed38a0SRalf Baechle return; 63c4ed38a0SRalf Baechle 641da177e4SLinus Torvalds /* Fix PCI latency-timer and cache-line-size values in Galileo 651da177e4SLinus Torvalds * host bridge. 661da177e4SLinus Torvalds */ 671da177e4SLinus Torvalds pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); 6852378445SPeter Horton pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); 691da177e4SLinus Torvalds 701da177e4SLinus Torvalds /* 71c4ed38a0SRalf Baechle * The code described by the comment below has been removed 72c4ed38a0SRalf Baechle * as it causes bus mastering by the Ethernet controllers 73c4ed38a0SRalf Baechle * to break under any kind of network load. We always set 74c4ed38a0SRalf Baechle * the retry timeouts to their maximum. 75c4ed38a0SRalf Baechle * 76c4ed38a0SRalf Baechle * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x-- 77c4ed38a0SRalf Baechle * 781da177e4SLinus Torvalds * On all machines prior to Q2, we had the STOP line disconnected 791da177e4SLinus Torvalds * from Galileo to VIA on PCI. The new Galileo does not function 801da177e4SLinus Torvalds * correctly unless we have it connected. 811da177e4SLinus Torvalds * 821da177e4SLinus Torvalds * Therefore we must set the disconnect/retry cycle values to 831da177e4SLinus Torvalds * something sensible when using the new Galileo. 841da177e4SLinus Torvalds */ 85c4ed38a0SRalf Baechle 8644c10138SAuke Kok printk(KERN_INFO "Galileo: revision %u\n", dev->revision); 87c4ed38a0SRalf Baechle 88c4ed38a0SRalf Baechle #if 0 8944c10138SAuke Kok if (dev->revision >= 0x10) { 901da177e4SLinus Torvalds /* New Galileo, assumes PCI stop line to VIA is connected. */ 9156ae5833SYoichi Yuasa GT_WRITE(GT_PCI0_TOR_OFS, 0x4020); 9244c10138SAuke Kok } else if (dev->revision == 0x1 || dev->revision == 0x2) 93c4ed38a0SRalf Baechle #endif 94c4ed38a0SRalf Baechle { 951da177e4SLinus Torvalds signed int timeo; 961da177e4SLinus Torvalds /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ 9756ae5833SYoichi Yuasa timeo = GT_READ(GT_PCI0_TOR_OFS); 981da177e4SLinus Torvalds /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ 9956ae5833SYoichi Yuasa GT_WRITE(GT_PCI0_TOR_OFS, 100c4ed38a0SRalf Baechle (0xff << 16) | /* retry count */ 101c4ed38a0SRalf Baechle (0xff << 8) | /* timeout 1 */ 10256ae5833SYoichi Yuasa 0xff); /* timeout 0 */ 103c4ed38a0SRalf Baechle 104c4ed38a0SRalf Baechle /* enable PCI retry exceeded interrupt */ 10556ae5833SYoichi Yuasa GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS)); 1061da177e4SLinus Torvalds } 1071da177e4SLinus Torvalds } 1081da177e4SLinus Torvalds 109c4ed38a0SRalf Baechle DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, 1101da177e4SLinus Torvalds qube_raq_galileo_fixup); 1111da177e4SLinus Torvalds 1123f2d560eSYoichi Yuasa int cobalt_board_id; 1133f2d560eSYoichi Yuasa 1143f2d560eSYoichi Yuasa static void qube_raq_via_board_id_fixup(struct pci_dev *dev) 1153f2d560eSYoichi Yuasa { 1163f2d560eSYoichi Yuasa u8 id; 1173f2d560eSYoichi Yuasa int retval; 1183f2d560eSYoichi Yuasa 1193f2d560eSYoichi Yuasa retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id); 1203f2d560eSYoichi Yuasa if (retval) { 1213f2d560eSYoichi Yuasa panic("Cannot read board ID"); 1223f2d560eSYoichi Yuasa return; 1233f2d560eSYoichi Yuasa } 1243f2d560eSYoichi Yuasa 1253f2d560eSYoichi Yuasa cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id); 1263f2d560eSYoichi Yuasa 1273f2d560eSYoichi Yuasa printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id); 1283f2d560eSYoichi Yuasa } 1293f2d560eSYoichi Yuasa 1303f2d560eSYoichi Yuasa DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, 1313f2d560eSYoichi Yuasa qube_raq_via_board_id_fixup); 1323f2d560eSYoichi Yuasa 133c4ed38a0SRalf Baechle static char irq_tab_qube1[] __initdata = { 134c4ed38a0SRalf Baechle [COBALT_PCICONF_CPU] = 0, 135c4ed38a0SRalf Baechle [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ, 136c4ed38a0SRalf Baechle [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, 137c4ed38a0SRalf Baechle [COBALT_PCICONF_VIA] = 0, 138c4ed38a0SRalf Baechle [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, 139c4ed38a0SRalf Baechle [COBALT_PCICONF_ETH1] = 0 140c4ed38a0SRalf Baechle }; 141c4ed38a0SRalf Baechle 1421da177e4SLinus Torvalds static char irq_tab_cobalt[] __initdata = { 1431da177e4SLinus Torvalds [COBALT_PCICONF_CPU] = 0, 1441da177e4SLinus Torvalds [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, 1451da177e4SLinus Torvalds [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, 1461da177e4SLinus Torvalds [COBALT_PCICONF_VIA] = 0, 1471da177e4SLinus Torvalds [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, 1481da177e4SLinus Torvalds [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ 1491da177e4SLinus Torvalds }; 1501da177e4SLinus Torvalds 1511da177e4SLinus Torvalds static char irq_tab_raq2[] __initdata = { 1521da177e4SLinus Torvalds [COBALT_PCICONF_CPU] = 0, 1531da177e4SLinus Torvalds [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, 1541da177e4SLinus Torvalds [COBALT_PCICONF_RAQSCSI] = COBALT_RAQ_SCSI_IRQ, 1551da177e4SLinus Torvalds [COBALT_PCICONF_VIA] = 0, 1561da177e4SLinus Torvalds [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, 1571da177e4SLinus Torvalds [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ 1581da177e4SLinus Torvalds }; 1591da177e4SLinus Torvalds 16019df0d11SRalf Baechle int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 1611da177e4SLinus Torvalds { 162c4ed38a0SRalf Baechle if (cobalt_board_id < COBALT_BRD_ID_QUBE2) 163c4ed38a0SRalf Baechle return irq_tab_qube1[slot]; 164c4ed38a0SRalf Baechle 1651da177e4SLinus Torvalds if (cobalt_board_id == COBALT_BRD_ID_RAQ2) 1661da177e4SLinus Torvalds return irq_tab_raq2[slot]; 1671da177e4SLinus Torvalds 1681da177e4SLinus Torvalds return irq_tab_cobalt[slot]; 1691da177e4SLinus Torvalds } 1701da177e4SLinus Torvalds 1711da177e4SLinus Torvalds /* Do platform specific device initialization at pci_enable_device() time */ 1721da177e4SLinus Torvalds int pcibios_plat_dev_init(struct pci_dev *dev) 1731da177e4SLinus Torvalds { 1741da177e4SLinus Torvalds return 0; 1751da177e4SLinus Torvalds } 176