11da177e4SLinus Torvalds /*
21da177e4SLinus Torvalds * Cobalt Qube/Raq PCI support
31da177e4SLinus Torvalds *
41da177e4SLinus Torvalds * This file is subject to the terms and conditions of the GNU General Public
51da177e4SLinus Torvalds * License. See the file "COPYING" in the main directory of this archive
61da177e4SLinus Torvalds * for more details.
71da177e4SLinus Torvalds *
81da177e4SLinus Torvalds * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
91da177e4SLinus Torvalds * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
101da177e4SLinus Torvalds */
111da177e4SLinus Torvalds #include <linux/types.h>
121da177e4SLinus Torvalds #include <linux/pci.h>
131da177e4SLinus Torvalds #include <linux/kernel.h>
141da177e4SLinus Torvalds #include <linux/init.h>
151da177e4SLinus Torvalds
161da177e4SLinus Torvalds #include <asm/io.h>
171da177e4SLinus Torvalds #include <asm/gt64120.h>
181da177e4SLinus Torvalds
1944320f2bSYoichi Yuasa #include <cobalt.h>
20d5ab1a69SYoichi Yuasa #include <irq.h>
211da177e4SLinus Torvalds
22b4126e86SYoichi Yuasa /*
23b4126e86SYoichi Yuasa * PCI slot numbers
24b4126e86SYoichi Yuasa */
25b4126e86SYoichi Yuasa #define COBALT_PCICONF_CPU 0x06
26b4126e86SYoichi Yuasa #define COBALT_PCICONF_ETH0 0x07
27b4126e86SYoichi Yuasa #define COBALT_PCICONF_RAQSCSI 0x08
28b4126e86SYoichi Yuasa #define COBALT_PCICONF_VIA 0x09
29b4126e86SYoichi Yuasa #define COBALT_PCICONF_PCISLOT 0x0A
30b4126e86SYoichi Yuasa #define COBALT_PCICONF_ETH1 0x0C
31b4126e86SYoichi Yuasa
32b4126e86SYoichi Yuasa /*
33b4126e86SYoichi Yuasa * The Cobalt board ID information. The boards have an ID number wired
34b4126e86SYoichi Yuasa * into the VIA that is available in the high nibble of register 94.
35b4126e86SYoichi Yuasa */
36b4126e86SYoichi Yuasa #define VIA_COBALT_BRD_ID_REG 0x94
37b4126e86SYoichi Yuasa #define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4)
38b4126e86SYoichi Yuasa
39*36de23a4SPali Rohár /*
40*36de23a4SPali Rohár * Default value of PCI Class Code on GT64111 is PCI_CLASS_MEMORY_OTHER (0x0580)
41*36de23a4SPali Rohár * instead of PCI_CLASS_BRIDGE_HOST (0x0600). Galileo explained this choice in
42*36de23a4SPali Rohár * document "GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs",
43*36de23a4SPali Rohár * section "6.5.3 PCI Autoconfiguration at RESET":
44*36de23a4SPali Rohár *
45*36de23a4SPali Rohár * Some PCs refuse to configure host bridges if they are found plugged into
46*36de23a4SPali Rohár * a PCI slot (ask the BIOS vendors why...). The "Memory Controller" Class
47*36de23a4SPali Rohár * Code does not cause a problem for these non-compliant BIOSes, so we used
48*36de23a4SPali Rohár * this as the default in the GT-64111.
49*36de23a4SPali Rohár *
50*36de23a4SPali Rohár * So fix the incorrect default value of PCI Class Code. More details are on:
51*36de23a4SPali Rohár * https://lore.kernel.org/r/20211102154831.xtrlgrmrizl5eidl@pali/
52*36de23a4SPali Rohár * https://lore.kernel.org/r/20211102150201.GA11675@alpha.franken.de/
53*36de23a4SPali Rohár */
qube_raq_galileo_early_fixup(struct pci_dev * dev)5428eb0e46SGreg Kroah-Hartman static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
55c4ed38a0SRalf Baechle {
56c4ed38a0SRalf Baechle if (dev->devfn == PCI_DEVFN(0, 0) &&
57c4ed38a0SRalf Baechle (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
58c4ed38a0SRalf Baechle
59c4ed38a0SRalf Baechle dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
60c4ed38a0SRalf Baechle
61c4ed38a0SRalf Baechle printk(KERN_INFO "Galileo: fixed bridge class\n");
62c4ed38a0SRalf Baechle }
63c4ed38a0SRalf Baechle }
64c4ed38a0SRalf Baechle
65c4ed38a0SRalf Baechle DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
66c4ed38a0SRalf Baechle qube_raq_galileo_early_fixup);
67c4ed38a0SRalf Baechle
qube_raq_via_bmIDE_fixup(struct pci_dev * dev)6828eb0e46SGreg Kroah-Hartman static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
691da177e4SLinus Torvalds {
701da177e4SLinus Torvalds unsigned short cfgword;
711da177e4SLinus Torvalds unsigned char lt;
721da177e4SLinus Torvalds
731da177e4SLinus Torvalds /* Enable Bus Mastering and fast back to back. */
741da177e4SLinus Torvalds pci_read_config_word(dev, PCI_COMMAND, &cfgword);
751da177e4SLinus Torvalds cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
761da177e4SLinus Torvalds pci_write_config_word(dev, PCI_COMMAND, cfgword);
771da177e4SLinus Torvalds
781da177e4SLinus Torvalds /* Enable both ide interfaces. ROM only enables primary one. */
791da177e4SLinus Torvalds pci_write_config_byte(dev, 0x40, 0xb);
801da177e4SLinus Torvalds
811da177e4SLinus Torvalds /* Set latency timer to reasonable value. */
821da177e4SLinus Torvalds pci_read_config_byte(dev, PCI_LATENCY_TIMER, <);
831da177e4SLinus Torvalds if (lt < 64)
841da177e4SLinus Torvalds pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
8552378445SPeter Horton pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
861da177e4SLinus Torvalds }
871da177e4SLinus Torvalds
881da177e4SLinus Torvalds DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
891da177e4SLinus Torvalds qube_raq_via_bmIDE_fixup);
901da177e4SLinus Torvalds
qube_raq_galileo_fixup(struct pci_dev * dev)9128eb0e46SGreg Kroah-Hartman static void qube_raq_galileo_fixup(struct pci_dev *dev)
921da177e4SLinus Torvalds {
93c4ed38a0SRalf Baechle if (dev->devfn != PCI_DEVFN(0, 0))
94c4ed38a0SRalf Baechle return;
95c4ed38a0SRalf Baechle
961da177e4SLinus Torvalds /* Fix PCI latency-timer and cache-line-size values in Galileo
971da177e4SLinus Torvalds * host bridge.
981da177e4SLinus Torvalds */
991da177e4SLinus Torvalds pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
10052378445SPeter Horton pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
1011da177e4SLinus Torvalds
1021da177e4SLinus Torvalds /*
103c4ed38a0SRalf Baechle * The code described by the comment below has been removed
104c4ed38a0SRalf Baechle * as it causes bus mastering by the Ethernet controllers
105c4ed38a0SRalf Baechle * to break under any kind of network load. We always set
106c4ed38a0SRalf Baechle * the retry timeouts to their maximum.
107c4ed38a0SRalf Baechle *
108c4ed38a0SRalf Baechle * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
109c4ed38a0SRalf Baechle *
1101da177e4SLinus Torvalds * On all machines prior to Q2, we had the STOP line disconnected
1111da177e4SLinus Torvalds * from Galileo to VIA on PCI. The new Galileo does not function
1121da177e4SLinus Torvalds * correctly unless we have it connected.
1131da177e4SLinus Torvalds *
1141da177e4SLinus Torvalds * Therefore we must set the disconnect/retry cycle values to
1151da177e4SLinus Torvalds * something sensible when using the new Galileo.
1161da177e4SLinus Torvalds */
117c4ed38a0SRalf Baechle
11844c10138SAuke Kok printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
119c4ed38a0SRalf Baechle
120c4ed38a0SRalf Baechle #if 0
12144c10138SAuke Kok if (dev->revision >= 0x10) {
1221da177e4SLinus Torvalds /* New Galileo, assumes PCI stop line to VIA is connected. */
12356ae5833SYoichi Yuasa GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
12444c10138SAuke Kok } else if (dev->revision == 0x1 || dev->revision == 0x2)
125c4ed38a0SRalf Baechle #endif
126c4ed38a0SRalf Baechle {
1271da177e4SLinus Torvalds signed int timeo;
1281da177e4SLinus Torvalds /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
12956ae5833SYoichi Yuasa timeo = GT_READ(GT_PCI0_TOR_OFS);
1301da177e4SLinus Torvalds /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
13156ae5833SYoichi Yuasa GT_WRITE(GT_PCI0_TOR_OFS,
132c4ed38a0SRalf Baechle (0xff << 16) | /* retry count */
133c4ed38a0SRalf Baechle (0xff << 8) | /* timeout 1 */
13456ae5833SYoichi Yuasa 0xff); /* timeout 0 */
135c4ed38a0SRalf Baechle
136c4ed38a0SRalf Baechle /* enable PCI retry exceeded interrupt */
13756ae5833SYoichi Yuasa GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
1381da177e4SLinus Torvalds }
1391da177e4SLinus Torvalds }
1401da177e4SLinus Torvalds
141c4ed38a0SRalf Baechle DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
1421da177e4SLinus Torvalds qube_raq_galileo_fixup);
1431da177e4SLinus Torvalds
1443f2d560eSYoichi Yuasa int cobalt_board_id;
1453f2d560eSYoichi Yuasa
qube_raq_via_board_id_fixup(struct pci_dev * dev)14628eb0e46SGreg Kroah-Hartman static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
1473f2d560eSYoichi Yuasa {
1483f2d560eSYoichi Yuasa u8 id;
1493f2d560eSYoichi Yuasa int retval;
1503f2d560eSYoichi Yuasa
1513f2d560eSYoichi Yuasa retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
1523f2d560eSYoichi Yuasa if (retval) {
1533f2d560eSYoichi Yuasa panic("Cannot read board ID");
1543f2d560eSYoichi Yuasa return;
1553f2d560eSYoichi Yuasa }
1563f2d560eSYoichi Yuasa
1573f2d560eSYoichi Yuasa cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);
1583f2d560eSYoichi Yuasa
1593f2d560eSYoichi Yuasa printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
1603f2d560eSYoichi Yuasa }
1613f2d560eSYoichi Yuasa
1623f2d560eSYoichi Yuasa DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
1633f2d560eSYoichi Yuasa qube_raq_via_board_id_fixup);
1643f2d560eSYoichi Yuasa
16519a8d6b7SLorenzo Pieralisi static char irq_tab_qube1[] = {
166c4ed38a0SRalf Baechle [COBALT_PCICONF_CPU] = 0,
167d5ab1a69SYoichi Yuasa [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,
168d5ab1a69SYoichi Yuasa [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
169c4ed38a0SRalf Baechle [COBALT_PCICONF_VIA] = 0,
170d5ab1a69SYoichi Yuasa [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
171c4ed38a0SRalf Baechle [COBALT_PCICONF_ETH1] = 0
172c4ed38a0SRalf Baechle };
173c4ed38a0SRalf Baechle
17419a8d6b7SLorenzo Pieralisi static char irq_tab_cobalt[] = {
1751da177e4SLinus Torvalds [COBALT_PCICONF_CPU] = 0,
176d5ab1a69SYoichi Yuasa [COBALT_PCICONF_ETH0] = ETH0_IRQ,
177d5ab1a69SYoichi Yuasa [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
1781da177e4SLinus Torvalds [COBALT_PCICONF_VIA] = 0,
179d5ab1a69SYoichi Yuasa [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
180d5ab1a69SYoichi Yuasa [COBALT_PCICONF_ETH1] = ETH1_IRQ
1811da177e4SLinus Torvalds };
1821da177e4SLinus Torvalds
18319a8d6b7SLorenzo Pieralisi static char irq_tab_raq2[] = {
1841da177e4SLinus Torvalds [COBALT_PCICONF_CPU] = 0,
185d5ab1a69SYoichi Yuasa [COBALT_PCICONF_ETH0] = ETH0_IRQ,
186d5ab1a69SYoichi Yuasa [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
1871da177e4SLinus Torvalds [COBALT_PCICONF_VIA] = 0,
188d5ab1a69SYoichi Yuasa [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
189d5ab1a69SYoichi Yuasa [COBALT_PCICONF_ETH1] = ETH1_IRQ
1901da177e4SLinus Torvalds };
1911da177e4SLinus Torvalds
pcibios_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)19219a8d6b7SLorenzo Pieralisi int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1931da177e4SLinus Torvalds {
194f6c0f32eSThomas Bogendoerfer if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
195c4ed38a0SRalf Baechle return irq_tab_qube1[slot];
196c4ed38a0SRalf Baechle
1971da177e4SLinus Torvalds if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
1981da177e4SLinus Torvalds return irq_tab_raq2[slot];
1991da177e4SLinus Torvalds
2001da177e4SLinus Torvalds return irq_tab_cobalt[slot];
2011da177e4SLinus Torvalds }
2021da177e4SLinus Torvalds
2031da177e4SLinus Torvalds /* Do platform specific device initialization at pci_enable_device() time */
pcibios_plat_dev_init(struct pci_dev * dev)2041da177e4SLinus Torvalds int pcibios_plat_dev_init(struct pci_dev *dev)
2051da177e4SLinus Torvalds {
2061da177e4SLinus Torvalds return 0;
2071da177e4SLinus Torvalds }
208