11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * Cobalt Qube/Raq PCI support 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * This file is subject to the terms and conditions of the GNU General Public 51da177e4SLinus Torvalds * License. See the file "COPYING" in the main directory of this archive 61da177e4SLinus Torvalds * for more details. 71da177e4SLinus Torvalds * 81da177e4SLinus Torvalds * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle 91da177e4SLinus Torvalds * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) 101da177e4SLinus Torvalds */ 111da177e4SLinus Torvalds #include <linux/types.h> 121da177e4SLinus Torvalds #include <linux/pci.h> 131da177e4SLinus Torvalds #include <linux/kernel.h> 141da177e4SLinus Torvalds #include <linux/init.h> 151da177e4SLinus Torvalds 161da177e4SLinus Torvalds #include <asm/io.h> 171da177e4SLinus Torvalds #include <asm/gt64120.h> 181da177e4SLinus Torvalds 1944320f2bSYoichi Yuasa #include <cobalt.h> 20d5ab1a69SYoichi Yuasa #include <irq.h> 211da177e4SLinus Torvalds 22b4126e86SYoichi Yuasa /* 23b4126e86SYoichi Yuasa * PCI slot numbers 24b4126e86SYoichi Yuasa */ 25b4126e86SYoichi Yuasa #define COBALT_PCICONF_CPU 0x06 26b4126e86SYoichi Yuasa #define COBALT_PCICONF_ETH0 0x07 27b4126e86SYoichi Yuasa #define COBALT_PCICONF_RAQSCSI 0x08 28b4126e86SYoichi Yuasa #define COBALT_PCICONF_VIA 0x09 29b4126e86SYoichi Yuasa #define COBALT_PCICONF_PCISLOT 0x0A 30b4126e86SYoichi Yuasa #define COBALT_PCICONF_ETH1 0x0C 31b4126e86SYoichi Yuasa 32b4126e86SYoichi Yuasa /* 33b4126e86SYoichi Yuasa * The Cobalt board ID information. The boards have an ID number wired 34b4126e86SYoichi Yuasa * into the VIA that is available in the high nibble of register 94. 35b4126e86SYoichi Yuasa */ 36b4126e86SYoichi Yuasa #define VIA_COBALT_BRD_ID_REG 0x94 37b4126e86SYoichi Yuasa #define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4) 38b4126e86SYoichi Yuasa 3928eb0e46SGreg Kroah-Hartman static void qube_raq_galileo_early_fixup(struct pci_dev *dev) 40c4ed38a0SRalf Baechle { 41c4ed38a0SRalf Baechle if (dev->devfn == PCI_DEVFN(0, 0) && 42c4ed38a0SRalf Baechle (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) { 43c4ed38a0SRalf Baechle 44c4ed38a0SRalf Baechle dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff); 45c4ed38a0SRalf Baechle 46c4ed38a0SRalf Baechle printk(KERN_INFO "Galileo: fixed bridge class\n"); 47c4ed38a0SRalf Baechle } 48c4ed38a0SRalf Baechle } 49c4ed38a0SRalf Baechle 50c4ed38a0SRalf Baechle DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, 51c4ed38a0SRalf Baechle qube_raq_galileo_early_fixup); 52c4ed38a0SRalf Baechle 5328eb0e46SGreg Kroah-Hartman static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) 541da177e4SLinus Torvalds { 551da177e4SLinus Torvalds unsigned short cfgword; 561da177e4SLinus Torvalds unsigned char lt; 571da177e4SLinus Torvalds 581da177e4SLinus Torvalds /* Enable Bus Mastering and fast back to back. */ 591da177e4SLinus Torvalds pci_read_config_word(dev, PCI_COMMAND, &cfgword); 601da177e4SLinus Torvalds cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER); 611da177e4SLinus Torvalds pci_write_config_word(dev, PCI_COMMAND, cfgword); 621da177e4SLinus Torvalds 631da177e4SLinus Torvalds /* Enable both ide interfaces. ROM only enables primary one. */ 641da177e4SLinus Torvalds pci_write_config_byte(dev, 0x40, 0xb); 651da177e4SLinus Torvalds 661da177e4SLinus Torvalds /* Set latency timer to reasonable value. */ 671da177e4SLinus Torvalds pci_read_config_byte(dev, PCI_LATENCY_TIMER, <); 681da177e4SLinus Torvalds if (lt < 64) 691da177e4SLinus Torvalds pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); 7052378445SPeter Horton pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); 711da177e4SLinus Torvalds } 721da177e4SLinus Torvalds 731da177e4SLinus Torvalds DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 741da177e4SLinus Torvalds qube_raq_via_bmIDE_fixup); 751da177e4SLinus Torvalds 7628eb0e46SGreg Kroah-Hartman static void qube_raq_galileo_fixup(struct pci_dev *dev) 771da177e4SLinus Torvalds { 78c4ed38a0SRalf Baechle if (dev->devfn != PCI_DEVFN(0, 0)) 79c4ed38a0SRalf Baechle return; 80c4ed38a0SRalf Baechle 811da177e4SLinus Torvalds /* Fix PCI latency-timer and cache-line-size values in Galileo 821da177e4SLinus Torvalds * host bridge. 831da177e4SLinus Torvalds */ 841da177e4SLinus Torvalds pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); 8552378445SPeter Horton pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); 861da177e4SLinus Torvalds 871da177e4SLinus Torvalds /* 88c4ed38a0SRalf Baechle * The code described by the comment below has been removed 89c4ed38a0SRalf Baechle * as it causes bus mastering by the Ethernet controllers 90c4ed38a0SRalf Baechle * to break under any kind of network load. We always set 91c4ed38a0SRalf Baechle * the retry timeouts to their maximum. 92c4ed38a0SRalf Baechle * 93c4ed38a0SRalf Baechle * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x-- 94c4ed38a0SRalf Baechle * 951da177e4SLinus Torvalds * On all machines prior to Q2, we had the STOP line disconnected 961da177e4SLinus Torvalds * from Galileo to VIA on PCI. The new Galileo does not function 971da177e4SLinus Torvalds * correctly unless we have it connected. 981da177e4SLinus Torvalds * 991da177e4SLinus Torvalds * Therefore we must set the disconnect/retry cycle values to 1001da177e4SLinus Torvalds * something sensible when using the new Galileo. 1011da177e4SLinus Torvalds */ 102c4ed38a0SRalf Baechle 10344c10138SAuke Kok printk(KERN_INFO "Galileo: revision %u\n", dev->revision); 104c4ed38a0SRalf Baechle 105c4ed38a0SRalf Baechle #if 0 10644c10138SAuke Kok if (dev->revision >= 0x10) { 1071da177e4SLinus Torvalds /* New Galileo, assumes PCI stop line to VIA is connected. */ 10856ae5833SYoichi Yuasa GT_WRITE(GT_PCI0_TOR_OFS, 0x4020); 10944c10138SAuke Kok } else if (dev->revision == 0x1 || dev->revision == 0x2) 110c4ed38a0SRalf Baechle #endif 111c4ed38a0SRalf Baechle { 1121da177e4SLinus Torvalds signed int timeo; 1131da177e4SLinus Torvalds /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ 11456ae5833SYoichi Yuasa timeo = GT_READ(GT_PCI0_TOR_OFS); 1151da177e4SLinus Torvalds /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ 11656ae5833SYoichi Yuasa GT_WRITE(GT_PCI0_TOR_OFS, 117c4ed38a0SRalf Baechle (0xff << 16) | /* retry count */ 118c4ed38a0SRalf Baechle (0xff << 8) | /* timeout 1 */ 11956ae5833SYoichi Yuasa 0xff); /* timeout 0 */ 120c4ed38a0SRalf Baechle 121c4ed38a0SRalf Baechle /* enable PCI retry exceeded interrupt */ 12256ae5833SYoichi Yuasa GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS)); 1231da177e4SLinus Torvalds } 1241da177e4SLinus Torvalds } 1251da177e4SLinus Torvalds 126c4ed38a0SRalf Baechle DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, 1271da177e4SLinus Torvalds qube_raq_galileo_fixup); 1281da177e4SLinus Torvalds 1293f2d560eSYoichi Yuasa int cobalt_board_id; 1303f2d560eSYoichi Yuasa 13128eb0e46SGreg Kroah-Hartman static void qube_raq_via_board_id_fixup(struct pci_dev *dev) 1323f2d560eSYoichi Yuasa { 1333f2d560eSYoichi Yuasa u8 id; 1343f2d560eSYoichi Yuasa int retval; 1353f2d560eSYoichi Yuasa 1363f2d560eSYoichi Yuasa retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id); 1373f2d560eSYoichi Yuasa if (retval) { 1383f2d560eSYoichi Yuasa panic("Cannot read board ID"); 1393f2d560eSYoichi Yuasa return; 1403f2d560eSYoichi Yuasa } 1413f2d560eSYoichi Yuasa 1423f2d560eSYoichi Yuasa cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id); 1433f2d560eSYoichi Yuasa 1443f2d560eSYoichi Yuasa printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id); 1453f2d560eSYoichi Yuasa } 1463f2d560eSYoichi Yuasa 1473f2d560eSYoichi Yuasa DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, 1483f2d560eSYoichi Yuasa qube_raq_via_board_id_fixup); 1493f2d560eSYoichi Yuasa 15019a8d6b7SLorenzo Pieralisi static char irq_tab_qube1[] = { 151c4ed38a0SRalf Baechle [COBALT_PCICONF_CPU] = 0, 152d5ab1a69SYoichi Yuasa [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ, 153d5ab1a69SYoichi Yuasa [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ, 154c4ed38a0SRalf Baechle [COBALT_PCICONF_VIA] = 0, 155d5ab1a69SYoichi Yuasa [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, 156c4ed38a0SRalf Baechle [COBALT_PCICONF_ETH1] = 0 157c4ed38a0SRalf Baechle }; 158c4ed38a0SRalf Baechle 15919a8d6b7SLorenzo Pieralisi static char irq_tab_cobalt[] = { 1601da177e4SLinus Torvalds [COBALT_PCICONF_CPU] = 0, 161d5ab1a69SYoichi Yuasa [COBALT_PCICONF_ETH0] = ETH0_IRQ, 162d5ab1a69SYoichi Yuasa [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ, 1631da177e4SLinus Torvalds [COBALT_PCICONF_VIA] = 0, 164d5ab1a69SYoichi Yuasa [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, 165d5ab1a69SYoichi Yuasa [COBALT_PCICONF_ETH1] = ETH1_IRQ 1661da177e4SLinus Torvalds }; 1671da177e4SLinus Torvalds 16819a8d6b7SLorenzo Pieralisi static char irq_tab_raq2[] = { 1691da177e4SLinus Torvalds [COBALT_PCICONF_CPU] = 0, 170d5ab1a69SYoichi Yuasa [COBALT_PCICONF_ETH0] = ETH0_IRQ, 171d5ab1a69SYoichi Yuasa [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ, 1721da177e4SLinus Torvalds [COBALT_PCICONF_VIA] = 0, 173d5ab1a69SYoichi Yuasa [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, 174d5ab1a69SYoichi Yuasa [COBALT_PCICONF_ETH1] = ETH1_IRQ 1751da177e4SLinus Torvalds }; 1761da177e4SLinus Torvalds 17719a8d6b7SLorenzo Pieralisi int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 1781da177e4SLinus Torvalds { 179f6c0f32eSThomas Bogendoerfer if (cobalt_board_id <= COBALT_BRD_ID_QUBE1) 180c4ed38a0SRalf Baechle return irq_tab_qube1[slot]; 181c4ed38a0SRalf Baechle 1821da177e4SLinus Torvalds if (cobalt_board_id == COBALT_BRD_ID_RAQ2) 1831da177e4SLinus Torvalds return irq_tab_raq2[slot]; 1841da177e4SLinus Torvalds 1851da177e4SLinus Torvalds return irq_tab_cobalt[slot]; 1861da177e4SLinus Torvalds } 1871da177e4SLinus Torvalds 1881da177e4SLinus Torvalds /* Do platform specific device initialization at pci_enable_device() time */ 1891da177e4SLinus Torvalds int pcibios_plat_dev_init(struct pci_dev *dev) 1901da177e4SLinus Torvalds { 1911da177e4SLinus Torvalds return 0; 1921da177e4SLinus Torvalds } 193