1 /* 2 * Carsten Langgaard, carstenl@mips.com 3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 4 * 5 * This program is free software; you can distribute it and/or modify it 6 * under the terms of the GNU General Public License (Version 2) as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 * 18 * Setting up the clock on the MIPS boards. 19 */ 20 #include <linux/types.h> 21 #include <linux/i8253.h> 22 #include <linux/init.h> 23 #include <linux/kernel_stat.h> 24 #include <linux/sched.h> 25 #include <linux/spinlock.h> 26 #include <linux/interrupt.h> 27 #include <linux/timex.h> 28 #include <linux/mc146818rtc.h> 29 30 #include <asm/cpu.h> 31 #include <asm/mipsregs.h> 32 #include <asm/mipsmtregs.h> 33 #include <asm/hardirq.h> 34 #include <asm/irq.h> 35 #include <asm/div64.h> 36 #include <asm/setup.h> 37 #include <asm/time.h> 38 #include <asm/mc146818-time.h> 39 #include <asm/msc01_ic.h> 40 #include <asm/gic.h> 41 42 #include <asm/mips-boards/generic.h> 43 #include <asm/mips-boards/maltaint.h> 44 45 static int mips_cpu_timer_irq; 46 static int mips_cpu_perf_irq; 47 extern int cp0_perfcount_irq; 48 49 static void mips_timer_dispatch(void) 50 { 51 do_IRQ(mips_cpu_timer_irq); 52 } 53 54 static void mips_perf_dispatch(void) 55 { 56 do_IRQ(mips_cpu_perf_irq); 57 } 58 59 static unsigned int freqround(unsigned int freq, unsigned int amount) 60 { 61 freq += amount; 62 freq -= freq % (amount*2); 63 return freq; 64 } 65 66 /* 67 * Estimate CPU and GIC frequencies. 68 */ 69 static void __init estimate_frequencies(void) 70 { 71 unsigned long flags; 72 unsigned int count, start; 73 #ifdef CONFIG_IRQ_GIC 74 unsigned int giccount = 0, gicstart = 0; 75 #endif 76 77 #if defined(CONFIG_KVM_GUEST) && CONFIG_KVM_GUEST_TIMER_FREQ 78 mips_hpt_frequency = CONFIG_KVM_GUEST_TIMER_FREQ * 1000000; 79 return; 80 #endif 81 82 local_irq_save(flags); 83 84 /* Start counter exactly on falling edge of update flag. */ 85 while (CMOS_READ(RTC_REG_A) & RTC_UIP); 86 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); 87 88 /* Initialize counters. */ 89 start = read_c0_count(); 90 #ifdef CONFIG_IRQ_GIC 91 if (gic_present) 92 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart); 93 #endif 94 95 /* Read counter exactly on falling edge of update flag. */ 96 while (CMOS_READ(RTC_REG_A) & RTC_UIP); 97 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); 98 99 count = read_c0_count(); 100 #ifdef CONFIG_IRQ_GIC 101 if (gic_present) 102 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount); 103 #endif 104 105 local_irq_restore(flags); 106 107 count -= start; 108 mips_hpt_frequency = count; 109 110 #ifdef CONFIG_IRQ_GIC 111 if (gic_present) { 112 giccount -= gicstart; 113 gic_frequency = giccount; 114 } 115 #endif 116 } 117 118 void read_persistent_clock(struct timespec *ts) 119 { 120 ts->tv_sec = mc146818_get_cmos_time(); 121 ts->tv_nsec = 0; 122 } 123 124 static void __init plat_perf_setup(void) 125 { 126 #ifdef MSC01E_INT_BASE 127 if (cpu_has_veic) { 128 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); 129 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; 130 } else 131 #endif 132 if (cp0_perfcount_irq >= 0) { 133 if (cpu_has_vint) 134 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); 135 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; 136 #ifdef CONFIG_SMP 137 irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq); 138 #endif 139 } 140 } 141 142 unsigned int get_c0_compare_int(void) 143 { 144 #ifdef MSC01E_INT_BASE 145 if (cpu_has_veic) { 146 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); 147 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; 148 } else 149 #endif 150 { 151 if (cpu_has_vint) 152 set_vi_handler(cp0_compare_irq, mips_timer_dispatch); 153 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; 154 } 155 156 return mips_cpu_timer_irq; 157 } 158 159 static void __init init_rtc(void) 160 { 161 /* stop the clock whilst setting it up */ 162 CMOS_WRITE(RTC_SET | RTC_24H, RTC_CONTROL); 163 164 /* 32KHz time base */ 165 CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT); 166 167 /* start the clock */ 168 CMOS_WRITE(RTC_24H, RTC_CONTROL); 169 } 170 171 void __init plat_time_init(void) 172 { 173 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); 174 unsigned int freq; 175 176 init_rtc(); 177 estimate_frequencies(); 178 179 freq = mips_hpt_frequency; 180 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && 181 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) 182 freq *= 2; 183 freq = freqround(freq, 5000); 184 printk("CPU frequency %d.%02d MHz\n", freq/1000000, 185 (freq%1000000)*100/1000000); 186 187 mips_scroll_message(); 188 189 #ifdef CONFIG_I8253 190 /* Only Malta has a PIT. */ 191 setup_pit_timer(); 192 #endif 193 194 #ifdef CONFIG_IRQ_GIC 195 if (gic_present) { 196 freq = freqround(gic_frequency, 5000); 197 printk("GIC frequency %d.%02d MHz\n", freq/1000000, 198 (freq%1000000)*100/1000000); 199 #ifdef CONFIG_CSRC_GIC 200 gic_clocksource_init(gic_frequency); 201 #endif 202 } 203 #endif 204 205 plat_perf_setup(); 206 } 207