1 /* 2 * Carsten Langgaard, carstenl@mips.com 3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 4 * 5 * This program is free software; you can distribute it and/or modify it 6 * under the terms of the GNU General Public License (Version 2) as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 * 18 * Setting up the clock on the MIPS boards. 19 */ 20 #include <linux/types.h> 21 #include <linux/i8253.h> 22 #include <linux/init.h> 23 #include <linux/kernel_stat.h> 24 #include <linux/sched.h> 25 #include <linux/spinlock.h> 26 #include <linux/interrupt.h> 27 #include <linux/timex.h> 28 #include <linux/mc146818rtc.h> 29 30 #include <asm/cpu.h> 31 #include <asm/mipsregs.h> 32 #include <asm/mipsmtregs.h> 33 #include <asm/hardirq.h> 34 #include <asm/irq.h> 35 #include <asm/div64.h> 36 #include <asm/setup.h> 37 #include <asm/time.h> 38 #include <asm/mc146818-time.h> 39 #include <asm/msc01_ic.h> 40 #include <asm/gic.h> 41 42 #include <asm/mips-boards/generic.h> 43 #include <asm/mips-boards/maltaint.h> 44 45 unsigned long cpu_khz; 46 47 static int mips_cpu_timer_irq; 48 static int mips_cpu_perf_irq; 49 extern int cp0_perfcount_irq; 50 51 static void mips_timer_dispatch(void) 52 { 53 do_IRQ(mips_cpu_timer_irq); 54 } 55 56 static void mips_perf_dispatch(void) 57 { 58 do_IRQ(mips_cpu_perf_irq); 59 } 60 61 static unsigned int freqround(unsigned int freq, unsigned int amount) 62 { 63 freq += amount; 64 freq -= freq % (amount*2); 65 return freq; 66 } 67 68 /* 69 * Estimate CPU and GIC frequencies. 70 */ 71 static void __init estimate_frequencies(void) 72 { 73 unsigned long flags; 74 unsigned int count, start; 75 #ifdef CONFIG_IRQ_GIC 76 unsigned int giccount = 0, gicstart = 0; 77 #endif 78 79 #if defined (CONFIG_KVM_GUEST) && defined (CONFIG_KVM_HOST_FREQ) 80 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); 81 82 /* 83 * XXXKYMA: hardwire the CPU frequency to Host Freq/4 84 */ 85 count = (CONFIG_KVM_HOST_FREQ * 1000000) >> 3; 86 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && 87 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) 88 count *= 2; 89 90 mips_hpt_frequency = count; 91 return; 92 #endif 93 94 local_irq_save(flags); 95 96 /* Start counter exactly on falling edge of update flag. */ 97 while (CMOS_READ(RTC_REG_A) & RTC_UIP); 98 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); 99 100 /* Initialize counters. */ 101 start = read_c0_count(); 102 #ifdef CONFIG_IRQ_GIC 103 if (gic_present) 104 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart); 105 #endif 106 107 /* Read counter exactly on falling edge of update flag. */ 108 while (CMOS_READ(RTC_REG_A) & RTC_UIP); 109 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); 110 111 count = read_c0_count(); 112 #ifdef CONFIG_IRQ_GIC 113 if (gic_present) 114 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount); 115 #endif 116 117 local_irq_restore(flags); 118 119 count -= start; 120 mips_hpt_frequency = count; 121 122 #ifdef CONFIG_IRQ_GIC 123 if (gic_present) { 124 giccount -= gicstart; 125 gic_frequency = giccount; 126 } 127 #endif 128 } 129 130 void read_persistent_clock(struct timespec *ts) 131 { 132 ts->tv_sec = mc146818_get_cmos_time(); 133 ts->tv_nsec = 0; 134 } 135 136 static void __init plat_perf_setup(void) 137 { 138 #ifdef MSC01E_INT_BASE 139 if (cpu_has_veic) { 140 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); 141 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; 142 } else 143 #endif 144 if (cp0_perfcount_irq >= 0) { 145 if (cpu_has_vint) 146 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); 147 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; 148 #ifdef CONFIG_SMP 149 irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq); 150 #endif 151 } 152 } 153 154 unsigned int get_c0_compare_int(void) 155 { 156 #ifdef MSC01E_INT_BASE 157 if (cpu_has_veic) { 158 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); 159 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; 160 } else 161 #endif 162 { 163 if (cpu_has_vint) 164 set_vi_handler(cp0_compare_irq, mips_timer_dispatch); 165 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; 166 } 167 168 return mips_cpu_timer_irq; 169 } 170 171 void __init plat_time_init(void) 172 { 173 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); 174 unsigned int freq; 175 176 estimate_frequencies(); 177 178 freq = mips_hpt_frequency; 179 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && 180 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) 181 freq *= 2; 182 freq = freqround(freq, 5000); 183 printk("CPU frequency %d.%02d MHz\n", freq/1000000, 184 (freq%1000000)*100/1000000); 185 cpu_khz = freq / 1000; 186 187 mips_scroll_message(); 188 189 #ifdef CONFIG_I8253 190 /* Only Malta has a PIT. */ 191 setup_pit_timer(); 192 #endif 193 194 #ifdef CONFIG_IRQ_GIC 195 if (gic_present) { 196 freq = freqround(gic_frequency, 5000); 197 printk("GIC frequency %d.%02d MHz\n", freq/1000000, 198 (freq%1000000)*100/1000000); 199 #ifdef CONFIG_CSRC_GIC 200 gic_clocksource_init(gic_frequency); 201 #endif 202 } 203 #endif 204 205 plat_perf_setup(); 206 } 207