1 /* 2 * Carsten Langgaard, carstenl@mips.com 3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 4 * Copyright (C) 2008 Dmitri Vorobiev 5 * 6 * This program is free software; you can distribute it and/or modify it 7 * under the terms of the GNU General Public License (Version 2) as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, write to the Free Software Foundation, Inc., 17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 18 */ 19 #include <linux/cpu.h> 20 #include <linux/init.h> 21 #include <linux/sched.h> 22 #include <linux/ioport.h> 23 #include <linux/irq.h> 24 #include <linux/of_fdt.h> 25 #include <linux/pci.h> 26 #include <linux/screen_info.h> 27 #include <linux/time.h> 28 29 #include <asm/fw/fw.h> 30 #include <asm/mach-malta/malta-dtshim.h> 31 #include <asm/mips-cps.h> 32 #include <asm/mips-boards/generic.h> 33 #include <asm/mips-boards/malta.h> 34 #include <asm/mips-boards/maltaint.h> 35 #include <asm/dma.h> 36 #include <asm/prom.h> 37 #include <asm/traps.h> 38 #ifdef CONFIG_VT 39 #include <linux/console.h> 40 #endif 41 42 #define ROCIT_CONFIG_GEN0 0x1f403000 43 #define ROCIT_CONFIG_GEN0_PCI_IOCU BIT(7) 44 45 static struct resource standard_io_resources[] = { 46 { 47 .name = "dma1", 48 .start = 0x00, 49 .end = 0x1f, 50 .flags = IORESOURCE_BUSY 51 }, 52 { 53 .name = "timer", 54 .start = 0x40, 55 .end = 0x5f, 56 .flags = IORESOURCE_BUSY 57 }, 58 { 59 .name = "keyboard", 60 .start = 0x60, 61 .end = 0x6f, 62 .flags = IORESOURCE_BUSY 63 }, 64 { 65 .name = "dma page reg", 66 .start = 0x80, 67 .end = 0x8f, 68 .flags = IORESOURCE_BUSY 69 }, 70 { 71 .name = "dma2", 72 .start = 0xc0, 73 .end = 0xdf, 74 .flags = IORESOURCE_BUSY 75 }, 76 }; 77 78 const char *get_system_type(void) 79 { 80 return "MIPS Malta"; 81 } 82 83 const char display_string[] = " LINUX ON MALTA "; 84 85 #ifdef CONFIG_BLK_DEV_FD 86 static void __init fd_activate(void) 87 { 88 /* 89 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O 90 * Controller. 91 * Done by YAMON 2.00 onwards 92 */ 93 /* Entering config state. */ 94 SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG); 95 96 /* Activate floppy controller. */ 97 SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG); 98 SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG); 99 SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG); 100 SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG); 101 102 /* Exit config state. */ 103 SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG); 104 } 105 #endif 106 107 static int __init plat_enable_iocoherency(void) 108 { 109 int supported = 0; 110 u32 cfg; 111 112 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { 113 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { 114 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; 115 pr_info("Enabled Bonito CPU coherency\n"); 116 supported = 1; 117 } 118 if (strstr(fw_getcmdline(), "iobcuncached")) { 119 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; 120 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & 121 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 122 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 123 pr_info("Disabled Bonito IOBC coherency\n"); 124 } else { 125 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; 126 BONITO_PCIMEMBASECFG |= 127 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 128 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 129 pr_info("Enabled Bonito IOBC coherency\n"); 130 } 131 } else if (mips_cps_numiocu(0) != 0) { 132 /* Nothing special needs to be done to enable coherency */ 133 pr_info("CMP IOCU detected\n"); 134 cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0)); 135 if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) { 136 pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); 137 return 0; 138 } 139 supported = 1; 140 } 141 hw_coherentio = supported; 142 return supported; 143 } 144 145 static void __init plat_setup_iocoherency(void) 146 { 147 #ifdef CONFIG_DMA_NONCOHERENT 148 /* 149 * Kernel has been configured with software coherency 150 * but we might choose to turn it off and use hardware 151 * coherency instead. 152 */ 153 if (plat_enable_iocoherency()) { 154 if (coherentio == IO_COHERENCE_DISABLED) 155 pr_info("Hardware DMA cache coherency disabled\n"); 156 else 157 pr_info("Hardware DMA cache coherency enabled\n"); 158 } else { 159 if (coherentio == IO_COHERENCE_ENABLED) 160 pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n"); 161 else 162 pr_info("Software DMA cache coherency enabled\n"); 163 } 164 #else 165 if (!plat_enable_iocoherency()) 166 panic("Hardware DMA cache coherency not supported!"); 167 #endif 168 } 169 170 static void __init pci_clock_check(void) 171 { 172 unsigned int __iomem *jmpr_p = 173 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); 174 int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; 175 static const int pciclocks[] __initconst = { 176 33, 20, 25, 30, 12, 16, 37, 10 177 }; 178 int pciclock = pciclocks[jmpr]; 179 char *optptr, *argptr = fw_getcmdline(); 180 181 /* 182 * If user passed a pci_clock= option, don't tack on another one 183 */ 184 optptr = strstr(argptr, "pci_clock="); 185 if (optptr && (optptr == argptr || optptr[-1] == ' ')) 186 return; 187 188 if (pciclock != 33) { 189 pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n", 190 pciclock); 191 argptr += strlen(argptr); 192 sprintf(argptr, " pci_clock=%d", pciclock); 193 if (pciclock < 20 || pciclock > 66) 194 pr_warn("WARNING: IDE timing calculations will be " 195 "incorrect\n"); 196 } 197 } 198 199 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 200 static void __init screen_info_setup(void) 201 { 202 screen_info = (struct screen_info) { 203 .orig_x = 0, 204 .orig_y = 25, 205 .ext_mem_k = 0, 206 .orig_video_page = 0, 207 .orig_video_mode = 0, 208 .orig_video_cols = 80, 209 .unused2 = 0, 210 .orig_video_ega_bx = 0, 211 .unused3 = 0, 212 .orig_video_lines = 25, 213 .orig_video_isVGA = VIDEO_TYPE_VGAC, 214 .orig_video_points = 16 215 }; 216 } 217 #endif 218 219 static void __init bonito_quirks_setup(void) 220 { 221 char *argptr; 222 223 argptr = fw_getcmdline(); 224 if (strstr(argptr, "debug")) { 225 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; 226 pr_info("Enabled Bonito debug mode\n"); 227 } else 228 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; 229 230 #ifdef CONFIG_DMA_COHERENT 231 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { 232 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; 233 pr_info("Enabled Bonito CPU coherency\n"); 234 235 argptr = fw_getcmdline(); 236 if (strstr(argptr, "iobcuncached")) { 237 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; 238 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & 239 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 240 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 241 pr_info("Disabled Bonito IOBC coherency\n"); 242 } else { 243 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; 244 BONITO_PCIMEMBASECFG |= 245 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 246 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 247 pr_info("Enabled Bonito IOBC coherency\n"); 248 } 249 } else 250 panic("Hardware DMA cache coherency not supported"); 251 #endif 252 } 253 254 void __init *plat_get_fdt(void) 255 { 256 return (void *)__dtb_start; 257 } 258 259 void __init plat_mem_setup(void) 260 { 261 unsigned int i; 262 void *fdt = plat_get_fdt(); 263 264 fdt = malta_dt_shim(fdt); 265 __dt_setup_arch(fdt); 266 267 if (IS_ENABLED(CONFIG_EVA)) 268 /* EVA has already been configured in mach-malta/kernel-init.h */ 269 pr_info("Enhanced Virtual Addressing (EVA) activated\n"); 270 271 mips_pcibios_init(); 272 273 /* Request I/O space for devices used on the Malta board. */ 274 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) 275 request_resource(&ioport_resource, standard_io_resources+i); 276 277 /* 278 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge. 279 */ 280 enable_dma(4); 281 282 #ifdef CONFIG_DMA_COHERENT 283 if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO) 284 panic("Hardware DMA cache coherency not supported"); 285 #endif 286 287 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) 288 bonito_quirks_setup(); 289 290 plat_setup_iocoherency(); 291 292 pci_clock_check(); 293 294 #ifdef CONFIG_BLK_DEV_FD 295 fd_activate(); 296 #endif 297 298 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 299 screen_info_setup(); 300 #endif 301 } 302