1 /* 2 * Carsten Langgaard, carstenl@mips.com 3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 4 * Copyright (C) 2008 Dmitri Vorobiev 5 * 6 * This program is free software; you can distribute it and/or modify it 7 * under the terms of the GNU General Public License (Version 2) as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, write to the Free Software Foundation, Inc., 17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 18 */ 19 #include <linux/cpu.h> 20 #include <linux/init.h> 21 #include <linux/sched.h> 22 #include <linux/ioport.h> 23 #include <linux/irq.h> 24 #include <linux/of_fdt.h> 25 #include <linux/pci.h> 26 #include <linux/screen_info.h> 27 #include <linux/time.h> 28 29 #include <asm/dma-coherence.h> 30 #include <asm/fw/fw.h> 31 #include <asm/mach-malta/malta-dtshim.h> 32 #include <asm/mips-cps.h> 33 #include <asm/mips-boards/generic.h> 34 #include <asm/mips-boards/malta.h> 35 #include <asm/mips-boards/maltaint.h> 36 #include <asm/dma.h> 37 #include <asm/prom.h> 38 #include <asm/traps.h> 39 #ifdef CONFIG_VT 40 #include <linux/console.h> 41 #endif 42 43 #define ROCIT_CONFIG_GEN0 0x1f403000 44 #define ROCIT_CONFIG_GEN0_PCI_IOCU BIT(7) 45 46 static struct resource standard_io_resources[] = { 47 { 48 .name = "dma1", 49 .start = 0x00, 50 .end = 0x1f, 51 .flags = IORESOURCE_IO | IORESOURCE_BUSY 52 }, 53 { 54 .name = "timer", 55 .start = 0x40, 56 .end = 0x5f, 57 .flags = IORESOURCE_IO | IORESOURCE_BUSY 58 }, 59 { 60 .name = "keyboard", 61 .start = 0x60, 62 .end = 0x6f, 63 .flags = IORESOURCE_IO | IORESOURCE_BUSY 64 }, 65 { 66 .name = "dma page reg", 67 .start = 0x80, 68 .end = 0x8f, 69 .flags = IORESOURCE_IO | IORESOURCE_BUSY 70 }, 71 { 72 .name = "dma2", 73 .start = 0xc0, 74 .end = 0xdf, 75 .flags = IORESOURCE_IO | IORESOURCE_BUSY 76 }, 77 }; 78 79 const char *get_system_type(void) 80 { 81 return "MIPS Malta"; 82 } 83 84 const char display_string[] = " LINUX ON MALTA "; 85 86 #ifdef CONFIG_BLK_DEV_FD 87 static void __init fd_activate(void) 88 { 89 /* 90 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O 91 * Controller. 92 * Done by YAMON 2.00 onwards 93 */ 94 /* Entering config state. */ 95 SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG); 96 97 /* Activate floppy controller. */ 98 SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG); 99 SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG); 100 SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG); 101 SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG); 102 103 /* Exit config state. */ 104 SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG); 105 } 106 #endif 107 108 static int __init plat_enable_iocoherency(void) 109 { 110 int supported = 0; 111 u32 cfg; 112 113 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { 114 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { 115 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; 116 pr_info("Enabled Bonito CPU coherency\n"); 117 supported = 1; 118 } 119 if (strstr(fw_getcmdline(), "iobcuncached")) { 120 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; 121 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & 122 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 123 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 124 pr_info("Disabled Bonito IOBC coherency\n"); 125 } else { 126 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; 127 BONITO_PCIMEMBASECFG |= 128 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 129 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 130 pr_info("Enabled Bonito IOBC coherency\n"); 131 } 132 } else if (mips_cps_numiocu(0) != 0) { 133 /* Nothing special needs to be done to enable coherency */ 134 pr_info("CMP IOCU detected\n"); 135 cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0)); 136 if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) { 137 pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); 138 return 0; 139 } 140 supported = 1; 141 } 142 hw_coherentio = supported; 143 return supported; 144 } 145 146 static void __init plat_setup_iocoherency(void) 147 { 148 if (plat_enable_iocoherency()) { 149 if (coherentio == IO_COHERENCE_DISABLED) 150 pr_info("Hardware DMA cache coherency disabled\n"); 151 else 152 pr_info("Hardware DMA cache coherency enabled\n"); 153 } else { 154 if (coherentio == IO_COHERENCE_ENABLED) 155 pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n"); 156 else 157 pr_info("Software DMA cache coherency enabled\n"); 158 } 159 } 160 161 static void __init pci_clock_check(void) 162 { 163 unsigned int __iomem *jmpr_p = 164 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); 165 int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; 166 static const int pciclocks[] __initconst = { 167 33, 20, 25, 30, 12, 16, 37, 10 168 }; 169 int pciclock = pciclocks[jmpr]; 170 char *optptr, *argptr = fw_getcmdline(); 171 172 /* 173 * If user passed a pci_clock= option, don't tack on another one 174 */ 175 optptr = strstr(argptr, "pci_clock="); 176 if (optptr && (optptr == argptr || optptr[-1] == ' ')) 177 return; 178 179 if (pciclock != 33) { 180 pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n", 181 pciclock); 182 argptr += strlen(argptr); 183 sprintf(argptr, " pci_clock=%d", pciclock); 184 if (pciclock < 20 || pciclock > 66) 185 pr_warn("WARNING: IDE timing calculations will be " 186 "incorrect\n"); 187 } 188 } 189 190 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 191 static void __init screen_info_setup(void) 192 { 193 screen_info = (struct screen_info) { 194 .orig_x = 0, 195 .orig_y = 25, 196 .ext_mem_k = 0, 197 .orig_video_page = 0, 198 .orig_video_mode = 0, 199 .orig_video_cols = 80, 200 .unused2 = 0, 201 .orig_video_ega_bx = 0, 202 .unused3 = 0, 203 .orig_video_lines = 25, 204 .orig_video_isVGA = VIDEO_TYPE_VGAC, 205 .orig_video_points = 16 206 }; 207 } 208 #endif 209 210 static void __init bonito_quirks_setup(void) 211 { 212 char *argptr; 213 214 argptr = fw_getcmdline(); 215 if (strstr(argptr, "debug")) { 216 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; 217 pr_info("Enabled Bonito debug mode\n"); 218 } else 219 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; 220 } 221 222 void __init *plat_get_fdt(void) 223 { 224 return (void *)__dtb_start; 225 } 226 227 void __init plat_mem_setup(void) 228 { 229 unsigned int i; 230 void *fdt = plat_get_fdt(); 231 232 fdt = malta_dt_shim(fdt); 233 __dt_setup_arch(fdt); 234 235 if (IS_ENABLED(CONFIG_EVA)) 236 /* EVA has already been configured in mach-malta/kernel-init.h */ 237 pr_info("Enhanced Virtual Addressing (EVA) activated\n"); 238 239 mips_pcibios_init(); 240 241 /* Request I/O space for devices used on the Malta board. */ 242 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) 243 request_resource(&ioport_resource, standard_io_resources+i); 244 245 /* 246 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge. 247 */ 248 enable_dma(4); 249 250 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) 251 bonito_quirks_setup(); 252 253 plat_setup_iocoherency(); 254 255 pci_clock_check(); 256 257 #ifdef CONFIG_BLK_DEV_FD 258 fd_activate(); 259 #endif 260 261 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 262 screen_info_setup(); 263 #endif 264 } 265