1 /* 2 * Carsten Langgaard, carstenl@mips.com 3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 4 * Copyright (C) 2008 Dmitri Vorobiev 5 * 6 * This program is free software; you can distribute it and/or modify it 7 * under the terms of the GNU General Public License (Version 2) as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, write to the Free Software Foundation, Inc., 17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 18 */ 19 #include <linux/cpu.h> 20 #include <linux/init.h> 21 #include <linux/sched.h> 22 #include <linux/ioport.h> 23 #include <linux/irq.h> 24 #include <linux/of_fdt.h> 25 #include <linux/pci.h> 26 #include <linux/screen_info.h> 27 #include <linux/time.h> 28 29 #include <asm/dma-coherence.h> 30 #include <asm/fw/fw.h> 31 #include <asm/mach-malta/malta-dtshim.h> 32 #include <asm/mips-cps.h> 33 #include <asm/mips-boards/generic.h> 34 #include <asm/mips-boards/malta.h> 35 #include <asm/mips-boards/maltaint.h> 36 #include <asm/dma.h> 37 #include <asm/prom.h> 38 #include <asm/traps.h> 39 #ifdef CONFIG_VT 40 #include <linux/console.h> 41 #endif 42 43 #define ROCIT_CONFIG_GEN0 0x1f403000 44 #define ROCIT_CONFIG_GEN0_PCI_IOCU BIT(7) 45 46 static struct resource standard_io_resources[] = { 47 { 48 .name = "dma1", 49 .start = 0x00, 50 .end = 0x1f, 51 .flags = IORESOURCE_IO | IORESOURCE_BUSY 52 }, 53 { 54 .name = "timer", 55 .start = 0x40, 56 .end = 0x5f, 57 .flags = IORESOURCE_IO | IORESOURCE_BUSY 58 }, 59 { 60 .name = "keyboard", 61 .start = 0x60, 62 .end = 0x6f, 63 .flags = IORESOURCE_IO | IORESOURCE_BUSY 64 }, 65 { 66 .name = "dma page reg", 67 .start = 0x80, 68 .end = 0x8f, 69 .flags = IORESOURCE_IO | IORESOURCE_BUSY 70 }, 71 { 72 .name = "dma2", 73 .start = 0xc0, 74 .end = 0xdf, 75 .flags = IORESOURCE_IO | IORESOURCE_BUSY 76 }, 77 }; 78 79 const char *get_system_type(void) 80 { 81 return "MIPS Malta"; 82 } 83 84 #ifdef CONFIG_BLK_DEV_FD 85 static void __init fd_activate(void) 86 { 87 /* 88 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O 89 * Controller. 90 * Done by YAMON 2.00 onwards 91 */ 92 /* Entering config state. */ 93 SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG); 94 95 /* Activate floppy controller. */ 96 SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG); 97 SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG); 98 SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG); 99 SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG); 100 101 /* Exit config state. */ 102 SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG); 103 } 104 #endif 105 106 static int __init plat_enable_iocoherency(void) 107 { 108 int supported = 0; 109 u32 cfg; 110 111 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { 112 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { 113 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; 114 pr_info("Enabled Bonito CPU coherency\n"); 115 supported = 1; 116 } 117 if (strstr(fw_getcmdline(), "iobcuncached")) { 118 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; 119 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & 120 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 121 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 122 pr_info("Disabled Bonito IOBC coherency\n"); 123 } else { 124 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; 125 BONITO_PCIMEMBASECFG |= 126 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 127 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 128 pr_info("Enabled Bonito IOBC coherency\n"); 129 } 130 } else if (mips_cps_numiocu(0) != 0) { 131 /* Nothing special needs to be done to enable coherency */ 132 pr_info("CMP IOCU detected\n"); 133 cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0)); 134 if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) { 135 pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); 136 return 0; 137 } 138 supported = 1; 139 } 140 hw_coherentio = supported; 141 return supported; 142 } 143 144 static void __init plat_setup_iocoherency(void) 145 { 146 if (plat_enable_iocoherency()) { 147 if (coherentio == IO_COHERENCE_DISABLED) 148 pr_info("Hardware DMA cache coherency disabled\n"); 149 else 150 pr_info("Hardware DMA cache coherency enabled\n"); 151 } else { 152 if (coherentio == IO_COHERENCE_ENABLED) 153 pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n"); 154 else 155 pr_info("Software DMA cache coherency enabled\n"); 156 } 157 } 158 159 static void __init pci_clock_check(void) 160 { 161 unsigned int __iomem *jmpr_p = 162 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); 163 int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; 164 static const int pciclocks[] __initconst = { 165 33, 20, 25, 30, 12, 16, 37, 10 166 }; 167 int pciclock = pciclocks[jmpr]; 168 char *optptr, *argptr = fw_getcmdline(); 169 170 /* 171 * If user passed a pci_clock= option, don't tack on another one 172 */ 173 optptr = strstr(argptr, "pci_clock="); 174 if (optptr && (optptr == argptr || optptr[-1] == ' ')) 175 return; 176 177 if (pciclock != 33) { 178 pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n", 179 pciclock); 180 argptr += strlen(argptr); 181 sprintf(argptr, " pci_clock=%d", pciclock); 182 if (pciclock < 20 || pciclock > 66) 183 pr_warn("WARNING: IDE timing calculations will be " 184 "incorrect\n"); 185 } 186 } 187 188 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 189 static void __init screen_info_setup(void) 190 { 191 screen_info = (struct screen_info) { 192 .orig_x = 0, 193 .orig_y = 25, 194 .ext_mem_k = 0, 195 .orig_video_page = 0, 196 .orig_video_mode = 0, 197 .orig_video_cols = 80, 198 .unused2 = 0, 199 .orig_video_ega_bx = 0, 200 .unused3 = 0, 201 .orig_video_lines = 25, 202 .orig_video_isVGA = VIDEO_TYPE_VGAC, 203 .orig_video_points = 16 204 }; 205 } 206 #endif 207 208 static void __init bonito_quirks_setup(void) 209 { 210 char *argptr; 211 212 argptr = fw_getcmdline(); 213 if (strstr(argptr, "debug")) { 214 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; 215 pr_info("Enabled Bonito debug mode\n"); 216 } else 217 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; 218 } 219 220 void __init *plat_get_fdt(void) 221 { 222 return (void *)__dtb_start; 223 } 224 225 void __init plat_mem_setup(void) 226 { 227 unsigned int i; 228 void *fdt = plat_get_fdt(); 229 230 fdt = malta_dt_shim(fdt); 231 __dt_setup_arch(fdt); 232 233 if (IS_ENABLED(CONFIG_EVA)) 234 /* EVA has already been configured in mach-malta/kernel-init.h */ 235 pr_info("Enhanced Virtual Addressing (EVA) activated\n"); 236 237 mips_pcibios_init(); 238 239 /* Request I/O space for devices used on the Malta board. */ 240 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) 241 request_resource(&ioport_resource, standard_io_resources+i); 242 243 /* 244 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge. 245 */ 246 enable_dma(4); 247 248 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) 249 bonito_quirks_setup(); 250 251 plat_setup_iocoherency(); 252 253 pci_clock_check(); 254 255 #ifdef CONFIG_BLK_DEV_FD 256 fd_activate(); 257 #endif 258 259 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 260 screen_info_setup(); 261 #endif 262 } 263