1 /* 2 * Carsten Langgaard, carstenl@mips.com 3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. 4 * Copyright (C) 2001 Ralf Baechle 5 * 6 * This program is free software; you can distribute it and/or modify it 7 * under the terms of the GNU General Public License (Version 2) as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, write to the Free Software Foundation, Inc., 17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 18 * 19 * Routines for generic manipulation of the interrupts found on the MIPS 20 * Malta board. 21 * The interrupt controller is located in the South Bridge a PIIX4 device 22 * with two internal 82C95 interrupt controllers. 23 */ 24 #include <linux/init.h> 25 #include <linux/irq.h> 26 #include <linux/sched.h> 27 #include <linux/smp.h> 28 #include <linux/interrupt.h> 29 #include <linux/io.h> 30 #include <linux/kernel_stat.h> 31 #include <linux/kernel.h> 32 #include <linux/random.h> 33 34 #include <asm/traps.h> 35 #include <asm/i8259.h> 36 #include <asm/irq_cpu.h> 37 #include <asm/irq_regs.h> 38 #include <asm/mips-boards/malta.h> 39 #include <asm/mips-boards/maltaint.h> 40 #include <asm/mips-boards/piix4.h> 41 #include <asm/gt64120.h> 42 #include <asm/mips-boards/generic.h> 43 #include <asm/mips-boards/msc01_pci.h> 44 #include <asm/msc01_ic.h> 45 #include <asm/gic.h> 46 #include <asm/gcmpregs.h> 47 #include <asm/setup.h> 48 49 int gcmp_present = -1; 50 static unsigned long _msc01_biu_base; 51 static unsigned long _gcmp_base; 52 static unsigned int ipi_map[NR_CPUS]; 53 54 static DEFINE_RAW_SPINLOCK(mips_irq_lock); 55 56 static inline int mips_pcibios_iack(void) 57 { 58 int irq; 59 60 /* 61 * Determine highest priority pending interrupt by performing 62 * a PCI Interrupt Acknowledge cycle. 63 */ 64 switch (mips_revision_sconid) { 65 case MIPS_REVISION_SCON_SOCIT: 66 case MIPS_REVISION_SCON_ROCIT: 67 case MIPS_REVISION_SCON_SOCITSC: 68 case MIPS_REVISION_SCON_SOCITSCP: 69 MSC_READ(MSC01_PCI_IACK, irq); 70 irq &= 0xff; 71 break; 72 case MIPS_REVISION_SCON_GT64120: 73 irq = GT_READ(GT_PCI0_IACK_OFS); 74 irq &= 0xff; 75 break; 76 case MIPS_REVISION_SCON_BONITO: 77 /* The following will generate a PCI IACK cycle on the 78 * Bonito controller. It's a little bit kludgy, but it 79 * was the easiest way to implement it in hardware at 80 * the given time. 81 */ 82 BONITO_PCIMAP_CFG = 0x20000; 83 84 /* Flush Bonito register block */ 85 (void) BONITO_PCIMAP_CFG; 86 iob(); /* sync */ 87 88 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg); 89 iob(); /* sync */ 90 irq &= 0xff; 91 BONITO_PCIMAP_CFG = 0; 92 break; 93 default: 94 printk(KERN_WARNING "Unknown system controller.\n"); 95 return -1; 96 } 97 return irq; 98 } 99 100 static inline int get_int(void) 101 { 102 unsigned long flags; 103 int irq; 104 raw_spin_lock_irqsave(&mips_irq_lock, flags); 105 106 irq = mips_pcibios_iack(); 107 108 /* 109 * The only way we can decide if an interrupt is spurious 110 * is by checking the 8259 registers. This needs a spinlock 111 * on an SMP system, so leave it up to the generic code... 112 */ 113 114 raw_spin_unlock_irqrestore(&mips_irq_lock, flags); 115 116 return irq; 117 } 118 119 static void malta_hw0_irqdispatch(void) 120 { 121 int irq; 122 123 irq = get_int(); 124 if (irq < 0) { 125 /* interrupt has already been cleared */ 126 return; 127 } 128 129 do_IRQ(MALTA_INT_BASE + irq); 130 } 131 132 static void malta_ipi_irqdispatch(void) 133 { 134 int irq; 135 136 if (gic_compare_int()) 137 do_IRQ(MIPS_GIC_IRQ_BASE); 138 139 irq = gic_get_int(); 140 if (irq < 0) 141 return; /* interrupt has already been cleared */ 142 143 do_IRQ(MIPS_GIC_IRQ_BASE + irq); 144 } 145 146 static void corehi_irqdispatch(void) 147 { 148 unsigned int intedge, intsteer, pcicmd, pcibadaddr; 149 unsigned int pcimstat, intisr, inten, intpol; 150 unsigned int intrcause, datalo, datahi; 151 struct pt_regs *regs = get_irq_regs(); 152 153 printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n"); 154 printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n" 155 "Cause : %08lx\nbadVaddr : %08lx\n", 156 regs->cp0_epc, regs->cp0_status, 157 regs->cp0_cause, regs->cp0_badvaddr); 158 159 /* Read all the registers and then print them as there is a 160 problem with interspersed printk's upsetting the Bonito controller. 161 Do it for the others too. 162 */ 163 164 switch (mips_revision_sconid) { 165 case MIPS_REVISION_SCON_SOCIT: 166 case MIPS_REVISION_SCON_ROCIT: 167 case MIPS_REVISION_SCON_SOCITSC: 168 case MIPS_REVISION_SCON_SOCITSCP: 169 ll_msc_irq(); 170 break; 171 case MIPS_REVISION_SCON_GT64120: 172 intrcause = GT_READ(GT_INTRCAUSE_OFS); 173 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); 174 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); 175 printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause); 176 printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n", 177 datahi, datalo); 178 break; 179 case MIPS_REVISION_SCON_BONITO: 180 pcibadaddr = BONITO_PCIBADADDR; 181 pcimstat = BONITO_PCIMSTAT; 182 intisr = BONITO_INTISR; 183 inten = BONITO_INTEN; 184 intpol = BONITO_INTPOL; 185 intedge = BONITO_INTEDGE; 186 intsteer = BONITO_INTSTEER; 187 pcicmd = BONITO_PCICMD; 188 printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr); 189 printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten); 190 printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol); 191 printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge); 192 printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer); 193 printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd); 194 printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr); 195 printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat); 196 break; 197 } 198 199 die("CoreHi interrupt", regs); 200 } 201 202 static inline int clz(unsigned long x) 203 { 204 __asm__( 205 " .set push \n" 206 " .set mips32 \n" 207 " clz %0, %1 \n" 208 " .set pop \n" 209 : "=r" (x) 210 : "r" (x)); 211 212 return x; 213 } 214 215 /* 216 * Version of ffs that only looks at bits 12..15. 217 */ 218 static inline unsigned int irq_ffs(unsigned int pending) 219 { 220 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 221 return -clz(pending) + 31 - CAUSEB_IP; 222 #else 223 unsigned int a0 = 7; 224 unsigned int t0; 225 226 t0 = pending & 0xf000; 227 t0 = t0 < 1; 228 t0 = t0 << 2; 229 a0 = a0 - t0; 230 pending = pending << t0; 231 232 t0 = pending & 0xc000; 233 t0 = t0 < 1; 234 t0 = t0 << 1; 235 a0 = a0 - t0; 236 pending = pending << t0; 237 238 t0 = pending & 0x8000; 239 t0 = t0 < 1; 240 /* t0 = t0 << 2; */ 241 a0 = a0 - t0; 242 /* pending = pending << t0; */ 243 244 return a0; 245 #endif 246 } 247 248 /* 249 * IRQs on the Malta board look basically (barring software IRQs which we 250 * don't use at all and all external interrupt sources are combined together 251 * on hardware interrupt 0 (MIPS IRQ 2)) like: 252 * 253 * MIPS IRQ Source 254 * -------- ------ 255 * 0 Software (ignored) 256 * 1 Software (ignored) 257 * 2 Combined hardware interrupt (hw0) 258 * 3 Hardware (ignored) 259 * 4 Hardware (ignored) 260 * 5 Hardware (ignored) 261 * 6 Hardware (ignored) 262 * 7 R4k timer (what we use) 263 * 264 * We handle the IRQ according to _our_ priority which is: 265 * 266 * Highest ---- R4k Timer 267 * Lowest ---- Combined hardware interrupt 268 * 269 * then we just return, if multiple IRQs are pending then we will just take 270 * another exception, big deal. 271 */ 272 273 asmlinkage void plat_irq_dispatch(void) 274 { 275 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 276 int irq; 277 278 if (unlikely(!pending)) { 279 spurious_interrupt(); 280 return; 281 } 282 283 irq = irq_ffs(pending); 284 285 if (irq == MIPSCPU_INT_I8259A) 286 malta_hw0_irqdispatch(); 287 else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()])) 288 malta_ipi_irqdispatch(); 289 else 290 do_IRQ(MIPS_CPU_IRQ_BASE + irq); 291 } 292 293 #ifdef CONFIG_MIPS_MT_SMP 294 295 296 #define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3 297 #define GIC_MIPS_CPU_IPI_CALL_IRQ 4 298 299 #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ 300 #define C_RESCHED C_SW0 301 #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */ 302 #define C_CALL C_SW1 303 static int cpu_ipi_resched_irq, cpu_ipi_call_irq; 304 305 static void ipi_resched_dispatch(void) 306 { 307 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); 308 } 309 310 static void ipi_call_dispatch(void) 311 { 312 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); 313 } 314 315 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) 316 { 317 scheduler_ipi(); 318 319 return IRQ_HANDLED; 320 } 321 322 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) 323 { 324 smp_call_function_interrupt(); 325 326 return IRQ_HANDLED; 327 } 328 329 static struct irqaction irq_resched = { 330 .handler = ipi_resched_interrupt, 331 .flags = IRQF_PERCPU, 332 .name = "IPI_resched" 333 }; 334 335 static struct irqaction irq_call = { 336 .handler = ipi_call_interrupt, 337 .flags = IRQF_PERCPU, 338 .name = "IPI_call" 339 }; 340 #endif /* CONFIG_MIPS_MT_SMP */ 341 342 static int gic_resched_int_base; 343 static int gic_call_int_base; 344 #define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu)) 345 #define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu)) 346 347 unsigned int plat_ipi_call_int_xlate(unsigned int cpu) 348 { 349 return GIC_CALL_INT(cpu); 350 } 351 352 unsigned int plat_ipi_resched_int_xlate(unsigned int cpu) 353 { 354 return GIC_RESCHED_INT(cpu); 355 } 356 357 static struct irqaction i8259irq = { 358 .handler = no_action, 359 .name = "XT-PIC cascade", 360 .flags = IRQF_NO_THREAD, 361 }; 362 363 static struct irqaction corehi_irqaction = { 364 .handler = no_action, 365 .name = "CoreHi", 366 .flags = IRQF_NO_THREAD, 367 }; 368 369 static msc_irqmap_t __initdata msc_irqmap[] = { 370 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, 371 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, 372 }; 373 static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap); 374 375 static msc_irqmap_t __initdata msc_eicirqmap[] = { 376 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, 377 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, 378 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, 379 {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0}, 380 {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0}, 381 {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0}, 382 {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, 383 {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, 384 {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, 385 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} 386 }; 387 388 static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); 389 390 /* 391 * This GIC specific tabular array defines the association between External 392 * Interrupts and CPUs/Core Interrupts. The nature of the External 393 * Interrupts is also defined here - polarity/trigger. 394 */ 395 396 #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK 397 #define X GIC_UNUSED 398 399 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { 400 { X, X, X, X, 0 }, 401 { X, X, X, X, 0 }, 402 { X, X, X, X, 0 }, 403 { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 404 { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 405 { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 406 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 407 { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 408 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 409 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 410 { X, X, X, X, 0 }, 411 { X, X, X, X, 0 }, 412 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 413 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 414 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 415 { X, X, X, X, 0 }, 416 /* The remainder of this table is initialised by fill_ipi_map */ 417 }; 418 #undef X 419 420 /* 421 * GCMP needs to be detected before any SMP initialisation 422 */ 423 int __init gcmp_probe(unsigned long addr, unsigned long size) 424 { 425 if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) { 426 gcmp_present = 0; 427 return gcmp_present; 428 } 429 430 if (gcmp_present >= 0) 431 return gcmp_present; 432 433 _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); 434 _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); 435 gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; 436 437 if (gcmp_present) 438 pr_debug("GCMP present\n"); 439 return gcmp_present; 440 } 441 442 /* Return the number of IOCU's present */ 443 int __init gcmp_niocu(void) 444 { 445 return gcmp_present ? 446 (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF : 447 0; 448 } 449 450 /* Set GCMP region attributes */ 451 void __init gcmp_setregion(int region, unsigned long base, 452 unsigned long mask, int type) 453 { 454 GCMPGCBn(CMxBASE, region) = base; 455 GCMPGCBn(CMxMASK, region) = mask | type; 456 } 457 458 #if defined(CONFIG_MIPS_MT_SMP) 459 static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) 460 { 461 int intr = baseintr + cpu; 462 gic_intr_map[intr].cpunum = cpu; 463 gic_intr_map[intr].pin = cpupin; 464 gic_intr_map[intr].polarity = GIC_POL_POS; 465 gic_intr_map[intr].trigtype = GIC_TRIG_EDGE; 466 gic_intr_map[intr].flags = GIC_FLAG_IPI; 467 ipi_map[cpu] |= (1 << (cpupin + 2)); 468 } 469 470 static void __init fill_ipi_map(void) 471 { 472 int cpu; 473 474 for (cpu = 0; cpu < NR_CPUS; cpu++) { 475 fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1); 476 fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2); 477 } 478 } 479 #endif 480 481 void __init arch_init_ipiirq(int irq, struct irqaction *action) 482 { 483 setup_irq(irq, action); 484 irq_set_handler(irq, handle_percpu_irq); 485 } 486 487 void __init arch_init_irq(void) 488 { 489 init_i8259_irqs(); 490 491 if (!cpu_has_veic) 492 mips_cpu_irq_init(); 493 494 if (gcmp_present) { 495 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; 496 gic_present = 1; 497 } else { 498 if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { 499 _msc01_biu_base = (unsigned long) 500 ioremap_nocache(MSC01_BIU_REG_BASE, 501 MSC01_BIU_ADDRSPACE_SZ); 502 gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & 503 MSC01_SC_CFG_GICPRES_MSK) >> 504 MSC01_SC_CFG_GICPRES_SHF; 505 } 506 } 507 if (gic_present) 508 pr_debug("GIC present\n"); 509 510 switch (mips_revision_sconid) { 511 case MIPS_REVISION_SCON_SOCIT: 512 case MIPS_REVISION_SCON_ROCIT: 513 if (cpu_has_veic) 514 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, 515 MSC01E_INT_BASE, msc_eicirqmap, 516 msc_nr_eicirqs); 517 else 518 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, 519 MSC01C_INT_BASE, msc_irqmap, 520 msc_nr_irqs); 521 break; 522 523 case MIPS_REVISION_SCON_SOCITSC: 524 case MIPS_REVISION_SCON_SOCITSCP: 525 if (cpu_has_veic) 526 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, 527 MSC01E_INT_BASE, msc_eicirqmap, 528 msc_nr_eicirqs); 529 else 530 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, 531 MSC01C_INT_BASE, msc_irqmap, 532 msc_nr_irqs); 533 } 534 535 if (cpu_has_veic) { 536 set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch); 537 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); 538 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); 539 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); 540 } else if (cpu_has_vint) { 541 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); 542 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch); 543 #ifdef CONFIG_MIPS_MT_SMTC 544 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, 545 (0x100 << MIPSCPU_INT_I8259A)); 546 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 547 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); 548 /* 549 * Temporary hack to ensure that the subsidiary device 550 * interrupts coing in via the i8259A, but associated 551 * with low IRQ numbers, will restore the Status.IM 552 * value associated with the i8259A. 553 */ 554 { 555 int i; 556 557 for (i = 0; i < 16; i++) 558 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); 559 } 560 #else /* Not SMTC */ 561 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 562 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 563 &corehi_irqaction); 564 #endif /* CONFIG_MIPS_MT_SMTC */ 565 } else { 566 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 567 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 568 &corehi_irqaction); 569 } 570 571 if (gic_present) { 572 /* FIXME */ 573 int i; 574 #if defined(CONFIG_MIPS_MT_SMP) 575 gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; 576 gic_resched_int_base = gic_call_int_base - NR_CPUS; 577 fill_ipi_map(); 578 #endif 579 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, 580 ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); 581 if (!gcmp_present) { 582 /* Enable the GIC */ 583 i = REG(_msc01_biu_base, MSC01_SC_CFG); 584 REG(_msc01_biu_base, MSC01_SC_CFG) = 585 (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); 586 pr_debug("GIC Enabled\n"); 587 } 588 #if defined(CONFIG_MIPS_MT_SMP) 589 /* set up ipi interrupts */ 590 if (cpu_has_vint) { 591 set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); 592 set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch); 593 } 594 /* Argh.. this really needs sorting out.. */ 595 printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status()); 596 write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4); 597 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status()); 598 write_c0_status(0x1100dc00); 599 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); 600 for (i = 0; i < NR_CPUS; i++) { 601 arch_init_ipiirq(MIPS_GIC_IRQ_BASE + 602 GIC_RESCHED_INT(i), &irq_resched); 603 arch_init_ipiirq(MIPS_GIC_IRQ_BASE + 604 GIC_CALL_INT(i), &irq_call); 605 } 606 #endif 607 } else { 608 #if defined(CONFIG_MIPS_MT_SMP) 609 /* set up ipi interrupts */ 610 if (cpu_has_veic) { 611 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); 612 set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch); 613 cpu_ipi_resched_irq = MSC01E_INT_SW0; 614 cpu_ipi_call_irq = MSC01E_INT_SW1; 615 } else { 616 if (cpu_has_vint) { 617 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); 618 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); 619 } 620 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; 621 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; 622 } 623 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); 624 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); 625 #endif 626 } 627 } 628 629 void malta_be_init(void) 630 { 631 if (gcmp_present) { 632 /* Could change CM error mask register */ 633 } 634 } 635 636 637 static char *tr[8] = { 638 "mem", "gcr", "gic", "mmio", 639 "0x04", "0x05", "0x06", "0x07" 640 }; 641 642 static char *mcmd[32] = { 643 [0x00] = "0x00", 644 [0x01] = "Legacy Write", 645 [0x02] = "Legacy Read", 646 [0x03] = "0x03", 647 [0x04] = "0x04", 648 [0x05] = "0x05", 649 [0x06] = "0x06", 650 [0x07] = "0x07", 651 [0x08] = "Coherent Read Own", 652 [0x09] = "Coherent Read Share", 653 [0x0a] = "Coherent Read Discard", 654 [0x0b] = "Coherent Ready Share Always", 655 [0x0c] = "Coherent Upgrade", 656 [0x0d] = "Coherent Writeback", 657 [0x0e] = "0x0e", 658 [0x0f] = "0x0f", 659 [0x10] = "Coherent Copyback", 660 [0x11] = "Coherent Copyback Invalidate", 661 [0x12] = "Coherent Invalidate", 662 [0x13] = "Coherent Write Invalidate", 663 [0x14] = "Coherent Completion Sync", 664 [0x15] = "0x15", 665 [0x16] = "0x16", 666 [0x17] = "0x17", 667 [0x18] = "0x18", 668 [0x19] = "0x19", 669 [0x1a] = "0x1a", 670 [0x1b] = "0x1b", 671 [0x1c] = "0x1c", 672 [0x1d] = "0x1d", 673 [0x1e] = "0x1e", 674 [0x1f] = "0x1f" 675 }; 676 677 static char *core[8] = { 678 "Invalid/OK", "Invalid/Data", 679 "Shared/OK", "Shared/Data", 680 "Modified/OK", "Modified/Data", 681 "Exclusive/OK", "Exclusive/Data" 682 }; 683 684 static char *causes[32] = { 685 "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR", 686 "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07", 687 "0x08", "0x09", "0x0a", "0x0b", 688 "0x0c", "0x0d", "0x0e", "0x0f", 689 "0x10", "0x11", "0x12", "0x13", 690 "0x14", "0x15", "0x16", "INTVN_WR_ERR", 691 "INTVN_RD_ERR", "0x19", "0x1a", "0x1b", 692 "0x1c", "0x1d", "0x1e", "0x1f" 693 }; 694 695 int malta_be_handler(struct pt_regs *regs, int is_fixup) 696 { 697 /* This duplicates the handling in do_be which seems wrong */ 698 int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL; 699 700 if (gcmp_present) { 701 unsigned long cm_error = GCMPGCB(GCMEC); 702 unsigned long cm_addr = GCMPGCB(GCMEA); 703 unsigned long cm_other = GCMPGCB(GCMEO); 704 unsigned long cause, ocause; 705 char buf[256]; 706 707 cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK); 708 if (cause != 0) { 709 cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF; 710 if (cause < 16) { 711 unsigned long cca_bits = (cm_error >> 15) & 7; 712 unsigned long tr_bits = (cm_error >> 12) & 7; 713 unsigned long mcmd_bits = (cm_error >> 7) & 0x1f; 714 unsigned long stag_bits = (cm_error >> 3) & 15; 715 unsigned long sport_bits = (cm_error >> 0) & 7; 716 717 snprintf(buf, sizeof(buf), 718 "CCA=%lu TR=%s MCmd=%s STag=%lu " 719 "SPort=%lu\n", 720 cca_bits, tr[tr_bits], mcmd[mcmd_bits], 721 stag_bits, sport_bits); 722 } else { 723 /* glob state & sresp together */ 724 unsigned long c3_bits = (cm_error >> 18) & 7; 725 unsigned long c2_bits = (cm_error >> 15) & 7; 726 unsigned long c1_bits = (cm_error >> 12) & 7; 727 unsigned long c0_bits = (cm_error >> 9) & 7; 728 unsigned long sc_bit = (cm_error >> 8) & 1; 729 unsigned long mcmd_bits = (cm_error >> 3) & 0x1f; 730 unsigned long sport_bits = (cm_error >> 0) & 7; 731 snprintf(buf, sizeof(buf), 732 "C3=%s C2=%s C1=%s C0=%s SC=%s " 733 "MCmd=%s SPort=%lu\n", 734 core[c3_bits], core[c2_bits], 735 core[c1_bits], core[c0_bits], 736 sc_bit ? "True" : "False", 737 mcmd[mcmd_bits], sport_bits); 738 } 739 740 ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >> 741 GCMP_GCB_GMEO_ERROR_2ND_SHF; 742 743 printk("CM_ERROR=%08lx %s <%s>\n", cm_error, 744 causes[cause], buf); 745 printk("CM_ADDR =%08lx\n", cm_addr); 746 printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]); 747 748 /* reprime cause register */ 749 GCMPGCB(GCMEC) = 0; 750 } 751 } 752 753 return retval; 754 } 755 756 void gic_enable_interrupt(int irq_vec) 757 { 758 GIC_SET_INTR_MASK(irq_vec); 759 } 760 761 void gic_disable_interrupt(int irq_vec) 762 { 763 GIC_CLR_INTR_MASK(irq_vec); 764 } 765 766 void gic_irq_ack(struct irq_data *d) 767 { 768 int irq = (d->irq - gic_irq_base); 769 770 GIC_CLR_INTR_MASK(irq); 771 772 if (gic_irq_flags[irq] & GIC_TRIG_EDGE) 773 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); 774 } 775 776 void gic_finish_irq(struct irq_data *d) 777 { 778 /* Enable interrupts. */ 779 GIC_SET_INTR_MASK(d->irq - gic_irq_base); 780 } 781 782 void __init gic_platform_init(int irqs, struct irq_chip *irq_controller) 783 { 784 int i; 785 786 for (i = gic_irq_base; i < (gic_irq_base + irqs); i++) 787 irq_set_chip(i, irq_controller); 788 } 789