1 /* 2 * Carsten Langgaard, carstenl@mips.com 3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. 4 * Copyright (C) 2001 Ralf Baechle 5 * 6 * This program is free software; you can distribute it and/or modify it 7 * under the terms of the GNU General Public License (Version 2) as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, write to the Free Software Foundation, Inc., 17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 18 * 19 * Routines for generic manipulation of the interrupts found on the MIPS 20 * Malta board. 21 * The interrupt controller is located in the South Bridge a PIIX4 device 22 * with two internal 82C95 interrupt controllers. 23 */ 24 #include <linux/init.h> 25 #include <linux/irq.h> 26 #include <linux/sched.h> 27 #include <linux/smp.h> 28 #include <linux/slab.h> 29 #include <linux/interrupt.h> 30 #include <linux/io.h> 31 #include <linux/kernel_stat.h> 32 #include <linux/kernel.h> 33 #include <linux/random.h> 34 35 #include <asm/traps.h> 36 #include <asm/i8259.h> 37 #include <asm/irq_cpu.h> 38 #include <asm/irq_regs.h> 39 #include <asm/mips-boards/malta.h> 40 #include <asm/mips-boards/maltaint.h> 41 #include <asm/mips-boards/piix4.h> 42 #include <asm/gt64120.h> 43 #include <asm/mips-boards/generic.h> 44 #include <asm/mips-boards/msc01_pci.h> 45 #include <asm/msc01_ic.h> 46 #include <asm/gic.h> 47 #include <asm/gcmpregs.h> 48 49 int gcmp_present = -1; 50 int gic_present; 51 static unsigned long _msc01_biu_base; 52 static unsigned long _gcmp_base; 53 static unsigned int ipi_map[NR_CPUS]; 54 55 static DEFINE_SPINLOCK(mips_irq_lock); 56 57 static inline int mips_pcibios_iack(void) 58 { 59 int irq; 60 u32 dummy; 61 62 /* 63 * Determine highest priority pending interrupt by performing 64 * a PCI Interrupt Acknowledge cycle. 65 */ 66 switch (mips_revision_sconid) { 67 case MIPS_REVISION_SCON_SOCIT: 68 case MIPS_REVISION_SCON_ROCIT: 69 case MIPS_REVISION_SCON_SOCITSC: 70 case MIPS_REVISION_SCON_SOCITSCP: 71 MSC_READ(MSC01_PCI_IACK, irq); 72 irq &= 0xff; 73 break; 74 case MIPS_REVISION_SCON_GT64120: 75 irq = GT_READ(GT_PCI0_IACK_OFS); 76 irq &= 0xff; 77 break; 78 case MIPS_REVISION_SCON_BONITO: 79 /* The following will generate a PCI IACK cycle on the 80 * Bonito controller. It's a little bit kludgy, but it 81 * was the easiest way to implement it in hardware at 82 * the given time. 83 */ 84 BONITO_PCIMAP_CFG = 0x20000; 85 86 /* Flush Bonito register block */ 87 dummy = BONITO_PCIMAP_CFG; 88 iob(); /* sync */ 89 90 irq = readl((u32 *)_pcictrl_bonito_pcicfg); 91 iob(); /* sync */ 92 irq &= 0xff; 93 BONITO_PCIMAP_CFG = 0; 94 break; 95 default: 96 printk(KERN_WARNING "Unknown system controller.\n"); 97 return -1; 98 } 99 return irq; 100 } 101 102 static inline int get_int(void) 103 { 104 unsigned long flags; 105 int irq; 106 spin_lock_irqsave(&mips_irq_lock, flags); 107 108 irq = mips_pcibios_iack(); 109 110 /* 111 * The only way we can decide if an interrupt is spurious 112 * is by checking the 8259 registers. This needs a spinlock 113 * on an SMP system, so leave it up to the generic code... 114 */ 115 116 spin_unlock_irqrestore(&mips_irq_lock, flags); 117 118 return irq; 119 } 120 121 static void malta_hw0_irqdispatch(void) 122 { 123 int irq; 124 125 irq = get_int(); 126 if (irq < 0) { 127 /* interrupt has already been cleared */ 128 return; 129 } 130 131 do_IRQ(MALTA_INT_BASE + irq); 132 } 133 134 static void malta_ipi_irqdispatch(void) 135 { 136 int irq; 137 138 irq = gic_get_int(); 139 if (irq < 0) 140 return; /* interrupt has already been cleared */ 141 142 do_IRQ(MIPS_GIC_IRQ_BASE + irq); 143 } 144 145 static void corehi_irqdispatch(void) 146 { 147 unsigned int intedge, intsteer, pcicmd, pcibadaddr; 148 unsigned int pcimstat, intisr, inten, intpol; 149 unsigned int intrcause, datalo, datahi; 150 struct pt_regs *regs = get_irq_regs(); 151 152 printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n"); 153 printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n" 154 "Cause : %08lx\nbadVaddr : %08lx\n", 155 regs->cp0_epc, regs->cp0_status, 156 regs->cp0_cause, regs->cp0_badvaddr); 157 158 /* Read all the registers and then print them as there is a 159 problem with interspersed printk's upsetting the Bonito controller. 160 Do it for the others too. 161 */ 162 163 switch (mips_revision_sconid) { 164 case MIPS_REVISION_SCON_SOCIT: 165 case MIPS_REVISION_SCON_ROCIT: 166 case MIPS_REVISION_SCON_SOCITSC: 167 case MIPS_REVISION_SCON_SOCITSCP: 168 ll_msc_irq(); 169 break; 170 case MIPS_REVISION_SCON_GT64120: 171 intrcause = GT_READ(GT_INTRCAUSE_OFS); 172 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); 173 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); 174 printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause); 175 printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n", 176 datahi, datalo); 177 break; 178 case MIPS_REVISION_SCON_BONITO: 179 pcibadaddr = BONITO_PCIBADADDR; 180 pcimstat = BONITO_PCIMSTAT; 181 intisr = BONITO_INTISR; 182 inten = BONITO_INTEN; 183 intpol = BONITO_INTPOL; 184 intedge = BONITO_INTEDGE; 185 intsteer = BONITO_INTSTEER; 186 pcicmd = BONITO_PCICMD; 187 printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr); 188 printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten); 189 printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol); 190 printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge); 191 printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer); 192 printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd); 193 printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr); 194 printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat); 195 break; 196 } 197 198 die("CoreHi interrupt", regs); 199 } 200 201 static inline int clz(unsigned long x) 202 { 203 __asm__( 204 " .set push \n" 205 " .set mips32 \n" 206 " clz %0, %1 \n" 207 " .set pop \n" 208 : "=r" (x) 209 : "r" (x)); 210 211 return x; 212 } 213 214 /* 215 * Version of ffs that only looks at bits 12..15. 216 */ 217 static inline unsigned int irq_ffs(unsigned int pending) 218 { 219 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 220 return -clz(pending) + 31 - CAUSEB_IP; 221 #else 222 unsigned int a0 = 7; 223 unsigned int t0; 224 225 t0 = pending & 0xf000; 226 t0 = t0 < 1; 227 t0 = t0 << 2; 228 a0 = a0 - t0; 229 pending = pending << t0; 230 231 t0 = pending & 0xc000; 232 t0 = t0 < 1; 233 t0 = t0 << 1; 234 a0 = a0 - t0; 235 pending = pending << t0; 236 237 t0 = pending & 0x8000; 238 t0 = t0 < 1; 239 /* t0 = t0 << 2; */ 240 a0 = a0 - t0; 241 /* pending = pending << t0; */ 242 243 return a0; 244 #endif 245 } 246 247 /* 248 * IRQs on the Malta board look basically (barring software IRQs which we 249 * don't use at all and all external interrupt sources are combined together 250 * on hardware interrupt 0 (MIPS IRQ 2)) like: 251 * 252 * MIPS IRQ Source 253 * -------- ------ 254 * 0 Software (ignored) 255 * 1 Software (ignored) 256 * 2 Combined hardware interrupt (hw0) 257 * 3 Hardware (ignored) 258 * 4 Hardware (ignored) 259 * 5 Hardware (ignored) 260 * 6 Hardware (ignored) 261 * 7 R4k timer (what we use) 262 * 263 * We handle the IRQ according to _our_ priority which is: 264 * 265 * Highest ---- R4k Timer 266 * Lowest ---- Combined hardware interrupt 267 * 268 * then we just return, if multiple IRQs are pending then we will just take 269 * another exception, big deal. 270 */ 271 272 asmlinkage void plat_irq_dispatch(void) 273 { 274 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 275 int irq; 276 277 irq = irq_ffs(pending); 278 279 if (irq == MIPSCPU_INT_I8259A) 280 malta_hw0_irqdispatch(); 281 else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()])) 282 malta_ipi_irqdispatch(); 283 else if (irq >= 0) 284 do_IRQ(MIPS_CPU_IRQ_BASE + irq); 285 else 286 spurious_interrupt(); 287 } 288 289 #ifdef CONFIG_MIPS_MT_SMP 290 291 292 #define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3 293 #define GIC_MIPS_CPU_IPI_CALL_IRQ 4 294 295 #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ 296 #define C_RESCHED C_SW0 297 #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */ 298 #define C_CALL C_SW1 299 static int cpu_ipi_resched_irq, cpu_ipi_call_irq; 300 301 static void ipi_resched_dispatch(void) 302 { 303 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); 304 } 305 306 static void ipi_call_dispatch(void) 307 { 308 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); 309 } 310 311 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) 312 { 313 return IRQ_HANDLED; 314 } 315 316 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) 317 { 318 smp_call_function_interrupt(); 319 320 return IRQ_HANDLED; 321 } 322 323 static struct irqaction irq_resched = { 324 .handler = ipi_resched_interrupt, 325 .flags = IRQF_DISABLED|IRQF_PERCPU, 326 .name = "IPI_resched" 327 }; 328 329 static struct irqaction irq_call = { 330 .handler = ipi_call_interrupt, 331 .flags = IRQF_DISABLED|IRQF_PERCPU, 332 .name = "IPI_call" 333 }; 334 #endif /* CONFIG_MIPS_MT_SMP */ 335 336 static int gic_resched_int_base; 337 static int gic_call_int_base; 338 #define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu)) 339 #define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu)) 340 341 unsigned int plat_ipi_call_int_xlate(unsigned int cpu) 342 { 343 return GIC_CALL_INT(cpu); 344 } 345 346 unsigned int plat_ipi_resched_int_xlate(unsigned int cpu) 347 { 348 return GIC_RESCHED_INT(cpu); 349 } 350 351 static struct irqaction i8259irq = { 352 .handler = no_action, 353 .name = "XT-PIC cascade" 354 }; 355 356 static struct irqaction corehi_irqaction = { 357 .handler = no_action, 358 .name = "CoreHi" 359 }; 360 361 static msc_irqmap_t __initdata msc_irqmap[] = { 362 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, 363 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, 364 }; 365 static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap); 366 367 static msc_irqmap_t __initdata msc_eicirqmap[] = { 368 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, 369 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, 370 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, 371 {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0}, 372 {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0}, 373 {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0}, 374 {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, 375 {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, 376 {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, 377 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} 378 }; 379 380 static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); 381 382 #if defined(CONFIG_MIPS_MT_SMP) 383 /* 384 * This GIC specific tabular array defines the association between External 385 * Interrupts and CPUs/Core Interrupts. The nature of the External 386 * Interrupts is also defined here - polarity/trigger. 387 */ 388 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { 389 { GIC_EXT_INTR(0), X, X, X, X, 0 }, 390 { GIC_EXT_INTR(1), X, X, X, X, 0 }, 391 { GIC_EXT_INTR(2), X, X, X, X, 0 }, 392 { GIC_EXT_INTR(3), 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 393 { GIC_EXT_INTR(4), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 394 { GIC_EXT_INTR(5), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 395 { GIC_EXT_INTR(6), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 396 { GIC_EXT_INTR(7), 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 397 { GIC_EXT_INTR(8), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 398 { GIC_EXT_INTR(9), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 399 { GIC_EXT_INTR(10), X, X, X, X, 0 }, 400 { GIC_EXT_INTR(11), X, X, X, X, 0 }, 401 { GIC_EXT_INTR(12), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 402 { GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 403 { GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 404 { GIC_EXT_INTR(15), X, X, X, X, 0 }, 405 /* This is the end of the general interrupts now we do IPI ones */ 406 }; 407 #endif 408 409 /* 410 * GCMP needs to be detected before any SMP initialisation 411 */ 412 int __init gcmp_probe(unsigned long addr, unsigned long size) 413 { 414 if (gcmp_present >= 0) 415 return gcmp_present; 416 417 _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); 418 _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); 419 gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; 420 421 if (gcmp_present) 422 printk(KERN_DEBUG "GCMP present\n"); 423 return gcmp_present; 424 } 425 426 #if defined(CONFIG_MIPS_MT_SMP) 427 static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) 428 { 429 int intr = baseintr + cpu; 430 gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr); 431 gic_intr_map[intr].cpunum = cpu; 432 gic_intr_map[intr].pin = cpupin; 433 gic_intr_map[intr].polarity = GIC_POL_POS; 434 gic_intr_map[intr].trigtype = GIC_TRIG_EDGE; 435 gic_intr_map[intr].ipiflag = 1; 436 ipi_map[cpu] |= (1 << (cpupin + 2)); 437 } 438 439 static void __init fill_ipi_map(void) 440 { 441 int cpu; 442 443 for (cpu = 0; cpu < NR_CPUS; cpu++) { 444 fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1); 445 fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2); 446 } 447 } 448 #endif 449 450 void __init arch_init_irq(void) 451 { 452 init_i8259_irqs(); 453 454 if (!cpu_has_veic) 455 mips_cpu_irq_init(); 456 457 if (gcmp_present) { 458 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; 459 gic_present = 1; 460 } else { 461 _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); 462 gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & 463 MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; 464 } 465 if (gic_present) 466 printk(KERN_DEBUG "GIC present\n"); 467 468 switch (mips_revision_sconid) { 469 case MIPS_REVISION_SCON_SOCIT: 470 case MIPS_REVISION_SCON_ROCIT: 471 if (cpu_has_veic) 472 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, 473 MSC01E_INT_BASE, msc_eicirqmap, 474 msc_nr_eicirqs); 475 else 476 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, 477 MSC01C_INT_BASE, msc_irqmap, 478 msc_nr_irqs); 479 break; 480 481 case MIPS_REVISION_SCON_SOCITSC: 482 case MIPS_REVISION_SCON_SOCITSCP: 483 if (cpu_has_veic) 484 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, 485 MSC01E_INT_BASE, msc_eicirqmap, 486 msc_nr_eicirqs); 487 else 488 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, 489 MSC01C_INT_BASE, msc_irqmap, 490 msc_nr_irqs); 491 } 492 493 if (cpu_has_veic) { 494 set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch); 495 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); 496 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); 497 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); 498 } else if (cpu_has_vint) { 499 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); 500 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch); 501 #ifdef CONFIG_MIPS_MT_SMTC 502 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, 503 (0x100 << MIPSCPU_INT_I8259A)); 504 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 505 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); 506 /* 507 * Temporary hack to ensure that the subsidiary device 508 * interrupts coing in via the i8259A, but associated 509 * with low IRQ numbers, will restore the Status.IM 510 * value associated with the i8259A. 511 */ 512 { 513 int i; 514 515 for (i = 0; i < 16; i++) 516 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); 517 } 518 #else /* Not SMTC */ 519 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 520 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 521 &corehi_irqaction); 522 #endif /* CONFIG_MIPS_MT_SMTC */ 523 } else { 524 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 525 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 526 &corehi_irqaction); 527 } 528 529 #if defined(CONFIG_MIPS_MT_SMP) 530 if (gic_present) { 531 /* FIXME */ 532 int i; 533 534 gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; 535 gic_resched_int_base = gic_call_int_base - NR_CPUS; 536 537 fill_ipi_map(); 538 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); 539 if (!gcmp_present) { 540 /* Enable the GIC */ 541 i = REG(_msc01_biu_base, MSC01_SC_CFG); 542 REG(_msc01_biu_base, MSC01_SC_CFG) = 543 (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); 544 pr_debug("GIC Enabled\n"); 545 } 546 547 /* set up ipi interrupts */ 548 if (cpu_has_vint) { 549 set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); 550 set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch); 551 } 552 /* Argh.. this really needs sorting out.. */ 553 printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status()); 554 write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4); 555 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status()); 556 write_c0_status(0x1100dc00); 557 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); 558 for (i = 0; i < NR_CPUS; i++) { 559 setup_irq(MIPS_GIC_IRQ_BASE + 560 GIC_RESCHED_INT(i), &irq_resched); 561 setup_irq(MIPS_GIC_IRQ_BASE + 562 GIC_CALL_INT(i), &irq_call); 563 set_irq_handler(MIPS_GIC_IRQ_BASE + 564 GIC_RESCHED_INT(i), handle_percpu_irq); 565 set_irq_handler(MIPS_GIC_IRQ_BASE + 566 GIC_CALL_INT(i), handle_percpu_irq); 567 } 568 } else { 569 /* set up ipi interrupts */ 570 if (cpu_has_veic) { 571 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); 572 set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch); 573 cpu_ipi_resched_irq = MSC01E_INT_SW0; 574 cpu_ipi_call_irq = MSC01E_INT_SW1; 575 } else { 576 if (cpu_has_vint) { 577 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); 578 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); 579 } 580 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; 581 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; 582 } 583 584 setup_irq(cpu_ipi_resched_irq, &irq_resched); 585 setup_irq(cpu_ipi_call_irq, &irq_call); 586 587 set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); 588 set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); 589 } 590 #endif 591 } 592 593 void malta_be_init(void) 594 { 595 if (gcmp_present) { 596 /* Could change CM error mask register */ 597 } 598 } 599 600 601 static char *tr[8] = { 602 "mem", "gcr", "gic", "mmio", 603 "0x04", "0x05", "0x06", "0x07" 604 }; 605 606 static char *mcmd[32] = { 607 [0x00] = "0x00", 608 [0x01] = "Legacy Write", 609 [0x02] = "Legacy Read", 610 [0x03] = "0x03", 611 [0x04] = "0x04", 612 [0x05] = "0x05", 613 [0x06] = "0x06", 614 [0x07] = "0x07", 615 [0x08] = "Coherent Read Own", 616 [0x09] = "Coherent Read Share", 617 [0x0a] = "Coherent Read Discard", 618 [0x0b] = "Coherent Ready Share Always", 619 [0x0c] = "Coherent Upgrade", 620 [0x0d] = "Coherent Writeback", 621 [0x0e] = "0x0e", 622 [0x0f] = "0x0f", 623 [0x10] = "Coherent Copyback", 624 [0x11] = "Coherent Copyback Invalidate", 625 [0x12] = "Coherent Invalidate", 626 [0x13] = "Coherent Write Invalidate", 627 [0x14] = "Coherent Completion Sync", 628 [0x15] = "0x15", 629 [0x16] = "0x16", 630 [0x17] = "0x17", 631 [0x18] = "0x18", 632 [0x19] = "0x19", 633 [0x1a] = "0x1a", 634 [0x1b] = "0x1b", 635 [0x1c] = "0x1c", 636 [0x1d] = "0x1d", 637 [0x1e] = "0x1e", 638 [0x1f] = "0x1f" 639 }; 640 641 static char *core[8] = { 642 "Invalid/OK", "Invalid/Data", 643 "Shared/OK", "Shared/Data", 644 "Modified/OK", "Modified/Data", 645 "Exclusive/OK", "Exclusive/Data" 646 }; 647 648 static char *causes[32] = { 649 "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR", 650 "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07", 651 "0x08", "0x09", "0x0a", "0x0b", 652 "0x0c", "0x0d", "0x0e", "0x0f", 653 "0x10", "0x11", "0x12", "0x13", 654 "0x14", "0x15", "0x16", "INTVN_WR_ERR", 655 "INTVN_RD_ERR", "0x19", "0x1a", "0x1b", 656 "0x1c", "0x1d", "0x1e", "0x1f" 657 }; 658 659 int malta_be_handler(struct pt_regs *regs, int is_fixup) 660 { 661 /* This duplicates the handling in do_be which seems wrong */ 662 int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL; 663 664 if (gcmp_present) { 665 unsigned long cm_error = GCMPGCB(GCMEC); 666 unsigned long cm_addr = GCMPGCB(GCMEA); 667 unsigned long cm_other = GCMPGCB(GCMEO); 668 unsigned long cause, ocause; 669 char buf[256]; 670 671 cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK); 672 if (cause != 0) { 673 cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF; 674 if (cause < 16) { 675 unsigned long cca_bits = (cm_error >> 15) & 7; 676 unsigned long tr_bits = (cm_error >> 12) & 7; 677 unsigned long mcmd_bits = (cm_error >> 7) & 0x1f; 678 unsigned long stag_bits = (cm_error >> 3) & 15; 679 unsigned long sport_bits = (cm_error >> 0) & 7; 680 681 snprintf(buf, sizeof(buf), 682 "CCA=%lu TR=%s MCmd=%s STag=%lu " 683 "SPort=%lu\n", 684 cca_bits, tr[tr_bits], mcmd[mcmd_bits], 685 stag_bits, sport_bits); 686 } else { 687 /* glob state & sresp together */ 688 unsigned long c3_bits = (cm_error >> 18) & 7; 689 unsigned long c2_bits = (cm_error >> 15) & 7; 690 unsigned long c1_bits = (cm_error >> 12) & 7; 691 unsigned long c0_bits = (cm_error >> 9) & 7; 692 unsigned long sc_bit = (cm_error >> 8) & 1; 693 unsigned long mcmd_bits = (cm_error >> 3) & 0x1f; 694 unsigned long sport_bits = (cm_error >> 0) & 7; 695 snprintf(buf, sizeof(buf), 696 "C3=%s C2=%s C1=%s C0=%s SC=%s " 697 "MCmd=%s SPort=%lu\n", 698 core[c3_bits], core[c2_bits], 699 core[c1_bits], core[c0_bits], 700 sc_bit ? "True" : "False", 701 mcmd[mcmd_bits], sport_bits); 702 } 703 704 ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >> 705 GCMP_GCB_GMEO_ERROR_2ND_SHF; 706 707 printk("CM_ERROR=%08lx %s <%s>\n", cm_error, 708 causes[cause], buf); 709 printk("CM_ADDR =%08lx\n", cm_addr); 710 printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]); 711 712 /* reprime cause register */ 713 GCMPGCB(GCMEC) = 0; 714 } 715 } 716 717 return retval; 718 } 719