1 /* 2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. 3 * All rights reserved. 4 * Authors: Carsten Langgaard <carstenl@mips.com> 5 * Maciej W. Rozycki <macro@mips.com> 6 * 7 * This program is free software; you can distribute it and/or modify it 8 * under the terms of the GNU General Public License (Version 2) as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 19 * 20 * PROM library initialisation code. 21 */ 22 #include <linux/init.h> 23 #include <linux/string.h> 24 #include <linux/kernel.h> 25 26 #include <asm/bootinfo.h> 27 #include <asm/gt64120.h> 28 #include <asm/io.h> 29 #include <asm/system.h> 30 #include <asm/cacheflush.h> 31 #include <asm/traps.h> 32 33 #include <asm/mips-boards/prom.h> 34 #include <asm/mips-boards/generic.h> 35 #include <asm/mips-boards/bonito64.h> 36 #include <asm/mips-boards/msc01_pci.h> 37 38 #include <asm/mips-boards/malta.h> 39 40 #ifdef CONFIG_KGDB 41 extern int rs_kgdb_hook(int, int); 42 extern int rs_putDebugChar(char); 43 extern char rs_getDebugChar(void); 44 extern int saa9730_kgdb_hook(int); 45 extern int saa9730_putDebugChar(char); 46 extern char saa9730_getDebugChar(void); 47 #endif 48 49 int prom_argc; 50 int *_prom_argv, *_prom_envp; 51 52 /* 53 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. 54 * This macro take care of sign extension, if running in 64-bit mode. 55 */ 56 #define prom_envp(index) ((char *)(long)_prom_envp[(index)]) 57 58 int init_debug = 0; 59 60 int mips_revision_corid; 61 int mips_revision_sconid; 62 63 /* Bonito64 system controller register base. */ 64 unsigned long _pcictrl_bonito; 65 unsigned long _pcictrl_bonito_pcicfg; 66 67 /* GT64120 system controller register base */ 68 unsigned long _pcictrl_gt64120; 69 70 /* MIPS System controller register base */ 71 unsigned long _pcictrl_msc; 72 73 char *prom_getenv(char *envname) 74 { 75 /* 76 * Return a pointer to the given environment variable. 77 * In 64-bit mode: we're using 64-bit pointers, but all pointers 78 * in the PROM structures are only 32-bit, so we need some 79 * workarounds, if we are running in 64-bit mode. 80 */ 81 int i, index=0; 82 83 i = strlen(envname); 84 85 while (prom_envp(index)) { 86 if(strncmp(envname, prom_envp(index), i) == 0) { 87 return(prom_envp(index+1)); 88 } 89 index += 2; 90 } 91 92 return NULL; 93 } 94 95 static inline unsigned char str2hexnum(unsigned char c) 96 { 97 if (c >= '0' && c <= '9') 98 return c - '0'; 99 if (c >= 'a' && c <= 'f') 100 return c - 'a' + 10; 101 return 0; /* foo */ 102 } 103 104 static inline void str2eaddr(unsigned char *ea, unsigned char *str) 105 { 106 int i; 107 108 for (i = 0; i < 6; i++) { 109 unsigned char num; 110 111 if((*str == '.') || (*str == ':')) 112 str++; 113 num = str2hexnum(*str++) << 4; 114 num |= (str2hexnum(*str++)); 115 ea[i] = num; 116 } 117 } 118 119 int get_ethernet_addr(char *ethernet_addr) 120 { 121 char *ethaddr_str; 122 123 ethaddr_str = prom_getenv("ethaddr"); 124 if (!ethaddr_str) { 125 printk("ethaddr not set in boot prom\n"); 126 return -1; 127 } 128 str2eaddr(ethernet_addr, ethaddr_str); 129 130 if (init_debug > 1) { 131 int i; 132 printk("get_ethernet_addr: "); 133 for (i=0; i<5; i++) 134 printk("%02x:", (unsigned char)*(ethernet_addr+i)); 135 printk("%02x\n", *(ethernet_addr+i)); 136 } 137 138 return 0; 139 } 140 141 #ifdef CONFIG_SERIAL_8250_CONSOLE 142 static void __init console_config(void) 143 { 144 char console_string[40]; 145 int baud = 0; 146 char parity = '\0', bits = '\0', flow = '\0'; 147 char *s; 148 149 if ((strstr(prom_getcmdline(), "console=")) == NULL) { 150 s = prom_getenv("modetty0"); 151 if (s) { 152 while (*s >= '0' && *s <= '9') 153 baud = baud*10 + *s++ - '0'; 154 if (*s == ',') s++; 155 if (*s) parity = *s++; 156 if (*s == ',') s++; 157 if (*s) bits = *s++; 158 if (*s == ',') s++; 159 if (*s == 'h') flow = 'r'; 160 } 161 if (baud == 0) 162 baud = 38400; 163 if (parity != 'n' && parity != 'o' && parity != 'e') 164 parity = 'n'; 165 if (bits != '7' && bits != '8') 166 bits = '8'; 167 if (flow == '\0') 168 flow = 'r'; 169 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); 170 strcat(prom_getcmdline(), console_string); 171 pr_info("Config serial console:%s\n", console_string); 172 } 173 } 174 #endif 175 176 #ifdef CONFIG_KGDB 177 void __init kgdb_config(void) 178 { 179 extern int (*generic_putDebugChar)(char); 180 extern char (*generic_getDebugChar)(void); 181 char *argptr; 182 int line, speed; 183 184 argptr = prom_getcmdline(); 185 if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { 186 argptr += strlen("kgdb=ttyS"); 187 if (*argptr != '0' && *argptr != '1') 188 printk("KGDB: Unknown serial line /dev/ttyS%c, " 189 "falling back to /dev/ttyS1\n", *argptr); 190 line = *argptr == '0' ? 0 : 1; 191 printk("KGDB: Using serial line /dev/ttyS%d for session\n", line); 192 193 speed = 0; 194 if (*++argptr == ',') 195 { 196 int c; 197 while ((c = *++argptr) && ('0' <= c && c <= '9')) 198 speed = speed * 10 + c - '0'; 199 } 200 { 201 speed = rs_kgdb_hook(line, speed); 202 generic_putDebugChar = rs_putDebugChar; 203 generic_getDebugChar = rs_getDebugChar; 204 } 205 206 pr_info("KGDB: Using serial line /dev/ttyS%d at %d for " 207 "session, please connect your debugger\n", 208 line ? 1 : 0, speed); 209 210 { 211 char *s; 212 for (s = "Please connect GDB to this port\r\n"; *s; ) 213 generic_putDebugChar(*s++); 214 } 215 216 /* Breakpoint is invoked after interrupts are initialised */ 217 } 218 } 219 #endif 220 221 static void __init mips_nmi_setup(void) 222 { 223 void *base; 224 extern char except_vec_nmi; 225 226 base = cpu_has_veic ? 227 (void *)(CAC_BASE + 0xa80) : 228 (void *)(CAC_BASE + 0x380); 229 memcpy(base, &except_vec_nmi, 0x80); 230 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 231 } 232 233 static void __init mips_ejtag_setup(void) 234 { 235 void *base; 236 extern char except_vec_ejtag_debug; 237 238 base = cpu_has_veic ? 239 (void *)(CAC_BASE + 0xa00) : 240 (void *)(CAC_BASE + 0x300); 241 memcpy(base, &except_vec_ejtag_debug, 0x80); 242 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 243 } 244 245 extern struct plat_smp_ops msmtc_smp_ops; 246 247 void __init prom_init(void) 248 { 249 prom_argc = fw_arg0; 250 _prom_argv = (int *) fw_arg1; 251 _prom_envp = (int *) fw_arg2; 252 253 mips_display_message("LINUX"); 254 255 /* 256 * early setup of _pcictrl_bonito so that we can determine 257 * the system controller on a CORE_EMUL board 258 */ 259 _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); 260 261 mips_revision_corid = MIPS_REVISION_CORID; 262 263 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { 264 if (BONITO_PCIDID == 0x0001df53 || 265 BONITO_PCIDID == 0x0003df53) 266 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; 267 else 268 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; 269 } 270 271 mips_revision_sconid = MIPS_REVISION_SCONID; 272 if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { 273 switch (mips_revision_corid) { 274 case MIPS_REVISION_CORID_QED_RM5261: 275 case MIPS_REVISION_CORID_CORE_LV: 276 case MIPS_REVISION_CORID_CORE_FPGA: 277 case MIPS_REVISION_CORID_CORE_FPGAR2: 278 mips_revision_sconid = MIPS_REVISION_SCON_GT64120; 279 break; 280 case MIPS_REVISION_CORID_CORE_EMUL_BON: 281 case MIPS_REVISION_CORID_BONITO64: 282 case MIPS_REVISION_CORID_CORE_20K: 283 mips_revision_sconid = MIPS_REVISION_SCON_BONITO; 284 break; 285 case MIPS_REVISION_CORID_CORE_MSC: 286 case MIPS_REVISION_CORID_CORE_FPGA2: 287 case MIPS_REVISION_CORID_CORE_24K: 288 /* 289 * SOCit/ROCit support is essentially identical 290 * but make an attempt to distinguish them 291 */ 292 mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; 293 break; 294 case MIPS_REVISION_CORID_CORE_FPGA3: 295 case MIPS_REVISION_CORID_CORE_FPGA4: 296 case MIPS_REVISION_CORID_CORE_FPGA5: 297 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 298 default: 299 /* See above */ 300 mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; 301 break; 302 } 303 } 304 305 switch (mips_revision_sconid) { 306 u32 start, map, mask, data; 307 308 case MIPS_REVISION_SCON_GT64120: 309 /* 310 * Setup the North bridge to do Master byte-lane swapping 311 * when running in bigendian. 312 */ 313 _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); 314 315 #ifdef CONFIG_CPU_LITTLE_ENDIAN 316 GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | 317 GT_PCI0_CMD_SBYTESWAP_BIT); 318 #else 319 GT_WRITE(GT_PCI0_CMD_OFS, 0); 320 #endif 321 /* Fix up PCI I/O mapping if necessary (for Atlas). */ 322 start = GT_READ(GT_PCI0IOLD_OFS); 323 map = GT_READ(GT_PCI0IOREMAP_OFS); 324 if ((start & map) != 0) { 325 map &= ~start; 326 GT_WRITE(GT_PCI0IOREMAP_OFS, map); 327 } 328 329 set_io_port_base(MALTA_GT_PORT_BASE); 330 break; 331 332 case MIPS_REVISION_SCON_BONITO: 333 _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); 334 335 /* 336 * Disable Bonito IOBC. 337 */ 338 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & 339 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 340 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 341 342 /* 343 * Setup the North bridge to do Master byte-lane swapping 344 * when running in bigendian. 345 */ 346 #ifdef CONFIG_CPU_LITTLE_ENDIAN 347 BONITO_BONGENCFG = BONITO_BONGENCFG & 348 ~(BONITO_BONGENCFG_MSTRBYTESWAP | 349 BONITO_BONGENCFG_BYTESWAP); 350 #else 351 BONITO_BONGENCFG = BONITO_BONGENCFG | 352 BONITO_BONGENCFG_MSTRBYTESWAP | 353 BONITO_BONGENCFG_BYTESWAP; 354 #endif 355 356 set_io_port_base(MALTA_BONITO_PORT_BASE); 357 break; 358 359 case MIPS_REVISION_SCON_SOCIT: 360 case MIPS_REVISION_SCON_ROCIT: 361 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); 362 mips_pci_controller: 363 mb(); 364 MSC_READ(MSC01_PCI_CFG, data); 365 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); 366 wmb(); 367 368 /* Fix up lane swapping. */ 369 #ifdef CONFIG_CPU_LITTLE_ENDIAN 370 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); 371 #else 372 MSC_WRITE(MSC01_PCI_SWAP, 373 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | 374 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | 375 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); 376 #endif 377 /* Fix up target memory mapping. */ 378 MSC_READ(MSC01_PCI_BAR0, mask); 379 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); 380 381 /* Don't handle target retries indefinitely. */ 382 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == 383 MSC01_PCI_CFG_MAXRTRY_MSK) 384 data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << 385 MSC01_PCI_CFG_MAXRTRY_SHF)) | 386 ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << 387 MSC01_PCI_CFG_MAXRTRY_SHF); 388 389 wmb(); 390 MSC_WRITE(MSC01_PCI_CFG, data); 391 mb(); 392 393 set_io_port_base(MALTA_MSC_PORT_BASE); 394 break; 395 396 case MIPS_REVISION_SCON_SOCITSC: 397 case MIPS_REVISION_SCON_SOCITSCP: 398 _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); 399 goto mips_pci_controller; 400 401 default: 402 /* Unknown system controller */ 403 mips_display_message("SC Error"); 404 while (1); /* We die here... */ 405 } 406 board_nmi_handler_setup = mips_nmi_setup; 407 board_ejtag_handler_setup = mips_ejtag_setup; 408 409 pr_info("\nLINUX started...\n"); 410 prom_init_cmdline(); 411 prom_meminit(); 412 #ifdef CONFIG_SERIAL_8250_CONSOLE 413 console_config(); 414 #endif 415 #ifdef CONFIG_MIPS_CMP 416 register_smp_ops(&cmp_smp_ops); 417 #endif 418 #ifdef CONFIG_MIPS_MT_SMP 419 register_smp_ops(&vsmp_smp_ops); 420 #endif 421 #ifdef CONFIG_MIPS_MT_SMTC 422 register_smp_ops(&msmtc_smp_ops); 423 #endif 424 } 425