1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * PROM library initialisation code. 7 * 8 * Copyright (C) 1999,2000,2004,2005,2012 MIPS Technologies, Inc. 9 * All rights reserved. 10 * Authors: Carsten Langgaard <carstenl@mips.com> 11 * Maciej W. Rozycki <macro@mips.com> 12 * Steven J. Hill <sjhill@mips.com> 13 */ 14 #include <linux/init.h> 15 #include <linux/string.h> 16 #include <linux/kernel.h> 17 #include <linux/serial_8250.h> 18 19 #include <asm/cacheflush.h> 20 #include <asm/smp-ops.h> 21 #include <asm/traps.h> 22 #include <asm/fw/fw.h> 23 #include <asm/mips-cm.h> 24 #include <asm/mips-cpc.h> 25 #include <asm/mips-boards/generic.h> 26 #include <asm/mips-boards/malta.h> 27 28 static int mips_revision_corid; 29 int mips_revision_sconid; 30 31 /* Bonito64 system controller register base. */ 32 unsigned long _pcictrl_bonito; 33 unsigned long _pcictrl_bonito_pcicfg; 34 35 /* GT64120 system controller register base */ 36 unsigned long _pcictrl_gt64120; 37 38 /* MIPS System controller register base */ 39 unsigned long _pcictrl_msc; 40 41 #ifdef CONFIG_SERIAL_8250_CONSOLE 42 static void __init console_config(void) 43 { 44 char console_string[40]; 45 int baud = 0; 46 char parity = '\0', bits = '\0', flow = '\0'; 47 char *s; 48 49 s = fw_getenv("modetty0"); 50 if (s) { 51 while (*s >= '0' && *s <= '9') 52 baud = baud*10 + *s++ - '0'; 53 if (*s == ',') 54 s++; 55 if (*s) 56 parity = *s++; 57 if (*s == ',') 58 s++; 59 if (*s) 60 bits = *s++; 61 if (*s == ',') 62 s++; 63 if (*s == 'h') 64 flow = 'r'; 65 } 66 if (baud == 0) 67 baud = 38400; 68 if (parity != 'n' && parity != 'o' && parity != 'e') 69 parity = 'n'; 70 if (bits != '7' && bits != '8') 71 bits = '8'; 72 if (flow == '\0') 73 flow = 'r'; 74 75 if ((strstr(fw_getcmdline(), "earlycon=")) == NULL) { 76 sprintf(console_string, "uart8250,io,0x3f8,%d%c%c", baud, 77 parity, bits); 78 setup_early_serial8250_console(console_string); 79 } 80 81 if ((strstr(fw_getcmdline(), "console=")) == NULL) { 82 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, 83 parity, bits, flow); 84 strcat(fw_getcmdline(), console_string); 85 pr_info("Config serial console:%s\n", console_string); 86 } 87 } 88 #endif 89 90 static void __init mips_nmi_setup(void) 91 { 92 void *base; 93 extern char except_vec_nmi; 94 95 base = cpu_has_veic ? 96 (void *)(CAC_BASE + 0xa80) : 97 (void *)(CAC_BASE + 0x380); 98 memcpy(base, &except_vec_nmi, 0x80); 99 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 100 } 101 102 static void __init mips_ejtag_setup(void) 103 { 104 void *base; 105 extern char except_vec_ejtag_debug; 106 107 base = cpu_has_veic ? 108 (void *)(CAC_BASE + 0xa00) : 109 (void *)(CAC_BASE + 0x300); 110 memcpy(base, &except_vec_ejtag_debug, 0x80); 111 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 112 } 113 114 phys_t mips_cpc_default_phys_base(void) 115 { 116 return CPC_BASE_ADDR; 117 } 118 119 extern struct plat_smp_ops msmtc_smp_ops; 120 121 void __init prom_init(void) 122 { 123 mips_display_message("LINUX"); 124 125 /* 126 * early setup of _pcictrl_bonito so that we can determine 127 * the system controller on a CORE_EMUL board 128 */ 129 _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); 130 131 mips_revision_corid = MIPS_REVISION_CORID; 132 133 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { 134 if (BONITO_PCIDID == 0x0001df53 || 135 BONITO_PCIDID == 0x0003df53) 136 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; 137 else 138 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; 139 } 140 141 mips_revision_sconid = MIPS_REVISION_SCONID; 142 if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { 143 switch (mips_revision_corid) { 144 case MIPS_REVISION_CORID_QED_RM5261: 145 case MIPS_REVISION_CORID_CORE_LV: 146 case MIPS_REVISION_CORID_CORE_FPGA: 147 case MIPS_REVISION_CORID_CORE_FPGAR2: 148 mips_revision_sconid = MIPS_REVISION_SCON_GT64120; 149 break; 150 case MIPS_REVISION_CORID_CORE_EMUL_BON: 151 case MIPS_REVISION_CORID_BONITO64: 152 case MIPS_REVISION_CORID_CORE_20K: 153 mips_revision_sconid = MIPS_REVISION_SCON_BONITO; 154 break; 155 case MIPS_REVISION_CORID_CORE_MSC: 156 case MIPS_REVISION_CORID_CORE_FPGA2: 157 case MIPS_REVISION_CORID_CORE_24K: 158 /* 159 * SOCit/ROCit support is essentially identical 160 * but make an attempt to distinguish them 161 */ 162 mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; 163 break; 164 case MIPS_REVISION_CORID_CORE_FPGA3: 165 case MIPS_REVISION_CORID_CORE_FPGA4: 166 case MIPS_REVISION_CORID_CORE_FPGA5: 167 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 168 default: 169 /* See above */ 170 mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; 171 break; 172 } 173 } 174 175 switch (mips_revision_sconid) { 176 u32 start, map, mask, data; 177 178 case MIPS_REVISION_SCON_GT64120: 179 /* 180 * Setup the North bridge to do Master byte-lane swapping 181 * when running in bigendian. 182 */ 183 _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); 184 185 #ifdef CONFIG_CPU_LITTLE_ENDIAN 186 GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | 187 GT_PCI0_CMD_SBYTESWAP_BIT); 188 #else 189 GT_WRITE(GT_PCI0_CMD_OFS, 0); 190 #endif 191 /* Fix up PCI I/O mapping if necessary (for Atlas). */ 192 start = GT_READ(GT_PCI0IOLD_OFS); 193 map = GT_READ(GT_PCI0IOREMAP_OFS); 194 if ((start & map) != 0) { 195 map &= ~start; 196 GT_WRITE(GT_PCI0IOREMAP_OFS, map); 197 } 198 199 set_io_port_base(MALTA_GT_PORT_BASE); 200 break; 201 202 case MIPS_REVISION_SCON_BONITO: 203 _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); 204 205 /* 206 * Disable Bonito IOBC. 207 */ 208 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & 209 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 210 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 211 212 /* 213 * Setup the North bridge to do Master byte-lane swapping 214 * when running in bigendian. 215 */ 216 #ifdef CONFIG_CPU_LITTLE_ENDIAN 217 BONITO_BONGENCFG = BONITO_BONGENCFG & 218 ~(BONITO_BONGENCFG_MSTRBYTESWAP | 219 BONITO_BONGENCFG_BYTESWAP); 220 #else 221 BONITO_BONGENCFG = BONITO_BONGENCFG | 222 BONITO_BONGENCFG_MSTRBYTESWAP | 223 BONITO_BONGENCFG_BYTESWAP; 224 #endif 225 226 set_io_port_base(MALTA_BONITO_PORT_BASE); 227 break; 228 229 case MIPS_REVISION_SCON_SOCIT: 230 case MIPS_REVISION_SCON_ROCIT: 231 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); 232 mips_pci_controller: 233 mb(); 234 MSC_READ(MSC01_PCI_CFG, data); 235 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); 236 wmb(); 237 238 /* Fix up lane swapping. */ 239 #ifdef CONFIG_CPU_LITTLE_ENDIAN 240 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); 241 #else 242 MSC_WRITE(MSC01_PCI_SWAP, 243 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | 244 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | 245 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); 246 #endif 247 #ifndef CONFIG_EVA 248 /* Fix up target memory mapping. */ 249 MSC_READ(MSC01_PCI_BAR0, mask); 250 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); 251 #else 252 /* 253 * Setup the Malta max (2GB) memory for PCI DMA in host bridge 254 * in transparent addressing mode, starting from 0x80000000. 255 */ 256 mask = PHYS_OFFSET | (1<<3); 257 MSC_WRITE(MSC01_PCI_BAR0, mask); 258 259 mask = PHYS_OFFSET; 260 MSC_WRITE(MSC01_PCI_HEAD4, mask); 261 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask); 262 MSC_WRITE(MSC01_PCI_P2SCMAPL, mask); 263 #endif 264 /* Don't handle target retries indefinitely. */ 265 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == 266 MSC01_PCI_CFG_MAXRTRY_MSK) 267 data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << 268 MSC01_PCI_CFG_MAXRTRY_SHF)) | 269 ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << 270 MSC01_PCI_CFG_MAXRTRY_SHF); 271 272 wmb(); 273 MSC_WRITE(MSC01_PCI_CFG, data); 274 mb(); 275 276 set_io_port_base(MALTA_MSC_PORT_BASE); 277 break; 278 279 case MIPS_REVISION_SCON_SOCITSC: 280 case MIPS_REVISION_SCON_SOCITSCP: 281 _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); 282 goto mips_pci_controller; 283 284 default: 285 /* Unknown system controller */ 286 mips_display_message("SC Error"); 287 while (1); /* We die here... */ 288 } 289 board_nmi_handler_setup = mips_nmi_setup; 290 board_ejtag_handler_setup = mips_ejtag_setup; 291 292 fw_init_cmdline(); 293 fw_meminit(); 294 #ifdef CONFIG_SERIAL_8250_CONSOLE 295 console_config(); 296 #endif 297 /* Early detection of CMP support */ 298 mips_cm_probe(); 299 mips_cpc_probe(); 300 301 if (!register_cps_smp_ops()) 302 return; 303 if (!register_cmp_smp_ops()) 304 return; 305 if (!register_vsmp_smp_ops()) 306 return; 307 308 #ifdef CONFIG_MIPS_MT_SMTC 309 register_smp_ops(&msmtc_smp_ops); 310 #endif 311 } 312