1 /* 2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. 3 * All rights reserved. 4 * Authors: Carsten Langgaard <carstenl@mips.com> 5 * Maciej W. Rozycki <macro@mips.com> 6 * 7 * This program is free software; you can distribute it and/or modify it 8 * under the terms of the GNU General Public License (Version 2) as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 19 * 20 * PROM library initialisation code. 21 */ 22 #include <linux/init.h> 23 #include <linux/string.h> 24 #include <linux/kernel.h> 25 26 #include <asm/bootinfo.h> 27 #include <asm/gt64120.h> 28 #include <asm/io.h> 29 #include <asm/system.h> 30 #include <asm/cacheflush.h> 31 #include <asm/smp-ops.h> 32 #include <asm/traps.h> 33 34 #include <asm/gcmpregs.h> 35 #include <asm/mips-boards/prom.h> 36 #include <asm/mips-boards/generic.h> 37 #include <asm/mips-boards/bonito64.h> 38 #include <asm/mips-boards/msc01_pci.h> 39 40 #include <asm/mips-boards/malta.h> 41 42 int prom_argc; 43 int *_prom_argv, *_prom_envp; 44 45 /* 46 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. 47 * This macro take care of sign extension, if running in 64-bit mode. 48 */ 49 #define prom_envp(index) ((char *)(long)_prom_envp[(index)]) 50 51 int init_debug; 52 53 static int mips_revision_corid; 54 int mips_revision_sconid; 55 56 /* Bonito64 system controller register base. */ 57 unsigned long _pcictrl_bonito; 58 unsigned long _pcictrl_bonito_pcicfg; 59 60 /* GT64120 system controller register base */ 61 unsigned long _pcictrl_gt64120; 62 63 /* MIPS System controller register base */ 64 unsigned long _pcictrl_msc; 65 66 char *prom_getenv(char *envname) 67 { 68 /* 69 * Return a pointer to the given environment variable. 70 * In 64-bit mode: we're using 64-bit pointers, but all pointers 71 * in the PROM structures are only 32-bit, so we need some 72 * workarounds, if we are running in 64-bit mode. 73 */ 74 int i, index=0; 75 76 i = strlen(envname); 77 78 while (prom_envp(index)) { 79 if(strncmp(envname, prom_envp(index), i) == 0) { 80 return(prom_envp(index+1)); 81 } 82 index += 2; 83 } 84 85 return NULL; 86 } 87 88 static inline unsigned char str2hexnum(unsigned char c) 89 { 90 if (c >= '0' && c <= '9') 91 return c - '0'; 92 if (c >= 'a' && c <= 'f') 93 return c - 'a' + 10; 94 return 0; /* foo */ 95 } 96 97 static inline void str2eaddr(unsigned char *ea, unsigned char *str) 98 { 99 int i; 100 101 for (i = 0; i < 6; i++) { 102 unsigned char num; 103 104 if((*str == '.') || (*str == ':')) 105 str++; 106 num = str2hexnum(*str++) << 4; 107 num |= (str2hexnum(*str++)); 108 ea[i] = num; 109 } 110 } 111 112 int get_ethernet_addr(char *ethernet_addr) 113 { 114 char *ethaddr_str; 115 116 ethaddr_str = prom_getenv("ethaddr"); 117 if (!ethaddr_str) { 118 printk("ethaddr not set in boot prom\n"); 119 return -1; 120 } 121 str2eaddr(ethernet_addr, ethaddr_str); 122 123 if (init_debug > 1) { 124 int i; 125 printk("get_ethernet_addr: "); 126 for (i=0; i<5; i++) 127 printk("%02x:", (unsigned char)*(ethernet_addr+i)); 128 printk("%02x\n", *(ethernet_addr+i)); 129 } 130 131 return 0; 132 } 133 134 #ifdef CONFIG_SERIAL_8250_CONSOLE 135 static void __init console_config(void) 136 { 137 char console_string[40]; 138 int baud = 0; 139 char parity = '\0', bits = '\0', flow = '\0'; 140 char *s; 141 142 if ((strstr(prom_getcmdline(), "console=")) == NULL) { 143 s = prom_getenv("modetty0"); 144 if (s) { 145 while (*s >= '0' && *s <= '9') 146 baud = baud*10 + *s++ - '0'; 147 if (*s == ',') s++; 148 if (*s) parity = *s++; 149 if (*s == ',') s++; 150 if (*s) bits = *s++; 151 if (*s == ',') s++; 152 if (*s == 'h') flow = 'r'; 153 } 154 if (baud == 0) 155 baud = 38400; 156 if (parity != 'n' && parity != 'o' && parity != 'e') 157 parity = 'n'; 158 if (bits != '7' && bits != '8') 159 bits = '8'; 160 if (flow == '\0') 161 flow = 'r'; 162 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); 163 strcat(prom_getcmdline(), console_string); 164 pr_info("Config serial console:%s\n", console_string); 165 } 166 } 167 #endif 168 169 static void __init mips_nmi_setup(void) 170 { 171 void *base; 172 extern char except_vec_nmi; 173 174 base = cpu_has_veic ? 175 (void *)(CAC_BASE + 0xa80) : 176 (void *)(CAC_BASE + 0x380); 177 memcpy(base, &except_vec_nmi, 0x80); 178 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 179 } 180 181 static void __init mips_ejtag_setup(void) 182 { 183 void *base; 184 extern char except_vec_ejtag_debug; 185 186 base = cpu_has_veic ? 187 (void *)(CAC_BASE + 0xa00) : 188 (void *)(CAC_BASE + 0x300); 189 memcpy(base, &except_vec_ejtag_debug, 0x80); 190 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 191 } 192 193 extern struct plat_smp_ops msmtc_smp_ops; 194 195 void __init prom_init(void) 196 { 197 prom_argc = fw_arg0; 198 _prom_argv = (int *) fw_arg1; 199 _prom_envp = (int *) fw_arg2; 200 201 mips_display_message("LINUX"); 202 203 /* 204 * early setup of _pcictrl_bonito so that we can determine 205 * the system controller on a CORE_EMUL board 206 */ 207 _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); 208 209 mips_revision_corid = MIPS_REVISION_CORID; 210 211 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { 212 if (BONITO_PCIDID == 0x0001df53 || 213 BONITO_PCIDID == 0x0003df53) 214 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; 215 else 216 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; 217 } 218 219 mips_revision_sconid = MIPS_REVISION_SCONID; 220 if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { 221 switch (mips_revision_corid) { 222 case MIPS_REVISION_CORID_QED_RM5261: 223 case MIPS_REVISION_CORID_CORE_LV: 224 case MIPS_REVISION_CORID_CORE_FPGA: 225 case MIPS_REVISION_CORID_CORE_FPGAR2: 226 mips_revision_sconid = MIPS_REVISION_SCON_GT64120; 227 break; 228 case MIPS_REVISION_CORID_CORE_EMUL_BON: 229 case MIPS_REVISION_CORID_BONITO64: 230 case MIPS_REVISION_CORID_CORE_20K: 231 mips_revision_sconid = MIPS_REVISION_SCON_BONITO; 232 break; 233 case MIPS_REVISION_CORID_CORE_MSC: 234 case MIPS_REVISION_CORID_CORE_FPGA2: 235 case MIPS_REVISION_CORID_CORE_24K: 236 /* 237 * SOCit/ROCit support is essentially identical 238 * but make an attempt to distinguish them 239 */ 240 mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; 241 break; 242 case MIPS_REVISION_CORID_CORE_FPGA3: 243 case MIPS_REVISION_CORID_CORE_FPGA4: 244 case MIPS_REVISION_CORID_CORE_FPGA5: 245 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 246 default: 247 /* See above */ 248 mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; 249 break; 250 } 251 } 252 253 switch (mips_revision_sconid) { 254 u32 start, map, mask, data; 255 256 case MIPS_REVISION_SCON_GT64120: 257 /* 258 * Setup the North bridge to do Master byte-lane swapping 259 * when running in bigendian. 260 */ 261 _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); 262 263 #ifdef CONFIG_CPU_LITTLE_ENDIAN 264 GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | 265 GT_PCI0_CMD_SBYTESWAP_BIT); 266 #else 267 GT_WRITE(GT_PCI0_CMD_OFS, 0); 268 #endif 269 /* Fix up PCI I/O mapping if necessary (for Atlas). */ 270 start = GT_READ(GT_PCI0IOLD_OFS); 271 map = GT_READ(GT_PCI0IOREMAP_OFS); 272 if ((start & map) != 0) { 273 map &= ~start; 274 GT_WRITE(GT_PCI0IOREMAP_OFS, map); 275 } 276 277 set_io_port_base(MALTA_GT_PORT_BASE); 278 break; 279 280 case MIPS_REVISION_SCON_BONITO: 281 _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); 282 283 /* 284 * Disable Bonito IOBC. 285 */ 286 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & 287 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 288 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 289 290 /* 291 * Setup the North bridge to do Master byte-lane swapping 292 * when running in bigendian. 293 */ 294 #ifdef CONFIG_CPU_LITTLE_ENDIAN 295 BONITO_BONGENCFG = BONITO_BONGENCFG & 296 ~(BONITO_BONGENCFG_MSTRBYTESWAP | 297 BONITO_BONGENCFG_BYTESWAP); 298 #else 299 BONITO_BONGENCFG = BONITO_BONGENCFG | 300 BONITO_BONGENCFG_MSTRBYTESWAP | 301 BONITO_BONGENCFG_BYTESWAP; 302 #endif 303 304 set_io_port_base(MALTA_BONITO_PORT_BASE); 305 break; 306 307 case MIPS_REVISION_SCON_SOCIT: 308 case MIPS_REVISION_SCON_ROCIT: 309 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); 310 mips_pci_controller: 311 mb(); 312 MSC_READ(MSC01_PCI_CFG, data); 313 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); 314 wmb(); 315 316 /* Fix up lane swapping. */ 317 #ifdef CONFIG_CPU_LITTLE_ENDIAN 318 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); 319 #else 320 MSC_WRITE(MSC01_PCI_SWAP, 321 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | 322 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | 323 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); 324 #endif 325 /* Fix up target memory mapping. */ 326 MSC_READ(MSC01_PCI_BAR0, mask); 327 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); 328 329 /* Don't handle target retries indefinitely. */ 330 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == 331 MSC01_PCI_CFG_MAXRTRY_MSK) 332 data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << 333 MSC01_PCI_CFG_MAXRTRY_SHF)) | 334 ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << 335 MSC01_PCI_CFG_MAXRTRY_SHF); 336 337 wmb(); 338 MSC_WRITE(MSC01_PCI_CFG, data); 339 mb(); 340 341 set_io_port_base(MALTA_MSC_PORT_BASE); 342 break; 343 344 case MIPS_REVISION_SCON_SOCITSC: 345 case MIPS_REVISION_SCON_SOCITSCP: 346 _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); 347 goto mips_pci_controller; 348 349 default: 350 /* Unknown system controller */ 351 mips_display_message("SC Error"); 352 while (1); /* We die here... */ 353 } 354 board_nmi_handler_setup = mips_nmi_setup; 355 board_ejtag_handler_setup = mips_ejtag_setup; 356 357 prom_init_cmdline(); 358 prom_meminit(); 359 #ifdef CONFIG_SERIAL_8250_CONSOLE 360 console_config(); 361 #endif 362 /* Early detection of CMP support */ 363 if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ)) 364 if (!register_cmp_smp_ops()) 365 return; 366 367 if (!register_vsmp_smp_ops()) 368 return; 369 370 #ifdef CONFIG_MIPS_MT_SMTC 371 register_smp_ops(&msmtc_smp_ops); 372 #endif 373 } 374