1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * PROM library initialisation code. 7 * 8 * Copyright (C) 1999,2000,2004,2005,2012 MIPS Technologies, Inc. 9 * All rights reserved. 10 * Authors: Carsten Langgaard <carstenl@mips.com> 11 * Maciej W. Rozycki <macro@mips.com> 12 * Steven J. Hill <sjhill@mips.com> 13 */ 14 #include <linux/init.h> 15 #include <linux/string.h> 16 #include <linux/kernel.h> 17 #include <linux/serial_8250.h> 18 19 #include <asm/cacheflush.h> 20 #include <asm/smp-ops.h> 21 #include <asm/traps.h> 22 #include <asm/fw/fw.h> 23 #include <asm/gcmpregs.h> 24 #include <asm/mips-boards/generic.h> 25 #include <asm/mips-boards/malta.h> 26 27 static int mips_revision_corid; 28 int mips_revision_sconid; 29 30 /* Bonito64 system controller register base. */ 31 unsigned long _pcictrl_bonito; 32 unsigned long _pcictrl_bonito_pcicfg; 33 34 /* GT64120 system controller register base */ 35 unsigned long _pcictrl_gt64120; 36 37 /* MIPS System controller register base */ 38 unsigned long _pcictrl_msc; 39 40 #ifdef CONFIG_SERIAL_8250_CONSOLE 41 static void __init console_config(void) 42 { 43 char console_string[40]; 44 int baud = 0; 45 char parity = '\0', bits = '\0', flow = '\0'; 46 char *s; 47 48 s = fw_getenv("modetty0"); 49 if (s) { 50 while (*s >= '0' && *s <= '9') 51 baud = baud*10 + *s++ - '0'; 52 if (*s == ',') 53 s++; 54 if (*s) 55 parity = *s++; 56 if (*s == ',') 57 s++; 58 if (*s) 59 bits = *s++; 60 if (*s == ',') 61 s++; 62 if (*s == 'h') 63 flow = 'r'; 64 } 65 if (baud == 0) 66 baud = 38400; 67 if (parity != 'n' && parity != 'o' && parity != 'e') 68 parity = 'n'; 69 if (bits != '7' && bits != '8') 70 bits = '8'; 71 if (flow == '\0') 72 flow = 'r'; 73 74 if ((strstr(fw_getcmdline(), "earlycon=")) == NULL) { 75 sprintf(console_string, "uart8250,io,0x3f8,%d%c%c", baud, 76 parity, bits); 77 setup_early_serial8250_console(console_string); 78 } 79 80 if ((strstr(fw_getcmdline(), "console=")) == NULL) { 81 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, 82 parity, bits, flow); 83 strcat(fw_getcmdline(), console_string); 84 pr_info("Config serial console:%s\n", console_string); 85 } 86 } 87 #endif 88 89 static void __init mips_nmi_setup(void) 90 { 91 void *base; 92 extern char except_vec_nmi; 93 94 base = cpu_has_veic ? 95 (void *)(CAC_BASE + 0xa80) : 96 (void *)(CAC_BASE + 0x380); 97 memcpy(base, &except_vec_nmi, 0x80); 98 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 99 } 100 101 static void __init mips_ejtag_setup(void) 102 { 103 void *base; 104 extern char except_vec_ejtag_debug; 105 106 base = cpu_has_veic ? 107 (void *)(CAC_BASE + 0xa00) : 108 (void *)(CAC_BASE + 0x300); 109 memcpy(base, &except_vec_ejtag_debug, 0x80); 110 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 111 } 112 113 extern struct plat_smp_ops msmtc_smp_ops; 114 115 void __init prom_init(void) 116 { 117 mips_display_message("LINUX"); 118 119 /* 120 * early setup of _pcictrl_bonito so that we can determine 121 * the system controller on a CORE_EMUL board 122 */ 123 _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); 124 125 mips_revision_corid = MIPS_REVISION_CORID; 126 127 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { 128 if (BONITO_PCIDID == 0x0001df53 || 129 BONITO_PCIDID == 0x0003df53) 130 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; 131 else 132 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; 133 } 134 135 mips_revision_sconid = MIPS_REVISION_SCONID; 136 if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { 137 switch (mips_revision_corid) { 138 case MIPS_REVISION_CORID_QED_RM5261: 139 case MIPS_REVISION_CORID_CORE_LV: 140 case MIPS_REVISION_CORID_CORE_FPGA: 141 case MIPS_REVISION_CORID_CORE_FPGAR2: 142 mips_revision_sconid = MIPS_REVISION_SCON_GT64120; 143 break; 144 case MIPS_REVISION_CORID_CORE_EMUL_BON: 145 case MIPS_REVISION_CORID_BONITO64: 146 case MIPS_REVISION_CORID_CORE_20K: 147 mips_revision_sconid = MIPS_REVISION_SCON_BONITO; 148 break; 149 case MIPS_REVISION_CORID_CORE_MSC: 150 case MIPS_REVISION_CORID_CORE_FPGA2: 151 case MIPS_REVISION_CORID_CORE_24K: 152 /* 153 * SOCit/ROCit support is essentially identical 154 * but make an attempt to distinguish them 155 */ 156 mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; 157 break; 158 case MIPS_REVISION_CORID_CORE_FPGA3: 159 case MIPS_REVISION_CORID_CORE_FPGA4: 160 case MIPS_REVISION_CORID_CORE_FPGA5: 161 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 162 default: 163 /* See above */ 164 mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; 165 break; 166 } 167 } 168 169 switch (mips_revision_sconid) { 170 u32 start, map, mask, data; 171 172 case MIPS_REVISION_SCON_GT64120: 173 /* 174 * Setup the North bridge to do Master byte-lane swapping 175 * when running in bigendian. 176 */ 177 _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); 178 179 #ifdef CONFIG_CPU_LITTLE_ENDIAN 180 GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | 181 GT_PCI0_CMD_SBYTESWAP_BIT); 182 #else 183 GT_WRITE(GT_PCI0_CMD_OFS, 0); 184 #endif 185 /* Fix up PCI I/O mapping if necessary (for Atlas). */ 186 start = GT_READ(GT_PCI0IOLD_OFS); 187 map = GT_READ(GT_PCI0IOREMAP_OFS); 188 if ((start & map) != 0) { 189 map &= ~start; 190 GT_WRITE(GT_PCI0IOREMAP_OFS, map); 191 } 192 193 set_io_port_base(MALTA_GT_PORT_BASE); 194 break; 195 196 case MIPS_REVISION_SCON_BONITO: 197 _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); 198 199 /* 200 * Disable Bonito IOBC. 201 */ 202 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & 203 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 204 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 205 206 /* 207 * Setup the North bridge to do Master byte-lane swapping 208 * when running in bigendian. 209 */ 210 #ifdef CONFIG_CPU_LITTLE_ENDIAN 211 BONITO_BONGENCFG = BONITO_BONGENCFG & 212 ~(BONITO_BONGENCFG_MSTRBYTESWAP | 213 BONITO_BONGENCFG_BYTESWAP); 214 #else 215 BONITO_BONGENCFG = BONITO_BONGENCFG | 216 BONITO_BONGENCFG_MSTRBYTESWAP | 217 BONITO_BONGENCFG_BYTESWAP; 218 #endif 219 220 set_io_port_base(MALTA_BONITO_PORT_BASE); 221 break; 222 223 case MIPS_REVISION_SCON_SOCIT: 224 case MIPS_REVISION_SCON_ROCIT: 225 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); 226 mips_pci_controller: 227 mb(); 228 MSC_READ(MSC01_PCI_CFG, data); 229 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); 230 wmb(); 231 232 /* Fix up lane swapping. */ 233 #ifdef CONFIG_CPU_LITTLE_ENDIAN 234 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); 235 #else 236 MSC_WRITE(MSC01_PCI_SWAP, 237 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | 238 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | 239 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); 240 #endif 241 /* Fix up target memory mapping. */ 242 MSC_READ(MSC01_PCI_BAR0, mask); 243 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); 244 245 /* Don't handle target retries indefinitely. */ 246 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == 247 MSC01_PCI_CFG_MAXRTRY_MSK) 248 data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << 249 MSC01_PCI_CFG_MAXRTRY_SHF)) | 250 ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << 251 MSC01_PCI_CFG_MAXRTRY_SHF); 252 253 wmb(); 254 MSC_WRITE(MSC01_PCI_CFG, data); 255 mb(); 256 257 set_io_port_base(MALTA_MSC_PORT_BASE); 258 break; 259 260 case MIPS_REVISION_SCON_SOCITSC: 261 case MIPS_REVISION_SCON_SOCITSCP: 262 _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); 263 goto mips_pci_controller; 264 265 default: 266 /* Unknown system controller */ 267 mips_display_message("SC Error"); 268 while (1); /* We die here... */ 269 } 270 board_nmi_handler_setup = mips_nmi_setup; 271 board_ejtag_handler_setup = mips_ejtag_setup; 272 273 fw_init_cmdline(); 274 fw_meminit(); 275 #ifdef CONFIG_SERIAL_8250_CONSOLE 276 console_config(); 277 #endif 278 /* Early detection of CMP support */ 279 if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ)) 280 if (!register_cmp_smp_ops()) 281 return; 282 283 if (!register_vsmp_smp_ops()) 284 return; 285 286 #ifdef CONFIG_MIPS_MT_SMTC 287 register_smp_ops(&msmtc_smp_ops); 288 #endif 289 } 290