1 /* 2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. 3 * All rights reserved. 4 * Authors: Carsten Langgaard <carstenl@mips.com> 5 * Maciej W. Rozycki <macro@mips.com> 6 * 7 * This program is free software; you can distribute it and/or modify it 8 * under the terms of the GNU General Public License (Version 2) as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 19 * 20 * PROM library initialisation code. 21 */ 22 #include <linux/init.h> 23 #include <linux/string.h> 24 #include <linux/kernel.h> 25 26 #include <asm/bootinfo.h> 27 #include <asm/gt64120.h> 28 #include <asm/io.h> 29 #include <asm/system.h> 30 #include <asm/cacheflush.h> 31 #include <asm/traps.h> 32 33 #include <asm/gcmpregs.h> 34 #include <asm/mips-boards/prom.h> 35 #include <asm/mips-boards/generic.h> 36 #include <asm/mips-boards/bonito64.h> 37 #include <asm/mips-boards/msc01_pci.h> 38 39 #include <asm/mips-boards/malta.h> 40 41 int prom_argc; 42 int *_prom_argv, *_prom_envp; 43 44 /* 45 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. 46 * This macro take care of sign extension, if running in 64-bit mode. 47 */ 48 #define prom_envp(index) ((char *)(long)_prom_envp[(index)]) 49 50 int init_debug; 51 52 static int mips_revision_corid; 53 int mips_revision_sconid; 54 55 /* Bonito64 system controller register base. */ 56 unsigned long _pcictrl_bonito; 57 unsigned long _pcictrl_bonito_pcicfg; 58 59 /* GT64120 system controller register base */ 60 unsigned long _pcictrl_gt64120; 61 62 /* MIPS System controller register base */ 63 unsigned long _pcictrl_msc; 64 65 char *prom_getenv(char *envname) 66 { 67 /* 68 * Return a pointer to the given environment variable. 69 * In 64-bit mode: we're using 64-bit pointers, but all pointers 70 * in the PROM structures are only 32-bit, so we need some 71 * workarounds, if we are running in 64-bit mode. 72 */ 73 int i, index=0; 74 75 i = strlen(envname); 76 77 while (prom_envp(index)) { 78 if(strncmp(envname, prom_envp(index), i) == 0) { 79 return(prom_envp(index+1)); 80 } 81 index += 2; 82 } 83 84 return NULL; 85 } 86 87 static inline unsigned char str2hexnum(unsigned char c) 88 { 89 if (c >= '0' && c <= '9') 90 return c - '0'; 91 if (c >= 'a' && c <= 'f') 92 return c - 'a' + 10; 93 return 0; /* foo */ 94 } 95 96 static inline void str2eaddr(unsigned char *ea, unsigned char *str) 97 { 98 int i; 99 100 for (i = 0; i < 6; i++) { 101 unsigned char num; 102 103 if((*str == '.') || (*str == ':')) 104 str++; 105 num = str2hexnum(*str++) << 4; 106 num |= (str2hexnum(*str++)); 107 ea[i] = num; 108 } 109 } 110 111 int get_ethernet_addr(char *ethernet_addr) 112 { 113 char *ethaddr_str; 114 115 ethaddr_str = prom_getenv("ethaddr"); 116 if (!ethaddr_str) { 117 printk("ethaddr not set in boot prom\n"); 118 return -1; 119 } 120 str2eaddr(ethernet_addr, ethaddr_str); 121 122 if (init_debug > 1) { 123 int i; 124 printk("get_ethernet_addr: "); 125 for (i=0; i<5; i++) 126 printk("%02x:", (unsigned char)*(ethernet_addr+i)); 127 printk("%02x\n", *(ethernet_addr+i)); 128 } 129 130 return 0; 131 } 132 133 #ifdef CONFIG_SERIAL_8250_CONSOLE 134 static void __init console_config(void) 135 { 136 char console_string[40]; 137 int baud = 0; 138 char parity = '\0', bits = '\0', flow = '\0'; 139 char *s; 140 141 if ((strstr(prom_getcmdline(), "console=")) == NULL) { 142 s = prom_getenv("modetty0"); 143 if (s) { 144 while (*s >= '0' && *s <= '9') 145 baud = baud*10 + *s++ - '0'; 146 if (*s == ',') s++; 147 if (*s) parity = *s++; 148 if (*s == ',') s++; 149 if (*s) bits = *s++; 150 if (*s == ',') s++; 151 if (*s == 'h') flow = 'r'; 152 } 153 if (baud == 0) 154 baud = 38400; 155 if (parity != 'n' && parity != 'o' && parity != 'e') 156 parity = 'n'; 157 if (bits != '7' && bits != '8') 158 bits = '8'; 159 if (flow == '\0') 160 flow = 'r'; 161 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); 162 strcat(prom_getcmdline(), console_string); 163 pr_info("Config serial console:%s\n", console_string); 164 } 165 } 166 #endif 167 168 static void __init mips_nmi_setup(void) 169 { 170 void *base; 171 extern char except_vec_nmi; 172 173 base = cpu_has_veic ? 174 (void *)(CAC_BASE + 0xa80) : 175 (void *)(CAC_BASE + 0x380); 176 memcpy(base, &except_vec_nmi, 0x80); 177 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 178 } 179 180 static void __init mips_ejtag_setup(void) 181 { 182 void *base; 183 extern char except_vec_ejtag_debug; 184 185 base = cpu_has_veic ? 186 (void *)(CAC_BASE + 0xa00) : 187 (void *)(CAC_BASE + 0x300); 188 memcpy(base, &except_vec_ejtag_debug, 0x80); 189 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 190 } 191 192 extern struct plat_smp_ops msmtc_smp_ops; 193 194 void __init prom_init(void) 195 { 196 int result; 197 198 prom_argc = fw_arg0; 199 _prom_argv = (int *) fw_arg1; 200 _prom_envp = (int *) fw_arg2; 201 202 mips_display_message("LINUX"); 203 204 /* 205 * early setup of _pcictrl_bonito so that we can determine 206 * the system controller on a CORE_EMUL board 207 */ 208 _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); 209 210 mips_revision_corid = MIPS_REVISION_CORID; 211 212 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { 213 if (BONITO_PCIDID == 0x0001df53 || 214 BONITO_PCIDID == 0x0003df53) 215 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; 216 else 217 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; 218 } 219 220 mips_revision_sconid = MIPS_REVISION_SCONID; 221 if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { 222 switch (mips_revision_corid) { 223 case MIPS_REVISION_CORID_QED_RM5261: 224 case MIPS_REVISION_CORID_CORE_LV: 225 case MIPS_REVISION_CORID_CORE_FPGA: 226 case MIPS_REVISION_CORID_CORE_FPGAR2: 227 mips_revision_sconid = MIPS_REVISION_SCON_GT64120; 228 break; 229 case MIPS_REVISION_CORID_CORE_EMUL_BON: 230 case MIPS_REVISION_CORID_BONITO64: 231 case MIPS_REVISION_CORID_CORE_20K: 232 mips_revision_sconid = MIPS_REVISION_SCON_BONITO; 233 break; 234 case MIPS_REVISION_CORID_CORE_MSC: 235 case MIPS_REVISION_CORID_CORE_FPGA2: 236 case MIPS_REVISION_CORID_CORE_24K: 237 /* 238 * SOCit/ROCit support is essentially identical 239 * but make an attempt to distinguish them 240 */ 241 mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; 242 break; 243 case MIPS_REVISION_CORID_CORE_FPGA3: 244 case MIPS_REVISION_CORID_CORE_FPGA4: 245 case MIPS_REVISION_CORID_CORE_FPGA5: 246 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 247 default: 248 /* See above */ 249 mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; 250 break; 251 } 252 } 253 254 switch (mips_revision_sconid) { 255 u32 start, map, mask, data; 256 257 case MIPS_REVISION_SCON_GT64120: 258 /* 259 * Setup the North bridge to do Master byte-lane swapping 260 * when running in bigendian. 261 */ 262 _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); 263 264 #ifdef CONFIG_CPU_LITTLE_ENDIAN 265 GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | 266 GT_PCI0_CMD_SBYTESWAP_BIT); 267 #else 268 GT_WRITE(GT_PCI0_CMD_OFS, 0); 269 #endif 270 /* Fix up PCI I/O mapping if necessary (for Atlas). */ 271 start = GT_READ(GT_PCI0IOLD_OFS); 272 map = GT_READ(GT_PCI0IOREMAP_OFS); 273 if ((start & map) != 0) { 274 map &= ~start; 275 GT_WRITE(GT_PCI0IOREMAP_OFS, map); 276 } 277 278 set_io_port_base(MALTA_GT_PORT_BASE); 279 break; 280 281 case MIPS_REVISION_SCON_BONITO: 282 _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); 283 284 /* 285 * Disable Bonito IOBC. 286 */ 287 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & 288 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 289 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 290 291 /* 292 * Setup the North bridge to do Master byte-lane swapping 293 * when running in bigendian. 294 */ 295 #ifdef CONFIG_CPU_LITTLE_ENDIAN 296 BONITO_BONGENCFG = BONITO_BONGENCFG & 297 ~(BONITO_BONGENCFG_MSTRBYTESWAP | 298 BONITO_BONGENCFG_BYTESWAP); 299 #else 300 BONITO_BONGENCFG = BONITO_BONGENCFG | 301 BONITO_BONGENCFG_MSTRBYTESWAP | 302 BONITO_BONGENCFG_BYTESWAP; 303 #endif 304 305 set_io_port_base(MALTA_BONITO_PORT_BASE); 306 break; 307 308 case MIPS_REVISION_SCON_SOCIT: 309 case MIPS_REVISION_SCON_ROCIT: 310 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); 311 mips_pci_controller: 312 mb(); 313 MSC_READ(MSC01_PCI_CFG, data); 314 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); 315 wmb(); 316 317 /* Fix up lane swapping. */ 318 #ifdef CONFIG_CPU_LITTLE_ENDIAN 319 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); 320 #else 321 MSC_WRITE(MSC01_PCI_SWAP, 322 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | 323 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | 324 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); 325 #endif 326 /* Fix up target memory mapping. */ 327 MSC_READ(MSC01_PCI_BAR0, mask); 328 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); 329 330 /* Don't handle target retries indefinitely. */ 331 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == 332 MSC01_PCI_CFG_MAXRTRY_MSK) 333 data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << 334 MSC01_PCI_CFG_MAXRTRY_SHF)) | 335 ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << 336 MSC01_PCI_CFG_MAXRTRY_SHF); 337 338 wmb(); 339 MSC_WRITE(MSC01_PCI_CFG, data); 340 mb(); 341 342 set_io_port_base(MALTA_MSC_PORT_BASE); 343 break; 344 345 case MIPS_REVISION_SCON_SOCITSC: 346 case MIPS_REVISION_SCON_SOCITSCP: 347 _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); 348 goto mips_pci_controller; 349 350 default: 351 /* Unknown system controller */ 352 mips_display_message("SC Error"); 353 while (1); /* We die here... */ 354 } 355 board_nmi_handler_setup = mips_nmi_setup; 356 board_ejtag_handler_setup = mips_ejtag_setup; 357 358 pr_info("\nLINUX started...\n"); 359 prom_init_cmdline(); 360 prom_meminit(); 361 #ifdef CONFIG_SERIAL_8250_CONSOLE 362 console_config(); 363 #endif 364 /* Early detection of CMP support */ 365 result = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); 366 367 #ifdef CONFIG_MIPS_CMP 368 if (result) 369 register_smp_ops(&cmp_smp_ops); 370 #endif 371 #ifdef CONFIG_MIPS_MT_SMP 372 #ifdef CONFIG_MIPS_CMP 373 if (!result) 374 register_smp_ops(&vsmp_smp_ops); 375 #else 376 register_smp_ops(&vsmp_smp_ops); 377 #endif 378 #endif 379 #ifdef CONFIG_MIPS_MT_SMTC 380 register_smp_ops(&msmtc_smp_ops); 381 #endif 382 } 383