1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * A small micro-assembler. It is intentionally kept simple, does only 7 * support a subset of instructions, and does not try to hide pipeline 8 * effects like branch delay slots. 9 * 10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 11 * Copyright (C) 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. 14 */ 15 16 enum fields { 17 RS = 0x001, 18 RT = 0x002, 19 RD = 0x004, 20 RE = 0x008, 21 SIMM = 0x010, 22 UIMM = 0x020, 23 BIMM = 0x040, 24 JIMM = 0x080, 25 FUNC = 0x100, 26 SET = 0x200, 27 SCIMM = 0x400, 28 SIMM9 = 0x800, 29 }; 30 31 #define OP_MASK 0x3f 32 #define OP_SH 26 33 #define RD_MASK 0x1f 34 #define RD_SH 11 35 #define RE_MASK 0x1f 36 #define RE_SH 6 37 #define IMM_MASK 0xffff 38 #define IMM_SH 0 39 #define JIMM_MASK 0x3ffffff 40 #define JIMM_SH 0 41 #define FUNC_MASK 0x3f 42 #define FUNC_SH 0 43 #define SET_MASK 0x7 44 #define SET_SH 0 45 #define SIMM9_SH 7 46 #define SIMM9_MASK 0x1ff 47 48 enum opcode { 49 insn_invalid, 50 insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1, 51 insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 52 insn_bne, insn_cache, insn_cfc1, insn_cfcmsa, insn_ctc1, insn_ctcmsa, 53 insn_daddiu, insn_daddu, insn_di, insn_dins, insn_dinsm, insn_divu, 54 insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll, 55 insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, 56 insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, 57 insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, 58 insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0, 59 insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_or, insn_ori, 60 insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, 61 insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra, insn_srl, 62 insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, 63 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor, 64 insn_xori, insn_yield, insn_lddir, insn_ldpte, insn_lhu, 65 }; 66 67 struct insn { 68 enum opcode opcode; 69 u32 match; 70 enum fields fields; 71 }; 72 73 static inline u32 build_rs(u32 arg) 74 { 75 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 76 77 return (arg & RS_MASK) << RS_SH; 78 } 79 80 static inline u32 build_rt(u32 arg) 81 { 82 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 83 84 return (arg & RT_MASK) << RT_SH; 85 } 86 87 static inline u32 build_rd(u32 arg) 88 { 89 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 90 91 return (arg & RD_MASK) << RD_SH; 92 } 93 94 static inline u32 build_re(u32 arg) 95 { 96 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 97 98 return (arg & RE_MASK) << RE_SH; 99 } 100 101 static inline u32 build_simm(s32 arg) 102 { 103 WARN(arg > 0x7fff || arg < -0x8000, 104 KERN_WARNING "Micro-assembler field overflow\n"); 105 106 return arg & 0xffff; 107 } 108 109 static inline u32 build_uimm(u32 arg) 110 { 111 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 112 113 return arg & IMM_MASK; 114 } 115 116 static inline u32 build_scimm(u32 arg) 117 { 118 WARN(arg & ~SCIMM_MASK, 119 KERN_WARNING "Micro-assembler field overflow\n"); 120 121 return (arg & SCIMM_MASK) << SCIMM_SH; 122 } 123 124 static inline u32 build_scimm9(s32 arg) 125 { 126 WARN((arg > 0xff || arg < -0x100), 127 KERN_WARNING "Micro-assembler field overflow\n"); 128 129 return (arg & SIMM9_MASK) << SIMM9_SH; 130 } 131 132 static inline u32 build_func(u32 arg) 133 { 134 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 135 136 return arg & FUNC_MASK; 137 } 138 139 static inline u32 build_set(u32 arg) 140 { 141 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 142 143 return arg & SET_MASK; 144 } 145 146 static void build_insn(u32 **buf, enum opcode opc, ...); 147 148 #define I_u1u2u3(op) \ 149 Ip_u1u2u3(op) \ 150 { \ 151 build_insn(buf, insn##op, a, b, c); \ 152 } \ 153 UASM_EXPORT_SYMBOL(uasm_i##op); 154 155 #define I_s3s1s2(op) \ 156 Ip_s3s1s2(op) \ 157 { \ 158 build_insn(buf, insn##op, b, c, a); \ 159 } \ 160 UASM_EXPORT_SYMBOL(uasm_i##op); 161 162 #define I_u2u1u3(op) \ 163 Ip_u2u1u3(op) \ 164 { \ 165 build_insn(buf, insn##op, b, a, c); \ 166 } \ 167 UASM_EXPORT_SYMBOL(uasm_i##op); 168 169 #define I_u3u2u1(op) \ 170 Ip_u3u2u1(op) \ 171 { \ 172 build_insn(buf, insn##op, c, b, a); \ 173 } \ 174 UASM_EXPORT_SYMBOL(uasm_i##op); 175 176 #define I_u3u1u2(op) \ 177 Ip_u3u1u2(op) \ 178 { \ 179 build_insn(buf, insn##op, b, c, a); \ 180 } \ 181 UASM_EXPORT_SYMBOL(uasm_i##op); 182 183 #define I_u1u2s3(op) \ 184 Ip_u1u2s3(op) \ 185 { \ 186 build_insn(buf, insn##op, a, b, c); \ 187 } \ 188 UASM_EXPORT_SYMBOL(uasm_i##op); 189 190 #define I_u2s3u1(op) \ 191 Ip_u2s3u1(op) \ 192 { \ 193 build_insn(buf, insn##op, c, a, b); \ 194 } \ 195 UASM_EXPORT_SYMBOL(uasm_i##op); 196 197 #define I_u2u1s3(op) \ 198 Ip_u2u1s3(op) \ 199 { \ 200 build_insn(buf, insn##op, b, a, c); \ 201 } \ 202 UASM_EXPORT_SYMBOL(uasm_i##op); 203 204 #define I_u2u1msbu3(op) \ 205 Ip_u2u1msbu3(op) \ 206 { \ 207 build_insn(buf, insn##op, b, a, c+d-1, c); \ 208 } \ 209 UASM_EXPORT_SYMBOL(uasm_i##op); 210 211 #define I_u2u1msb32u3(op) \ 212 Ip_u2u1msbu3(op) \ 213 { \ 214 build_insn(buf, insn##op, b, a, c+d-33, c); \ 215 } \ 216 UASM_EXPORT_SYMBOL(uasm_i##op); 217 218 #define I_u2u1msbdu3(op) \ 219 Ip_u2u1msbu3(op) \ 220 { \ 221 build_insn(buf, insn##op, b, a, d-1, c); \ 222 } \ 223 UASM_EXPORT_SYMBOL(uasm_i##op); 224 225 #define I_u1u2(op) \ 226 Ip_u1u2(op) \ 227 { \ 228 build_insn(buf, insn##op, a, b); \ 229 } \ 230 UASM_EXPORT_SYMBOL(uasm_i##op); 231 232 #define I_u2u1(op) \ 233 Ip_u1u2(op) \ 234 { \ 235 build_insn(buf, insn##op, b, a); \ 236 } \ 237 UASM_EXPORT_SYMBOL(uasm_i##op); 238 239 #define I_u1s2(op) \ 240 Ip_u1s2(op) \ 241 { \ 242 build_insn(buf, insn##op, a, b); \ 243 } \ 244 UASM_EXPORT_SYMBOL(uasm_i##op); 245 246 #define I_u1(op) \ 247 Ip_u1(op) \ 248 { \ 249 build_insn(buf, insn##op, a); \ 250 } \ 251 UASM_EXPORT_SYMBOL(uasm_i##op); 252 253 #define I_0(op) \ 254 Ip_0(op) \ 255 { \ 256 build_insn(buf, insn##op); \ 257 } \ 258 UASM_EXPORT_SYMBOL(uasm_i##op); 259 260 I_u2u1s3(_addiu) 261 I_u3u1u2(_addu) 262 I_u2u1u3(_andi) 263 I_u3u1u2(_and) 264 I_u1u2s3(_beq) 265 I_u1u2s3(_beql) 266 I_u1s2(_bgez) 267 I_u1s2(_bgezl) 268 I_u1s2(_bltz) 269 I_u1s2(_bltzl) 270 I_u1u2s3(_bne) 271 I_u2s3u1(_cache) 272 I_u1u2(_cfc1) 273 I_u2u1(_cfcmsa) 274 I_u1u2(_ctc1) 275 I_u2u1(_ctcmsa) 276 I_u1u2u3(_dmfc0) 277 I_u1u2u3(_dmtc0) 278 I_u2u1s3(_daddiu) 279 I_u3u1u2(_daddu) 280 I_u1(_di); 281 I_u1u2(_divu) 282 I_u2u1u3(_dsll) 283 I_u2u1u3(_dsll32) 284 I_u2u1u3(_dsra) 285 I_u2u1u3(_dsrl) 286 I_u2u1u3(_dsrl32) 287 I_u2u1u3(_drotr) 288 I_u2u1u3(_drotr32) 289 I_u3u1u2(_dsubu) 290 I_0(_eret) 291 I_u2u1msbdu3(_ext) 292 I_u2u1msbu3(_ins) 293 I_u1(_j) 294 I_u1(_jal) 295 I_u2u1(_jalr) 296 I_u1(_jr) 297 I_u2s3u1(_lb) 298 I_u2s3u1(_ld) 299 I_u2s3u1(_lh) 300 I_u2s3u1(_lhu) 301 I_u2s3u1(_ll) 302 I_u2s3u1(_lld) 303 I_u1s2(_lui) 304 I_u2s3u1(_lw) 305 I_u1u2u3(_mfc0) 306 I_u1u2u3(_mfhc0) 307 I_u1(_mfhi) 308 I_u1(_mflo) 309 I_u1u2u3(_mtc0) 310 I_u1u2u3(_mthc0) 311 I_u1(_mthi) 312 I_u1(_mtlo) 313 I_u3u1u2(_mul) 314 I_u2u1u3(_ori) 315 I_u3u1u2(_or) 316 I_0(_rfe) 317 I_u2s3u1(_sc) 318 I_u2s3u1(_scd) 319 I_u2s3u1(_sd) 320 I_u2u1u3(_sll) 321 I_u3u2u1(_sllv) 322 I_s3s1s2(_slt) 323 I_u2u1s3(_sltiu) 324 I_u3u1u2(_sltu) 325 I_u2u1u3(_sra) 326 I_u2u1u3(_srl) 327 I_u3u2u1(_srlv) 328 I_u2u1u3(_rotr) 329 I_u3u1u2(_subu) 330 I_u2s3u1(_sw) 331 I_u1(_sync) 332 I_0(_tlbp) 333 I_0(_tlbr) 334 I_0(_tlbwi) 335 I_0(_tlbwr) 336 I_u1(_wait); 337 I_u2u1(_wsbh) 338 I_u3u1u2(_xor) 339 I_u2u1u3(_xori) 340 I_u2u1(_yield) 341 I_u2u1msbu3(_dins); 342 I_u2u1msb32u3(_dinsm); 343 I_u1(_syscall); 344 I_u1u2s3(_bbit0); 345 I_u1u2s3(_bbit1); 346 I_u3u1u2(_lwx) 347 I_u3u1u2(_ldx) 348 I_u1u2(_ldpte) 349 I_u2u1u3(_lddir) 350 351 #ifdef CONFIG_CPU_CAVIUM_OCTEON 352 #include <asm/octeon/octeon.h> 353 void uasm_i_pref(u32 **buf, unsigned int a, signed int b, 354 unsigned int c) 355 { 356 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5) 357 /* 358 * As per erratum Core-14449, replace prefetches 0-4, 359 * 6-24 with 'pref 28'. 360 */ 361 build_insn(buf, insn_pref, c, 28, b); 362 else 363 build_insn(buf, insn_pref, c, a, b); 364 } 365 UASM_EXPORT_SYMBOL(uasm_i_pref); 366 #else 367 I_u2s3u1(_pref) 368 #endif 369 370 /* Handle labels. */ 371 void uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) 372 { 373 (*lab)->addr = addr; 374 (*lab)->lab = lid; 375 (*lab)++; 376 } 377 UASM_EXPORT_SYMBOL(uasm_build_label); 378 379 int uasm_in_compat_space_p(long addr) 380 { 381 /* Is this address in 32bit compat space? */ 382 return addr == (int)addr; 383 } 384 UASM_EXPORT_SYMBOL(uasm_in_compat_space_p); 385 386 static int uasm_rel_highest(long val) 387 { 388 #ifdef CONFIG_64BIT 389 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 390 #else 391 return 0; 392 #endif 393 } 394 395 static int uasm_rel_higher(long val) 396 { 397 #ifdef CONFIG_64BIT 398 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 399 #else 400 return 0; 401 #endif 402 } 403 404 int uasm_rel_hi(long val) 405 { 406 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 407 } 408 UASM_EXPORT_SYMBOL(uasm_rel_hi); 409 410 int uasm_rel_lo(long val) 411 { 412 return ((val & 0xffff) ^ 0x8000) - 0x8000; 413 } 414 UASM_EXPORT_SYMBOL(uasm_rel_lo); 415 416 void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr) 417 { 418 if (!uasm_in_compat_space_p(addr)) { 419 uasm_i_lui(buf, rs, uasm_rel_highest(addr)); 420 if (uasm_rel_higher(addr)) 421 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr)); 422 if (uasm_rel_hi(addr)) { 423 uasm_i_dsll(buf, rs, rs, 16); 424 uasm_i_daddiu(buf, rs, rs, 425 uasm_rel_hi(addr)); 426 uasm_i_dsll(buf, rs, rs, 16); 427 } else 428 uasm_i_dsll32(buf, rs, rs, 0); 429 } else 430 uasm_i_lui(buf, rs, uasm_rel_hi(addr)); 431 } 432 UASM_EXPORT_SYMBOL(UASM_i_LA_mostly); 433 434 void UASM_i_LA(u32 **buf, unsigned int rs, long addr) 435 { 436 UASM_i_LA_mostly(buf, rs, addr); 437 if (uasm_rel_lo(addr)) { 438 if (!uasm_in_compat_space_p(addr)) 439 uasm_i_daddiu(buf, rs, rs, 440 uasm_rel_lo(addr)); 441 else 442 uasm_i_addiu(buf, rs, rs, 443 uasm_rel_lo(addr)); 444 } 445 } 446 UASM_EXPORT_SYMBOL(UASM_i_LA); 447 448 /* Handle relocations. */ 449 void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid) 450 { 451 (*rel)->addr = addr; 452 (*rel)->type = R_MIPS_PC16; 453 (*rel)->lab = lid; 454 (*rel)++; 455 } 456 UASM_EXPORT_SYMBOL(uasm_r_mips_pc16); 457 458 static inline void __resolve_relocs(struct uasm_reloc *rel, 459 struct uasm_label *lab); 460 461 void uasm_resolve_relocs(struct uasm_reloc *rel, 462 struct uasm_label *lab) 463 { 464 struct uasm_label *l; 465 466 for (; rel->lab != UASM_LABEL_INVALID; rel++) 467 for (l = lab; l->lab != UASM_LABEL_INVALID; l++) 468 if (rel->lab == l->lab) 469 __resolve_relocs(rel, l); 470 } 471 UASM_EXPORT_SYMBOL(uasm_resolve_relocs); 472 473 void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, 474 long off) 475 { 476 for (; rel->lab != UASM_LABEL_INVALID; rel++) 477 if (rel->addr >= first && rel->addr < end) 478 rel->addr += off; 479 } 480 UASM_EXPORT_SYMBOL(uasm_move_relocs); 481 482 void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, 483 long off) 484 { 485 for (; lab->lab != UASM_LABEL_INVALID; lab++) 486 if (lab->addr >= first && lab->addr < end) 487 lab->addr += off; 488 } 489 UASM_EXPORT_SYMBOL(uasm_move_labels); 490 491 void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, 492 u32 *first, u32 *end, u32 *target) 493 { 494 long off = (long)(target - first); 495 496 memcpy(target, first, (end - first) * sizeof(u32)); 497 498 uasm_move_relocs(rel, first, end, off); 499 uasm_move_labels(lab, first, end, off); 500 } 501 UASM_EXPORT_SYMBOL(uasm_copy_handler); 502 503 int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr) 504 { 505 for (; rel->lab != UASM_LABEL_INVALID; rel++) { 506 if (rel->addr == addr 507 && (rel->type == R_MIPS_PC16 508 || rel->type == R_MIPS_26)) 509 return 1; 510 } 511 512 return 0; 513 } 514 UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay); 515 516 /* Convenience functions for labeled branches. */ 517 void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, 518 int lid) 519 { 520 uasm_r_mips_pc16(r, *p, lid); 521 uasm_i_bltz(p, reg, 0); 522 } 523 UASM_EXPORT_SYMBOL(uasm_il_bltz); 524 525 void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid) 526 { 527 uasm_r_mips_pc16(r, *p, lid); 528 uasm_i_b(p, 0); 529 } 530 UASM_EXPORT_SYMBOL(uasm_il_b); 531 532 void uasm_il_beq(u32 **p, struct uasm_reloc **r, unsigned int r1, 533 unsigned int r2, int lid) 534 { 535 uasm_r_mips_pc16(r, *p, lid); 536 uasm_i_beq(p, r1, r2, 0); 537 } 538 UASM_EXPORT_SYMBOL(uasm_il_beq); 539 540 void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, 541 int lid) 542 { 543 uasm_r_mips_pc16(r, *p, lid); 544 uasm_i_beqz(p, reg, 0); 545 } 546 UASM_EXPORT_SYMBOL(uasm_il_beqz); 547 548 void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, 549 int lid) 550 { 551 uasm_r_mips_pc16(r, *p, lid); 552 uasm_i_beqzl(p, reg, 0); 553 } 554 UASM_EXPORT_SYMBOL(uasm_il_beqzl); 555 556 void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, 557 unsigned int reg2, int lid) 558 { 559 uasm_r_mips_pc16(r, *p, lid); 560 uasm_i_bne(p, reg1, reg2, 0); 561 } 562 UASM_EXPORT_SYMBOL(uasm_il_bne); 563 564 void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, 565 int lid) 566 { 567 uasm_r_mips_pc16(r, *p, lid); 568 uasm_i_bnez(p, reg, 0); 569 } 570 UASM_EXPORT_SYMBOL(uasm_il_bnez); 571 572 void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, 573 int lid) 574 { 575 uasm_r_mips_pc16(r, *p, lid); 576 uasm_i_bgezl(p, reg, 0); 577 } 578 UASM_EXPORT_SYMBOL(uasm_il_bgezl); 579 580 void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, 581 int lid) 582 { 583 uasm_r_mips_pc16(r, *p, lid); 584 uasm_i_bgez(p, reg, 0); 585 } 586 UASM_EXPORT_SYMBOL(uasm_il_bgez); 587 588 void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg, 589 unsigned int bit, int lid) 590 { 591 uasm_r_mips_pc16(r, *p, lid); 592 uasm_i_bbit0(p, reg, bit, 0); 593 } 594 UASM_EXPORT_SYMBOL(uasm_il_bbit0); 595 596 void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg, 597 unsigned int bit, int lid) 598 { 599 uasm_r_mips_pc16(r, *p, lid); 600 uasm_i_bbit1(p, reg, bit, 0); 601 } 602 UASM_EXPORT_SYMBOL(uasm_il_bbit1); 603