1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * A small micro-assembler. It is intentionally kept simple, does only 7 * support a subset of instructions, and does not try to hide pipeline 8 * effects like branch delay slots. 9 * 10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 11 * Copyright (C) 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. 14 */ 15 16 enum fields { 17 RS = 0x001, 18 RT = 0x002, 19 RD = 0x004, 20 RE = 0x008, 21 SIMM = 0x010, 22 UIMM = 0x020, 23 BIMM = 0x040, 24 JIMM = 0x080, 25 FUNC = 0x100, 26 SET = 0x200, 27 SCIMM = 0x400, 28 SIMM9 = 0x800, 29 }; 30 31 #define OP_MASK 0x3f 32 #define OP_SH 26 33 #define RD_MASK 0x1f 34 #define RD_SH 11 35 #define RE_MASK 0x1f 36 #define RE_SH 6 37 #define IMM_MASK 0xffff 38 #define IMM_SH 0 39 #define JIMM_MASK 0x3ffffff 40 #define JIMM_SH 0 41 #define FUNC_MASK 0x3f 42 #define FUNC_SH 0 43 #define SET_MASK 0x7 44 #define SET_SH 0 45 #define SIMM9_SH 7 46 #define SIMM9_MASK 0x1ff 47 48 enum opcode { 49 insn_invalid, 50 insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1, 51 insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 52 insn_bne, insn_cache, insn_cfc1, insn_cfcmsa, insn_ctc1, insn_ctcmsa, 53 insn_daddiu, insn_daddu, insn_di, insn_dins, insn_dinsm, insn_divu, 54 insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll, 55 insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, 56 insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, 57 insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, 58 insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0, 59 insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_or, insn_ori, 60 insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, 61 insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra, insn_srl, 62 insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, 63 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor, 64 insn_xori, insn_yield, insn_lddir, insn_ldpte, 65 }; 66 67 struct insn { 68 enum opcode opcode; 69 u32 match; 70 enum fields fields; 71 }; 72 73 static inline u32 build_rs(u32 arg) 74 { 75 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 76 77 return (arg & RS_MASK) << RS_SH; 78 } 79 80 static inline u32 build_rt(u32 arg) 81 { 82 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 83 84 return (arg & RT_MASK) << RT_SH; 85 } 86 87 static inline u32 build_rd(u32 arg) 88 { 89 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 90 91 return (arg & RD_MASK) << RD_SH; 92 } 93 94 static inline u32 build_re(u32 arg) 95 { 96 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 97 98 return (arg & RE_MASK) << RE_SH; 99 } 100 101 static inline u32 build_simm(s32 arg) 102 { 103 WARN(arg > 0x7fff || arg < -0x8000, 104 KERN_WARNING "Micro-assembler field overflow\n"); 105 106 return arg & 0xffff; 107 } 108 109 static inline u32 build_uimm(u32 arg) 110 { 111 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 112 113 return arg & IMM_MASK; 114 } 115 116 static inline u32 build_scimm(u32 arg) 117 { 118 WARN(arg & ~SCIMM_MASK, 119 KERN_WARNING "Micro-assembler field overflow\n"); 120 121 return (arg & SCIMM_MASK) << SCIMM_SH; 122 } 123 124 static inline u32 build_scimm9(s32 arg) 125 { 126 WARN((arg > 0xff || arg < -0x100), 127 KERN_WARNING "Micro-assembler field overflow\n"); 128 129 return (arg & SIMM9_MASK) << SIMM9_SH; 130 } 131 132 static inline u32 build_func(u32 arg) 133 { 134 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 135 136 return arg & FUNC_MASK; 137 } 138 139 static inline u32 build_set(u32 arg) 140 { 141 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 142 143 return arg & SET_MASK; 144 } 145 146 static void build_insn(u32 **buf, enum opcode opc, ...); 147 148 #define I_u1u2u3(op) \ 149 Ip_u1u2u3(op) \ 150 { \ 151 build_insn(buf, insn##op, a, b, c); \ 152 } \ 153 UASM_EXPORT_SYMBOL(uasm_i##op); 154 155 #define I_s3s1s2(op) \ 156 Ip_s3s1s2(op) \ 157 { \ 158 build_insn(buf, insn##op, b, c, a); \ 159 } \ 160 UASM_EXPORT_SYMBOL(uasm_i##op); 161 162 #define I_u2u1u3(op) \ 163 Ip_u2u1u3(op) \ 164 { \ 165 build_insn(buf, insn##op, b, a, c); \ 166 } \ 167 UASM_EXPORT_SYMBOL(uasm_i##op); 168 169 #define I_u3u2u1(op) \ 170 Ip_u3u2u1(op) \ 171 { \ 172 build_insn(buf, insn##op, c, b, a); \ 173 } \ 174 UASM_EXPORT_SYMBOL(uasm_i##op); 175 176 #define I_u3u1u2(op) \ 177 Ip_u3u1u2(op) \ 178 { \ 179 build_insn(buf, insn##op, b, c, a); \ 180 } \ 181 UASM_EXPORT_SYMBOL(uasm_i##op); 182 183 #define I_u1u2s3(op) \ 184 Ip_u1u2s3(op) \ 185 { \ 186 build_insn(buf, insn##op, a, b, c); \ 187 } \ 188 UASM_EXPORT_SYMBOL(uasm_i##op); 189 190 #define I_u2s3u1(op) \ 191 Ip_u2s3u1(op) \ 192 { \ 193 build_insn(buf, insn##op, c, a, b); \ 194 } \ 195 UASM_EXPORT_SYMBOL(uasm_i##op); 196 197 #define I_u2u1s3(op) \ 198 Ip_u2u1s3(op) \ 199 { \ 200 build_insn(buf, insn##op, b, a, c); \ 201 } \ 202 UASM_EXPORT_SYMBOL(uasm_i##op); 203 204 #define I_u2u1msbu3(op) \ 205 Ip_u2u1msbu3(op) \ 206 { \ 207 build_insn(buf, insn##op, b, a, c+d-1, c); \ 208 } \ 209 UASM_EXPORT_SYMBOL(uasm_i##op); 210 211 #define I_u2u1msb32u3(op) \ 212 Ip_u2u1msbu3(op) \ 213 { \ 214 build_insn(buf, insn##op, b, a, c+d-33, c); \ 215 } \ 216 UASM_EXPORT_SYMBOL(uasm_i##op); 217 218 #define I_u2u1msbdu3(op) \ 219 Ip_u2u1msbu3(op) \ 220 { \ 221 build_insn(buf, insn##op, b, a, d-1, c); \ 222 } \ 223 UASM_EXPORT_SYMBOL(uasm_i##op); 224 225 #define I_u1u2(op) \ 226 Ip_u1u2(op) \ 227 { \ 228 build_insn(buf, insn##op, a, b); \ 229 } \ 230 UASM_EXPORT_SYMBOL(uasm_i##op); 231 232 #define I_u2u1(op) \ 233 Ip_u1u2(op) \ 234 { \ 235 build_insn(buf, insn##op, b, a); \ 236 } \ 237 UASM_EXPORT_SYMBOL(uasm_i##op); 238 239 #define I_u1s2(op) \ 240 Ip_u1s2(op) \ 241 { \ 242 build_insn(buf, insn##op, a, b); \ 243 } \ 244 UASM_EXPORT_SYMBOL(uasm_i##op); 245 246 #define I_u1(op) \ 247 Ip_u1(op) \ 248 { \ 249 build_insn(buf, insn##op, a); \ 250 } \ 251 UASM_EXPORT_SYMBOL(uasm_i##op); 252 253 #define I_0(op) \ 254 Ip_0(op) \ 255 { \ 256 build_insn(buf, insn##op); \ 257 } \ 258 UASM_EXPORT_SYMBOL(uasm_i##op); 259 260 I_u2u1s3(_addiu) 261 I_u3u1u2(_addu) 262 I_u2u1u3(_andi) 263 I_u3u1u2(_and) 264 I_u1u2s3(_beq) 265 I_u1u2s3(_beql) 266 I_u1s2(_bgez) 267 I_u1s2(_bgezl) 268 I_u1s2(_bltz) 269 I_u1s2(_bltzl) 270 I_u1u2s3(_bne) 271 I_u2s3u1(_cache) 272 I_u1u2(_cfc1) 273 I_u2u1(_cfcmsa) 274 I_u1u2(_ctc1) 275 I_u2u1(_ctcmsa) 276 I_u1u2u3(_dmfc0) 277 I_u1u2u3(_dmtc0) 278 I_u2u1s3(_daddiu) 279 I_u3u1u2(_daddu) 280 I_u1(_di); 281 I_u1u2(_divu) 282 I_u2u1u3(_dsll) 283 I_u2u1u3(_dsll32) 284 I_u2u1u3(_dsra) 285 I_u2u1u3(_dsrl) 286 I_u2u1u3(_dsrl32) 287 I_u2u1u3(_drotr) 288 I_u2u1u3(_drotr32) 289 I_u3u1u2(_dsubu) 290 I_0(_eret) 291 I_u2u1msbdu3(_ext) 292 I_u2u1msbu3(_ins) 293 I_u1(_j) 294 I_u1(_jal) 295 I_u2u1(_jalr) 296 I_u1(_jr) 297 I_u2s3u1(_lb) 298 I_u2s3u1(_ld) 299 I_u2s3u1(_lh) 300 I_u2s3u1(_ll) 301 I_u2s3u1(_lld) 302 I_u1s2(_lui) 303 I_u2s3u1(_lw) 304 I_u1u2u3(_mfc0) 305 I_u1u2u3(_mfhc0) 306 I_u1(_mfhi) 307 I_u1(_mflo) 308 I_u1u2u3(_mtc0) 309 I_u1u2u3(_mthc0) 310 I_u1(_mthi) 311 I_u1(_mtlo) 312 I_u3u1u2(_mul) 313 I_u2u1u3(_ori) 314 I_u3u1u2(_or) 315 I_0(_rfe) 316 I_u2s3u1(_sc) 317 I_u2s3u1(_scd) 318 I_u2s3u1(_sd) 319 I_u2u1u3(_sll) 320 I_u3u2u1(_sllv) 321 I_s3s1s2(_slt) 322 I_u2u1s3(_sltiu) 323 I_u3u1u2(_sltu) 324 I_u2u1u3(_sra) 325 I_u2u1u3(_srl) 326 I_u3u2u1(_srlv) 327 I_u2u1u3(_rotr) 328 I_u3u1u2(_subu) 329 I_u2s3u1(_sw) 330 I_u1(_sync) 331 I_0(_tlbp) 332 I_0(_tlbr) 333 I_0(_tlbwi) 334 I_0(_tlbwr) 335 I_u1(_wait); 336 I_u2u1(_wsbh) 337 I_u3u1u2(_xor) 338 I_u2u1u3(_xori) 339 I_u2u1(_yield) 340 I_u2u1msbu3(_dins); 341 I_u2u1msb32u3(_dinsm); 342 I_u1(_syscall); 343 I_u1u2s3(_bbit0); 344 I_u1u2s3(_bbit1); 345 I_u3u1u2(_lwx) 346 I_u3u1u2(_ldx) 347 I_u1u2(_ldpte) 348 I_u2u1u3(_lddir) 349 350 #ifdef CONFIG_CPU_CAVIUM_OCTEON 351 #include <asm/octeon/octeon.h> 352 void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b, 353 unsigned int c) 354 { 355 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5) 356 /* 357 * As per erratum Core-14449, replace prefetches 0-4, 358 * 6-24 with 'pref 28'. 359 */ 360 build_insn(buf, insn_pref, c, 28, b); 361 else 362 build_insn(buf, insn_pref, c, a, b); 363 } 364 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref)); 365 #else 366 I_u2s3u1(_pref) 367 #endif 368 369 /* Handle labels. */ 370 void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid) 371 { 372 (*lab)->addr = addr; 373 (*lab)->lab = lid; 374 (*lab)++; 375 } 376 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label)); 377 378 int ISAFUNC(uasm_in_compat_space_p)(long addr) 379 { 380 /* Is this address in 32bit compat space? */ 381 return addr == (int)addr; 382 } 383 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p)); 384 385 static int uasm_rel_highest(long val) 386 { 387 #ifdef CONFIG_64BIT 388 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 389 #else 390 return 0; 391 #endif 392 } 393 394 static int uasm_rel_higher(long val) 395 { 396 #ifdef CONFIG_64BIT 397 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 398 #else 399 return 0; 400 #endif 401 } 402 403 int ISAFUNC(uasm_rel_hi)(long val) 404 { 405 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 406 } 407 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi)); 408 409 int ISAFUNC(uasm_rel_lo)(long val) 410 { 411 return ((val & 0xffff) ^ 0x8000) - 0x8000; 412 } 413 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo)); 414 415 void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr) 416 { 417 if (!ISAFUNC(uasm_in_compat_space_p)(addr)) { 418 ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr)); 419 if (uasm_rel_higher(addr)) 420 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr)); 421 if (ISAFUNC(uasm_rel_hi(addr))) { 422 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); 423 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, 424 ISAFUNC(uasm_rel_hi)(addr)); 425 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); 426 } else 427 ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0); 428 } else 429 ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr))); 430 } 431 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly)); 432 433 void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr) 434 { 435 ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr); 436 if (ISAFUNC(uasm_rel_lo(addr))) { 437 if (!ISAFUNC(uasm_in_compat_space_p)(addr)) 438 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, 439 ISAFUNC(uasm_rel_lo(addr))); 440 else 441 ISAFUNC(uasm_i_addiu)(buf, rs, rs, 442 ISAFUNC(uasm_rel_lo(addr))); 443 } 444 } 445 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA)); 446 447 /* Handle relocations. */ 448 void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid) 449 { 450 (*rel)->addr = addr; 451 (*rel)->type = R_MIPS_PC16; 452 (*rel)->lab = lid; 453 (*rel)++; 454 } 455 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16)); 456 457 static inline void __resolve_relocs(struct uasm_reloc *rel, 458 struct uasm_label *lab); 459 460 void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel, 461 struct uasm_label *lab) 462 { 463 struct uasm_label *l; 464 465 for (; rel->lab != UASM_LABEL_INVALID; rel++) 466 for (l = lab; l->lab != UASM_LABEL_INVALID; l++) 467 if (rel->lab == l->lab) 468 __resolve_relocs(rel, l); 469 } 470 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs)); 471 472 void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end, 473 long off) 474 { 475 for (; rel->lab != UASM_LABEL_INVALID; rel++) 476 if (rel->addr >= first && rel->addr < end) 477 rel->addr += off; 478 } 479 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs)); 480 481 void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end, 482 long off) 483 { 484 for (; lab->lab != UASM_LABEL_INVALID; lab++) 485 if (lab->addr >= first && lab->addr < end) 486 lab->addr += off; 487 } 488 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels)); 489 490 void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab, 491 u32 *first, u32 *end, u32 *target) 492 { 493 long off = (long)(target - first); 494 495 memcpy(target, first, (end - first) * sizeof(u32)); 496 497 ISAFUNC(uasm_move_relocs(rel, first, end, off)); 498 ISAFUNC(uasm_move_labels(lab, first, end, off)); 499 } 500 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler)); 501 502 int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr) 503 { 504 for (; rel->lab != UASM_LABEL_INVALID; rel++) { 505 if (rel->addr == addr 506 && (rel->type == R_MIPS_PC16 507 || rel->type == R_MIPS_26)) 508 return 1; 509 } 510 511 return 0; 512 } 513 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay)); 514 515 /* Convenience functions for labeled branches. */ 516 void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg, 517 int lid) 518 { 519 uasm_r_mips_pc16(r, *p, lid); 520 ISAFUNC(uasm_i_bltz)(p, reg, 0); 521 } 522 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz)); 523 524 void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid) 525 { 526 uasm_r_mips_pc16(r, *p, lid); 527 ISAFUNC(uasm_i_b)(p, 0); 528 } 529 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b)); 530 531 void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1, 532 unsigned int r2, int lid) 533 { 534 uasm_r_mips_pc16(r, *p, lid); 535 ISAFUNC(uasm_i_beq)(p, r1, r2, 0); 536 } 537 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq)); 538 539 void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg, 540 int lid) 541 { 542 uasm_r_mips_pc16(r, *p, lid); 543 ISAFUNC(uasm_i_beqz)(p, reg, 0); 544 } 545 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz)); 546 547 void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg, 548 int lid) 549 { 550 uasm_r_mips_pc16(r, *p, lid); 551 ISAFUNC(uasm_i_beqzl)(p, reg, 0); 552 } 553 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl)); 554 555 void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1, 556 unsigned int reg2, int lid) 557 { 558 uasm_r_mips_pc16(r, *p, lid); 559 ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0); 560 } 561 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne)); 562 563 void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg, 564 int lid) 565 { 566 uasm_r_mips_pc16(r, *p, lid); 567 ISAFUNC(uasm_i_bnez)(p, reg, 0); 568 } 569 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez)); 570 571 void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg, 572 int lid) 573 { 574 uasm_r_mips_pc16(r, *p, lid); 575 ISAFUNC(uasm_i_bgezl)(p, reg, 0); 576 } 577 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl)); 578 579 void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg, 580 int lid) 581 { 582 uasm_r_mips_pc16(r, *p, lid); 583 ISAFUNC(uasm_i_bgez)(p, reg, 0); 584 } 585 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez)); 586 587 void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg, 588 unsigned int bit, int lid) 589 { 590 uasm_r_mips_pc16(r, *p, lid); 591 ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0); 592 } 593 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0)); 594 595 void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg, 596 unsigned int bit, int lid) 597 { 598 uasm_r_mips_pc16(r, *p, lid); 599 ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0); 600 } 601 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1)); 602