1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * A small micro-assembler. It is intentionally kept simple, does only 7 * support a subset of instructions, and does not try to hide pipeline 8 * effects like branch delay slots. 9 * 10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 11 * Copyright (C) 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. 14 */ 15 16 enum fields { 17 RS = 0x001, 18 RT = 0x002, 19 RD = 0x004, 20 RE = 0x008, 21 SIMM = 0x010, 22 UIMM = 0x020, 23 BIMM = 0x040, 24 JIMM = 0x080, 25 FUNC = 0x100, 26 SET = 0x200, 27 SCIMM = 0x400 28 }; 29 30 #define OP_MASK 0x3f 31 #define OP_SH 26 32 #define RD_MASK 0x1f 33 #define RD_SH 11 34 #define RE_MASK 0x1f 35 #define RE_SH 6 36 #define IMM_MASK 0xffff 37 #define IMM_SH 0 38 #define JIMM_MASK 0x3ffffff 39 #define JIMM_SH 0 40 #define FUNC_MASK 0x3f 41 #define FUNC_SH 0 42 #define SET_MASK 0x7 43 #define SET_SH 0 44 45 enum opcode { 46 insn_invalid, 47 insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1, 48 insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 49 insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm, 50 insn_divu, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll, 51 insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, 52 insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, 53 insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, 54 insn_lwx, insn_mfc0, insn_mfhi, insn_mflo, insn_mtc0, insn_mul, 55 insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, 56 insn_sd, insn_sll, insn_sllv, insn_sltiu, insn_sltu, insn_sra, 57 insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, 58 insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, 59 insn_xor, insn_xori, insn_yield, 60 }; 61 62 struct insn { 63 enum opcode opcode; 64 u32 match; 65 enum fields fields; 66 }; 67 68 static inline u32 build_rs(u32 arg) 69 { 70 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 71 72 return (arg & RS_MASK) << RS_SH; 73 } 74 75 static inline u32 build_rt(u32 arg) 76 { 77 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 78 79 return (arg & RT_MASK) << RT_SH; 80 } 81 82 static inline u32 build_rd(u32 arg) 83 { 84 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 85 86 return (arg & RD_MASK) << RD_SH; 87 } 88 89 static inline u32 build_re(u32 arg) 90 { 91 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 92 93 return (arg & RE_MASK) << RE_SH; 94 } 95 96 static inline u32 build_simm(s32 arg) 97 { 98 WARN(arg > 0x7fff || arg < -0x8000, 99 KERN_WARNING "Micro-assembler field overflow\n"); 100 101 return arg & 0xffff; 102 } 103 104 static inline u32 build_uimm(u32 arg) 105 { 106 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 107 108 return arg & IMM_MASK; 109 } 110 111 static inline u32 build_scimm(u32 arg) 112 { 113 WARN(arg & ~SCIMM_MASK, 114 KERN_WARNING "Micro-assembler field overflow\n"); 115 116 return (arg & SCIMM_MASK) << SCIMM_SH; 117 } 118 119 static inline u32 build_func(u32 arg) 120 { 121 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 122 123 return arg & FUNC_MASK; 124 } 125 126 static inline u32 build_set(u32 arg) 127 { 128 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 129 130 return arg & SET_MASK; 131 } 132 133 static void build_insn(u32 **buf, enum opcode opc, ...); 134 135 #define I_u1u2u3(op) \ 136 Ip_u1u2u3(op) \ 137 { \ 138 build_insn(buf, insn##op, a, b, c); \ 139 } \ 140 UASM_EXPORT_SYMBOL(uasm_i##op); 141 142 #define I_u2u1u3(op) \ 143 Ip_u2u1u3(op) \ 144 { \ 145 build_insn(buf, insn##op, b, a, c); \ 146 } \ 147 UASM_EXPORT_SYMBOL(uasm_i##op); 148 149 #define I_u3u2u1(op) \ 150 Ip_u3u2u1(op) \ 151 { \ 152 build_insn(buf, insn##op, c, b, a); \ 153 } \ 154 UASM_EXPORT_SYMBOL(uasm_i##op); 155 156 #define I_u3u1u2(op) \ 157 Ip_u3u1u2(op) \ 158 { \ 159 build_insn(buf, insn##op, b, c, a); \ 160 } \ 161 UASM_EXPORT_SYMBOL(uasm_i##op); 162 163 #define I_u1u2s3(op) \ 164 Ip_u1u2s3(op) \ 165 { \ 166 build_insn(buf, insn##op, a, b, c); \ 167 } \ 168 UASM_EXPORT_SYMBOL(uasm_i##op); 169 170 #define I_u2s3u1(op) \ 171 Ip_u2s3u1(op) \ 172 { \ 173 build_insn(buf, insn##op, c, a, b); \ 174 } \ 175 UASM_EXPORT_SYMBOL(uasm_i##op); 176 177 #define I_u2u1s3(op) \ 178 Ip_u2u1s3(op) \ 179 { \ 180 build_insn(buf, insn##op, b, a, c); \ 181 } \ 182 UASM_EXPORT_SYMBOL(uasm_i##op); 183 184 #define I_u2u1msbu3(op) \ 185 Ip_u2u1msbu3(op) \ 186 { \ 187 build_insn(buf, insn##op, b, a, c+d-1, c); \ 188 } \ 189 UASM_EXPORT_SYMBOL(uasm_i##op); 190 191 #define I_u2u1msb32u3(op) \ 192 Ip_u2u1msbu3(op) \ 193 { \ 194 build_insn(buf, insn##op, b, a, c+d-33, c); \ 195 } \ 196 UASM_EXPORT_SYMBOL(uasm_i##op); 197 198 #define I_u2u1msbdu3(op) \ 199 Ip_u2u1msbu3(op) \ 200 { \ 201 build_insn(buf, insn##op, b, a, d-1, c); \ 202 } \ 203 UASM_EXPORT_SYMBOL(uasm_i##op); 204 205 #define I_u1u2(op) \ 206 Ip_u1u2(op) \ 207 { \ 208 build_insn(buf, insn##op, a, b); \ 209 } \ 210 UASM_EXPORT_SYMBOL(uasm_i##op); 211 212 #define I_u2u1(op) \ 213 Ip_u1u2(op) \ 214 { \ 215 build_insn(buf, insn##op, b, a); \ 216 } \ 217 UASM_EXPORT_SYMBOL(uasm_i##op); 218 219 #define I_u1s2(op) \ 220 Ip_u1s2(op) \ 221 { \ 222 build_insn(buf, insn##op, a, b); \ 223 } \ 224 UASM_EXPORT_SYMBOL(uasm_i##op); 225 226 #define I_u1(op) \ 227 Ip_u1(op) \ 228 { \ 229 build_insn(buf, insn##op, a); \ 230 } \ 231 UASM_EXPORT_SYMBOL(uasm_i##op); 232 233 #define I_0(op) \ 234 Ip_0(op) \ 235 { \ 236 build_insn(buf, insn##op); \ 237 } \ 238 UASM_EXPORT_SYMBOL(uasm_i##op); 239 240 I_u2u1s3(_addiu) 241 I_u3u1u2(_addu) 242 I_u2u1u3(_andi) 243 I_u3u1u2(_and) 244 I_u1u2s3(_beq) 245 I_u1u2s3(_beql) 246 I_u1s2(_bgez) 247 I_u1s2(_bgezl) 248 I_u1s2(_bltz) 249 I_u1s2(_bltzl) 250 I_u1u2s3(_bne) 251 I_u2s3u1(_cache) 252 I_u1u2u3(_dmfc0) 253 I_u1u2u3(_dmtc0) 254 I_u2u1s3(_daddiu) 255 I_u3u1u2(_daddu) 256 I_u1u2(_divu) 257 I_u2u1u3(_dsll) 258 I_u2u1u3(_dsll32) 259 I_u2u1u3(_dsra) 260 I_u2u1u3(_dsrl) 261 I_u2u1u3(_dsrl32) 262 I_u2u1u3(_drotr) 263 I_u2u1u3(_drotr32) 264 I_u3u1u2(_dsubu) 265 I_0(_eret) 266 I_u2u1msbdu3(_ext) 267 I_u2u1msbu3(_ins) 268 I_u1(_j) 269 I_u1(_jal) 270 I_u2u1(_jalr) 271 I_u1(_jr) 272 I_u2s3u1(_lb) 273 I_u2s3u1(_ld) 274 I_u2s3u1(_lh) 275 I_u2s3u1(_ll) 276 I_u2s3u1(_lld) 277 I_u1s2(_lui) 278 I_u2s3u1(_lw) 279 I_u1u2u3(_mfc0) 280 I_u1(_mfhi) 281 I_u1(_mflo) 282 I_u1u2u3(_mtc0) 283 I_u3u1u2(_mul) 284 I_u2u1u3(_ori) 285 I_u3u1u2(_or) 286 I_0(_rfe) 287 I_u2s3u1(_sc) 288 I_u2s3u1(_scd) 289 I_u2s3u1(_sd) 290 I_u2u1u3(_sll) 291 I_u3u2u1(_sllv) 292 I_u2u1s3(_sltiu) 293 I_u3u1u2(_sltu) 294 I_u2u1u3(_sra) 295 I_u2u1u3(_srl) 296 I_u3u2u1(_srlv) 297 I_u2u1u3(_rotr) 298 I_u3u1u2(_subu) 299 I_u2s3u1(_sw) 300 I_u1(_sync) 301 I_0(_tlbp) 302 I_0(_tlbr) 303 I_0(_tlbwi) 304 I_0(_tlbwr) 305 I_u1(_wait); 306 I_u2u1(_wsbh) 307 I_u3u1u2(_xor) 308 I_u2u1u3(_xori) 309 I_u2u1(_yield) 310 I_u2u1msbu3(_dins); 311 I_u2u1msb32u3(_dinsm); 312 I_u1(_syscall); 313 I_u1u2s3(_bbit0); 314 I_u1u2s3(_bbit1); 315 I_u3u1u2(_lwx) 316 I_u3u1u2(_ldx) 317 318 #ifdef CONFIG_CPU_CAVIUM_OCTEON 319 #include <asm/octeon/octeon.h> 320 void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b, 321 unsigned int c) 322 { 323 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5) 324 /* 325 * As per erratum Core-14449, replace prefetches 0-4, 326 * 6-24 with 'pref 28'. 327 */ 328 build_insn(buf, insn_pref, c, 28, b); 329 else 330 build_insn(buf, insn_pref, c, a, b); 331 } 332 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref)); 333 #else 334 I_u2s3u1(_pref) 335 #endif 336 337 /* Handle labels. */ 338 void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid) 339 { 340 (*lab)->addr = addr; 341 (*lab)->lab = lid; 342 (*lab)++; 343 } 344 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label)); 345 346 int ISAFUNC(uasm_in_compat_space_p)(long addr) 347 { 348 /* Is this address in 32bit compat space? */ 349 #ifdef CONFIG_64BIT 350 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); 351 #else 352 return 1; 353 #endif 354 } 355 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p)); 356 357 static int uasm_rel_highest(long val) 358 { 359 #ifdef CONFIG_64BIT 360 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 361 #else 362 return 0; 363 #endif 364 } 365 366 static int uasm_rel_higher(long val) 367 { 368 #ifdef CONFIG_64BIT 369 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 370 #else 371 return 0; 372 #endif 373 } 374 375 int ISAFUNC(uasm_rel_hi)(long val) 376 { 377 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 378 } 379 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi)); 380 381 int ISAFUNC(uasm_rel_lo)(long val) 382 { 383 return ((val & 0xffff) ^ 0x8000) - 0x8000; 384 } 385 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo)); 386 387 void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr) 388 { 389 if (!ISAFUNC(uasm_in_compat_space_p)(addr)) { 390 ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr)); 391 if (uasm_rel_higher(addr)) 392 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr)); 393 if (ISAFUNC(uasm_rel_hi(addr))) { 394 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); 395 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, 396 ISAFUNC(uasm_rel_hi)(addr)); 397 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); 398 } else 399 ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0); 400 } else 401 ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr))); 402 } 403 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly)); 404 405 void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr) 406 { 407 ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr); 408 if (ISAFUNC(uasm_rel_lo(addr))) { 409 if (!ISAFUNC(uasm_in_compat_space_p)(addr)) 410 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, 411 ISAFUNC(uasm_rel_lo(addr))); 412 else 413 ISAFUNC(uasm_i_addiu)(buf, rs, rs, 414 ISAFUNC(uasm_rel_lo(addr))); 415 } 416 } 417 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA)); 418 419 /* Handle relocations. */ 420 void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid) 421 { 422 (*rel)->addr = addr; 423 (*rel)->type = R_MIPS_PC16; 424 (*rel)->lab = lid; 425 (*rel)++; 426 } 427 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16)); 428 429 static inline void __resolve_relocs(struct uasm_reloc *rel, 430 struct uasm_label *lab); 431 432 void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel, 433 struct uasm_label *lab) 434 { 435 struct uasm_label *l; 436 437 for (; rel->lab != UASM_LABEL_INVALID; rel++) 438 for (l = lab; l->lab != UASM_LABEL_INVALID; l++) 439 if (rel->lab == l->lab) 440 __resolve_relocs(rel, l); 441 } 442 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs)); 443 444 void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end, 445 long off) 446 { 447 for (; rel->lab != UASM_LABEL_INVALID; rel++) 448 if (rel->addr >= first && rel->addr < end) 449 rel->addr += off; 450 } 451 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs)); 452 453 void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end, 454 long off) 455 { 456 for (; lab->lab != UASM_LABEL_INVALID; lab++) 457 if (lab->addr >= first && lab->addr < end) 458 lab->addr += off; 459 } 460 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels)); 461 462 void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab, 463 u32 *first, u32 *end, u32 *target) 464 { 465 long off = (long)(target - first); 466 467 memcpy(target, first, (end - first) * sizeof(u32)); 468 469 ISAFUNC(uasm_move_relocs(rel, first, end, off)); 470 ISAFUNC(uasm_move_labels(lab, first, end, off)); 471 } 472 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler)); 473 474 int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr) 475 { 476 for (; rel->lab != UASM_LABEL_INVALID; rel++) { 477 if (rel->addr == addr 478 && (rel->type == R_MIPS_PC16 479 || rel->type == R_MIPS_26)) 480 return 1; 481 } 482 483 return 0; 484 } 485 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay)); 486 487 /* Convenience functions for labeled branches. */ 488 void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg, 489 int lid) 490 { 491 uasm_r_mips_pc16(r, *p, lid); 492 ISAFUNC(uasm_i_bltz)(p, reg, 0); 493 } 494 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz)); 495 496 void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid) 497 { 498 uasm_r_mips_pc16(r, *p, lid); 499 ISAFUNC(uasm_i_b)(p, 0); 500 } 501 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b)); 502 503 void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1, 504 unsigned int r2, int lid) 505 { 506 uasm_r_mips_pc16(r, *p, lid); 507 ISAFUNC(uasm_i_beq)(p, r1, r2, 0); 508 } 509 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq)); 510 511 void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg, 512 int lid) 513 { 514 uasm_r_mips_pc16(r, *p, lid); 515 ISAFUNC(uasm_i_beqz)(p, reg, 0); 516 } 517 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz)); 518 519 void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg, 520 int lid) 521 { 522 uasm_r_mips_pc16(r, *p, lid); 523 ISAFUNC(uasm_i_beqzl)(p, reg, 0); 524 } 525 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl)); 526 527 void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1, 528 unsigned int reg2, int lid) 529 { 530 uasm_r_mips_pc16(r, *p, lid); 531 ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0); 532 } 533 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne)); 534 535 void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg, 536 int lid) 537 { 538 uasm_r_mips_pc16(r, *p, lid); 539 ISAFUNC(uasm_i_bnez)(p, reg, 0); 540 } 541 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez)); 542 543 void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg, 544 int lid) 545 { 546 uasm_r_mips_pc16(r, *p, lid); 547 ISAFUNC(uasm_i_bgezl)(p, reg, 0); 548 } 549 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl)); 550 551 void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg, 552 int lid) 553 { 554 uasm_r_mips_pc16(r, *p, lid); 555 ISAFUNC(uasm_i_bgez)(p, reg, 0); 556 } 557 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez)); 558 559 void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg, 560 unsigned int bit, int lid) 561 { 562 uasm_r_mips_pc16(r, *p, lid); 563 ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0); 564 } 565 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0)); 566 567 void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg, 568 unsigned int bit, int lid) 569 { 570 uasm_r_mips_pc16(r, *p, lid); 571 ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0); 572 } 573 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1)); 574