1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * A small micro-assembler. It is intentionally kept simple, does only 7 * support a subset of instructions, and does not try to hide pipeline 8 * effects like branch delay slots. 9 * 10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 11 * Copyright (C) 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/types.h> 18 19 #include <asm/inst.h> 20 #include <asm/elf.h> 21 #include <asm/bugs.h> 22 #define UASM_ISA _UASM_ISA_MICROMIPS 23 #include <asm/uasm.h> 24 25 #define RS_MASK 0x1f 26 #define RS_SH 16 27 #define RT_MASK 0x1f 28 #define RT_SH 21 29 #define SCIMM_MASK 0x3ff 30 #define SCIMM_SH 16 31 32 /* This macro sets the non-variable bits of an instruction. */ 33 #define M(a, b, c, d, e, f) \ 34 ((a) << OP_SH \ 35 | (b) << RT_SH \ 36 | (c) << RS_SH \ 37 | (d) << RD_SH \ 38 | (e) << RE_SH \ 39 | (f) << FUNC_SH) 40 41 /* Define these when we are not the ISA the kernel is being compiled with. */ 42 #ifndef CONFIG_CPU_MICROMIPS 43 #define MM_uasm_i_b(buf, off) ISAOPC(_beq)(buf, 0, 0, off) 44 #define MM_uasm_i_beqz(buf, rs, off) ISAOPC(_beq)(buf, rs, 0, off) 45 #define MM_uasm_i_beqzl(buf, rs, off) ISAOPC(_beql)(buf, rs, 0, off) 46 #define MM_uasm_i_bnez(buf, rs, off) ISAOPC(_bne)(buf, rs, 0, off) 47 #endif 48 49 #include "uasm.c" 50 51 static struct insn insn_table_MM[] = { 52 { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD }, 53 { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, 54 { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD }, 55 { insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, 56 { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 57 { insn_beql, 0, 0 }, 58 { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM }, 59 { insn_bgezl, 0, 0 }, 60 { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM }, 61 { insn_bltzl, 0, 0 }, 62 { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM }, 63 { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM }, 64 { insn_daddu, 0, 0 }, 65 { insn_daddiu, 0, 0 }, 66 { insn_dmfc0, 0, 0 }, 67 { insn_dmtc0, 0, 0 }, 68 { insn_dsll, 0, 0 }, 69 { insn_dsll32, 0, 0 }, 70 { insn_dsra, 0, 0 }, 71 { insn_dsrl, 0, 0 }, 72 { insn_dsrl32, 0, 0 }, 73 { insn_drotr, 0, 0 }, 74 { insn_drotr32, 0, 0 }, 75 { insn_dsubu, 0, 0 }, 76 { insn_eret, M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0 }, 77 { insn_ins, M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE }, 78 { insn_ext, M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE }, 79 { insn_j, M(mm_j32_op, 0, 0, 0, 0, 0), JIMM }, 80 { insn_jal, M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM }, 81 { insn_jr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS }, 82 { insn_ld, 0, 0 }, 83 { insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM }, 84 { insn_lld, 0, 0 }, 85 { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM }, 86 { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, 87 { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD }, 88 { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD }, 89 { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD }, 90 { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, 91 { insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM }, 92 { insn_rfe, 0, 0 }, 93 { insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM }, 94 { insn_scd, 0, 0 }, 95 { insn_sd, 0, 0 }, 96 { insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD }, 97 { insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD }, 98 { insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD }, 99 { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD }, 100 { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD }, 101 { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, 102 { insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 }, 103 { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 }, 104 { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 }, 105 { insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 }, 106 { insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD }, 107 { insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, 108 { insn_dins, 0, 0 }, 109 { insn_dinsm, 0, 0 }, 110 { insn_syscall, M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM}, 111 { insn_bbit0, 0, 0 }, 112 { insn_bbit1, 0, 0 }, 113 { insn_lwx, 0, 0 }, 114 { insn_ldx, 0, 0 }, 115 { insn_invalid, 0, 0 } 116 }; 117 118 #undef M 119 120 static inline u32 build_bimm(s32 arg) 121 { 122 WARN(arg > 0xffff || arg < -0x10000, 123 KERN_WARNING "Micro-assembler field overflow\n"); 124 125 WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); 126 127 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff); 128 } 129 130 static inline u32 build_jimm(u32 arg) 131 { 132 133 WARN(arg & ~((JIMM_MASK << 2) | 1), 134 KERN_WARNING "Micro-assembler field overflow\n"); 135 136 return (arg >> 1) & JIMM_MASK; 137 } 138 139 /* 140 * The order of opcode arguments is implicitly left to right, 141 * starting with RS and ending with FUNC or IMM. 142 */ 143 static void build_insn(u32 **buf, enum opcode opc, ...) 144 { 145 struct insn *ip = NULL; 146 unsigned int i; 147 va_list ap; 148 u32 op; 149 150 for (i = 0; insn_table_MM[i].opcode != insn_invalid; i++) 151 if (insn_table_MM[i].opcode == opc) { 152 ip = &insn_table_MM[i]; 153 break; 154 } 155 156 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) 157 panic("Unsupported Micro-assembler instruction %d", opc); 158 159 op = ip->match; 160 va_start(ap, opc); 161 if (ip->fields & RS) { 162 if (opc == insn_mfc0 || opc == insn_mtc0) 163 op |= build_rt(va_arg(ap, u32)); 164 else 165 op |= build_rs(va_arg(ap, u32)); 166 } 167 if (ip->fields & RT) { 168 if (opc == insn_mfc0 || opc == insn_mtc0) 169 op |= build_rs(va_arg(ap, u32)); 170 else 171 op |= build_rt(va_arg(ap, u32)); 172 } 173 if (ip->fields & RD) 174 op |= build_rd(va_arg(ap, u32)); 175 if (ip->fields & RE) 176 op |= build_re(va_arg(ap, u32)); 177 if (ip->fields & SIMM) 178 op |= build_simm(va_arg(ap, s32)); 179 if (ip->fields & UIMM) 180 op |= build_uimm(va_arg(ap, u32)); 181 if (ip->fields & BIMM) 182 op |= build_bimm(va_arg(ap, s32)); 183 if (ip->fields & JIMM) 184 op |= build_jimm(va_arg(ap, u32)); 185 if (ip->fields & FUNC) 186 op |= build_func(va_arg(ap, u32)); 187 if (ip->fields & SET) 188 op |= build_set(va_arg(ap, u32)); 189 if (ip->fields & SCIMM) 190 op |= build_scimm(va_arg(ap, u32)); 191 va_end(ap); 192 193 #ifdef CONFIG_CPU_LITTLE_ENDIAN 194 **buf = ((op & 0xffff) << 16) | (op >> 16); 195 #else 196 **buf = op; 197 #endif 198 (*buf)++; 199 } 200 201 static inline void 202 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) 203 { 204 long laddr = (long)lab->addr; 205 long raddr = (long)rel->addr; 206 207 switch (rel->type) { 208 case R_MIPS_PC16: 209 #ifdef CONFIG_CPU_LITTLE_ENDIAN 210 *rel->addr |= (build_bimm(laddr - (raddr + 4)) << 16); 211 #else 212 *rel->addr |= build_bimm(laddr - (raddr + 4)); 213 #endif 214 break; 215 216 default: 217 panic("Unsupported Micro-assembler relocation %d", 218 rel->type); 219 } 220 } 221