1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 * Copyright (C) 2008, 2009 Cavium Networks, Inc. 12 * Copyright (C) 2011 MIPS Technologies, Inc. 13 * 14 * ... and the days got worse and worse and now you see 15 * I've gone completely out of my mind. 16 * 17 * They're coming to take me a away haha 18 * they're coming to take me a away hoho hihi haha 19 * to the funny farm where code is beautiful all the time ... 20 * 21 * (Condolences to Napoleon XIV) 22 */ 23 24 #include <linux/bug.h> 25 #include <linux/export.h> 26 #include <linux/kernel.h> 27 #include <linux/types.h> 28 #include <linux/smp.h> 29 #include <linux/string.h> 30 #include <linux/cache.h> 31 32 #include <asm/cacheflush.h> 33 #include <asm/cpu-type.h> 34 #include <asm/pgtable.h> 35 #include <asm/war.h> 36 #include <asm/uasm.h> 37 #include <asm/setup.h> 38 #include <asm/tlbex.h> 39 40 static int mips_xpa_disabled; 41 42 static int __init xpa_disable(char *s) 43 { 44 mips_xpa_disabled = 1; 45 46 return 1; 47 } 48 49 __setup("noxpa", xpa_disable); 50 51 /* 52 * TLB load/store/modify handlers. 53 * 54 * Only the fastpath gets synthesized at runtime, the slowpath for 55 * do_page_fault remains normal asm. 56 */ 57 extern void tlb_do_page_fault_0(void); 58 extern void tlb_do_page_fault_1(void); 59 60 struct work_registers { 61 int r1; 62 int r2; 63 int r3; 64 }; 65 66 struct tlb_reg_save { 67 unsigned long a; 68 unsigned long b; 69 } ____cacheline_aligned_in_smp; 70 71 static struct tlb_reg_save handler_reg_save[NR_CPUS]; 72 73 static inline int r45k_bvahwbug(void) 74 { 75 /* XXX: We should probe for the presence of this bug, but we don't. */ 76 return 0; 77 } 78 79 static inline int r4k_250MHZhwbug(void) 80 { 81 /* XXX: We should probe for the presence of this bug, but we don't. */ 82 return 0; 83 } 84 85 static inline int __maybe_unused bcm1250_m3_war(void) 86 { 87 return BCM1250_M3_WAR; 88 } 89 90 static inline int __maybe_unused r10000_llsc_war(void) 91 { 92 return R10000_LLSC_WAR; 93 } 94 95 static int use_bbit_insns(void) 96 { 97 switch (current_cpu_type()) { 98 case CPU_CAVIUM_OCTEON: 99 case CPU_CAVIUM_OCTEON_PLUS: 100 case CPU_CAVIUM_OCTEON2: 101 case CPU_CAVIUM_OCTEON3: 102 return 1; 103 default: 104 return 0; 105 } 106 } 107 108 static int use_lwx_insns(void) 109 { 110 switch (current_cpu_type()) { 111 case CPU_CAVIUM_OCTEON2: 112 case CPU_CAVIUM_OCTEON3: 113 return 1; 114 default: 115 return 0; 116 } 117 } 118 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ 119 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 120 static bool scratchpad_available(void) 121 { 122 return true; 123 } 124 static int scratchpad_offset(int i) 125 { 126 /* 127 * CVMSEG starts at address -32768 and extends for 128 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. 129 */ 130 i += 1; /* Kernel use starts at the top and works down. */ 131 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; 132 } 133 #else 134 static bool scratchpad_available(void) 135 { 136 return false; 137 } 138 static int scratchpad_offset(int i) 139 { 140 BUG(); 141 /* Really unreachable, but evidently some GCC want this. */ 142 return 0; 143 } 144 #endif 145 /* 146 * Found by experiment: At least some revisions of the 4kc throw under 147 * some circumstances a machine check exception, triggered by invalid 148 * values in the index register. Delaying the tlbp instruction until 149 * after the next branch, plus adding an additional nop in front of 150 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows 151 * why; it's not an issue caused by the core RTL. 152 * 153 */ 154 static int m4kc_tlbp_war(void) 155 { 156 return (current_cpu_data.processor_id & 0xffff00) == 157 (PRID_COMP_MIPS | PRID_IMP_4KC); 158 } 159 160 /* Handle labels (which must be positive integers). */ 161 enum label_id { 162 label_second_part = 1, 163 label_leave, 164 label_vmalloc, 165 label_vmalloc_done, 166 label_tlbw_hazard_0, 167 label_split = label_tlbw_hazard_0 + 8, 168 label_tlbl_goaround1, 169 label_tlbl_goaround2, 170 label_nopage_tlbl, 171 label_nopage_tlbs, 172 label_nopage_tlbm, 173 label_smp_pgtable_change, 174 label_r3000_write_probe_fail, 175 label_large_segbits_fault, 176 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 177 label_tlb_huge_update, 178 #endif 179 }; 180 181 UASM_L_LA(_second_part) 182 UASM_L_LA(_leave) 183 UASM_L_LA(_vmalloc) 184 UASM_L_LA(_vmalloc_done) 185 /* _tlbw_hazard_x is handled differently. */ 186 UASM_L_LA(_split) 187 UASM_L_LA(_tlbl_goaround1) 188 UASM_L_LA(_tlbl_goaround2) 189 UASM_L_LA(_nopage_tlbl) 190 UASM_L_LA(_nopage_tlbs) 191 UASM_L_LA(_nopage_tlbm) 192 UASM_L_LA(_smp_pgtable_change) 193 UASM_L_LA(_r3000_write_probe_fail) 194 UASM_L_LA(_large_segbits_fault) 195 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 196 UASM_L_LA(_tlb_huge_update) 197 #endif 198 199 static int hazard_instance; 200 201 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) 202 { 203 switch (instance) { 204 case 0 ... 7: 205 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); 206 return; 207 default: 208 BUG(); 209 } 210 } 211 212 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) 213 { 214 switch (instance) { 215 case 0 ... 7: 216 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); 217 break; 218 default: 219 BUG(); 220 } 221 } 222 223 /* 224 * pgtable bits are assigned dynamically depending on processor feature 225 * and statically based on kernel configuration. This spits out the actual 226 * values the kernel is using. Required to make sense from disassembled 227 * TLB exception handlers. 228 */ 229 static void output_pgtable_bits_defines(void) 230 { 231 #define pr_define(fmt, ...) \ 232 pr_debug("#define " fmt, ##__VA_ARGS__) 233 234 pr_debug("#include <asm/asm.h>\n"); 235 pr_debug("#include <asm/regdef.h>\n"); 236 pr_debug("\n"); 237 238 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); 239 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); 240 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); 241 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); 242 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); 243 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 244 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); 245 #endif 246 #ifdef _PAGE_NO_EXEC_SHIFT 247 if (cpu_has_rixi) 248 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); 249 #endif 250 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); 251 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); 252 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); 253 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); 254 pr_debug("\n"); 255 } 256 257 static inline void dump_handler(const char *symbol, const u32 *handler, int count) 258 { 259 int i; 260 261 pr_debug("LEAF(%s)\n", symbol); 262 263 pr_debug("\t.set push\n"); 264 pr_debug("\t.set noreorder\n"); 265 266 for (i = 0; i < count; i++) 267 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); 268 269 pr_debug("\t.set\tpop\n"); 270 271 pr_debug("\tEND(%s)\n", symbol); 272 } 273 274 /* The only general purpose registers allowed in TLB handlers. */ 275 #define K0 26 276 #define K1 27 277 278 /* Some CP0 registers */ 279 #define C0_INDEX 0, 0 280 #define C0_ENTRYLO0 2, 0 281 #define C0_TCBIND 2, 2 282 #define C0_ENTRYLO1 3, 0 283 #define C0_CONTEXT 4, 0 284 #define C0_PAGEMASK 5, 0 285 #define C0_PWBASE 5, 5 286 #define C0_PWFIELD 5, 6 287 #define C0_PWSIZE 5, 7 288 #define C0_PWCTL 6, 6 289 #define C0_BADVADDR 8, 0 290 #define C0_PGD 9, 7 291 #define C0_ENTRYHI 10, 0 292 #define C0_EPC 14, 0 293 #define C0_XCONTEXT 20, 0 294 295 #ifdef CONFIG_64BIT 296 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) 297 #else 298 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) 299 #endif 300 301 /* The worst case length of the handler is around 18 instructions for 302 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 303 * Maximum space available is 32 instructions for R3000 and 64 304 * instructions for R4000. 305 * 306 * We deliberately chose a buffer size of 128, so we won't scribble 307 * over anything important on overflow before we panic. 308 */ 309 static u32 tlb_handler[128]; 310 311 /* simply assume worst case size for labels and relocs */ 312 static struct uasm_label labels[128]; 313 static struct uasm_reloc relocs[128]; 314 315 static int check_for_high_segbits; 316 static bool fill_includes_sw_bits; 317 318 static unsigned int kscratch_used_mask; 319 320 static inline int __maybe_unused c0_kscratch(void) 321 { 322 switch (current_cpu_type()) { 323 case CPU_XLP: 324 case CPU_XLR: 325 return 22; 326 default: 327 return 31; 328 } 329 } 330 331 static int allocate_kscratch(void) 332 { 333 int r; 334 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; 335 336 r = ffs(a); 337 338 if (r == 0) 339 return -1; 340 341 r--; /* make it zero based */ 342 343 kscratch_used_mask |= (1 << r); 344 345 return r; 346 } 347 348 static int scratch_reg; 349 int pgd_reg; 350 EXPORT_SYMBOL_GPL(pgd_reg); 351 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; 352 353 static struct work_registers build_get_work_registers(u32 **p) 354 { 355 struct work_registers r; 356 357 if (scratch_reg >= 0) { 358 /* Save in CPU local C0_KScratch? */ 359 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); 360 r.r1 = K0; 361 r.r2 = K1; 362 r.r3 = 1; 363 return r; 364 } 365 366 if (num_possible_cpus() > 1) { 367 /* Get smp_processor_id */ 368 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); 369 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); 370 371 /* handler_reg_save index in K0 */ 372 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); 373 374 UASM_i_LA(p, K1, (long)&handler_reg_save); 375 UASM_i_ADDU(p, K0, K0, K1); 376 } else { 377 UASM_i_LA(p, K0, (long)&handler_reg_save); 378 } 379 /* K0 now points to save area, save $1 and $2 */ 380 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); 381 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); 382 383 r.r1 = K1; 384 r.r2 = 1; 385 r.r3 = 2; 386 return r; 387 } 388 389 static void build_restore_work_registers(u32 **p) 390 { 391 if (scratch_reg >= 0) { 392 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 393 return; 394 } 395 /* K0 already points to save area, restore $1 and $2 */ 396 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); 397 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); 398 } 399 400 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 401 402 /* 403 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, 404 * we cannot do r3000 under these circumstances. 405 * 406 * Declare pgd_current here instead of including mmu_context.h to avoid type 407 * conflicts for tlbmiss_handler_setup_pgd 408 */ 409 extern unsigned long pgd_current[]; 410 411 /* 412 * The R3000 TLB handler is simple. 413 */ 414 static void build_r3000_tlb_refill_handler(void) 415 { 416 long pgdc = (long)pgd_current; 417 u32 *p; 418 419 memset(tlb_handler, 0, sizeof(tlb_handler)); 420 p = tlb_handler; 421 422 uasm_i_mfc0(&p, K0, C0_BADVADDR); 423 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ 424 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); 425 uasm_i_srl(&p, K0, K0, 22); /* load delay */ 426 uasm_i_sll(&p, K0, K0, 2); 427 uasm_i_addu(&p, K1, K1, K0); 428 uasm_i_mfc0(&p, K0, C0_CONTEXT); 429 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ 430 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ 431 uasm_i_addu(&p, K1, K1, K0); 432 uasm_i_lw(&p, K0, 0, K1); 433 uasm_i_nop(&p); /* load delay */ 434 uasm_i_mtc0(&p, K0, C0_ENTRYLO0); 435 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 436 uasm_i_tlbwr(&p); /* cp0 delay */ 437 uasm_i_jr(&p, K1); 438 uasm_i_rfe(&p); /* branch delay */ 439 440 if (p > tlb_handler + 32) 441 panic("TLB refill handler space exceeded"); 442 443 pr_debug("Wrote TLB refill handler (%u instructions).\n", 444 (unsigned int)(p - tlb_handler)); 445 446 memcpy((void *)ebase, tlb_handler, 0x80); 447 local_flush_icache_range(ebase, ebase + 0x80); 448 449 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32); 450 } 451 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 452 453 /* 454 * The R4000 TLB handler is much more complicated. We have two 455 * consecutive handler areas with 32 instructions space each. 456 * Since they aren't used at the same time, we can overflow in the 457 * other one.To keep things simple, we first assume linear space, 458 * then we relocate it to the final handler layout as needed. 459 */ 460 static u32 final_handler[64]; 461 462 /* 463 * Hazards 464 * 465 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 466 * 2. A timing hazard exists for the TLBP instruction. 467 * 468 * stalling_instruction 469 * TLBP 470 * 471 * The JTLB is being read for the TLBP throughout the stall generated by the 472 * previous instruction. This is not really correct as the stalling instruction 473 * can modify the address used to access the JTLB. The failure symptom is that 474 * the TLBP instruction will use an address created for the stalling instruction 475 * and not the address held in C0_ENHI and thus report the wrong results. 476 * 477 * The software work-around is to not allow the instruction preceding the TLBP 478 * to stall - make it an NOP or some other instruction guaranteed not to stall. 479 * 480 * Errata 2 will not be fixed. This errata is also on the R5000. 481 * 482 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 483 */ 484 static void __maybe_unused build_tlb_probe_entry(u32 **p) 485 { 486 switch (current_cpu_type()) { 487 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ 488 case CPU_R4600: 489 case CPU_R4700: 490 case CPU_R5000: 491 case CPU_NEVADA: 492 uasm_i_nop(p); 493 uasm_i_tlbp(p); 494 break; 495 496 default: 497 uasm_i_tlbp(p); 498 break; 499 } 500 } 501 502 void build_tlb_write_entry(u32 **p, struct uasm_label **l, 503 struct uasm_reloc **r, 504 enum tlb_write_entry wmode) 505 { 506 void(*tlbw)(u32 **) = NULL; 507 508 switch (wmode) { 509 case tlb_random: tlbw = uasm_i_tlbwr; break; 510 case tlb_indexed: tlbw = uasm_i_tlbwi; break; 511 } 512 513 if (cpu_has_mips_r2_r6) { 514 if (cpu_has_mips_r2_exec_hazard) 515 uasm_i_ehb(p); 516 tlbw(p); 517 return; 518 } 519 520 switch (current_cpu_type()) { 521 case CPU_R4000PC: 522 case CPU_R4000SC: 523 case CPU_R4000MC: 524 case CPU_R4400PC: 525 case CPU_R4400SC: 526 case CPU_R4400MC: 527 /* 528 * This branch uses up a mtc0 hazard nop slot and saves 529 * two nops after the tlbw instruction. 530 */ 531 uasm_bgezl_hazard(p, r, hazard_instance); 532 tlbw(p); 533 uasm_bgezl_label(l, p, hazard_instance); 534 hazard_instance++; 535 uasm_i_nop(p); 536 break; 537 538 case CPU_R4600: 539 case CPU_R4700: 540 uasm_i_nop(p); 541 tlbw(p); 542 uasm_i_nop(p); 543 break; 544 545 case CPU_R5000: 546 case CPU_NEVADA: 547 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 548 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 549 tlbw(p); 550 break; 551 552 case CPU_R4300: 553 case CPU_5KC: 554 case CPU_TX49XX: 555 case CPU_PR4450: 556 case CPU_XLR: 557 uasm_i_nop(p); 558 tlbw(p); 559 break; 560 561 case CPU_R10000: 562 case CPU_R12000: 563 case CPU_R14000: 564 case CPU_R16000: 565 case CPU_4KC: 566 case CPU_4KEC: 567 case CPU_M14KC: 568 case CPU_M14KEC: 569 case CPU_SB1: 570 case CPU_SB1A: 571 case CPU_4KSC: 572 case CPU_20KC: 573 case CPU_25KF: 574 case CPU_BMIPS32: 575 case CPU_BMIPS3300: 576 case CPU_BMIPS4350: 577 case CPU_BMIPS4380: 578 case CPU_BMIPS5000: 579 case CPU_LOONGSON2: 580 case CPU_LOONGSON3: 581 case CPU_R5500: 582 if (m4kc_tlbp_war()) 583 uasm_i_nop(p); 584 case CPU_ALCHEMY: 585 tlbw(p); 586 break; 587 588 case CPU_RM7000: 589 uasm_i_nop(p); 590 uasm_i_nop(p); 591 uasm_i_nop(p); 592 uasm_i_nop(p); 593 tlbw(p); 594 break; 595 596 case CPU_VR4111: 597 case CPU_VR4121: 598 case CPU_VR4122: 599 case CPU_VR4181: 600 case CPU_VR4181A: 601 uasm_i_nop(p); 602 uasm_i_nop(p); 603 tlbw(p); 604 uasm_i_nop(p); 605 uasm_i_nop(p); 606 break; 607 608 case CPU_VR4131: 609 case CPU_VR4133: 610 case CPU_R5432: 611 uasm_i_nop(p); 612 uasm_i_nop(p); 613 tlbw(p); 614 break; 615 616 case CPU_JZRISC: 617 tlbw(p); 618 uasm_i_nop(p); 619 break; 620 621 default: 622 panic("No TLB refill handler yet (CPU type: %d)", 623 current_cpu_type()); 624 break; 625 } 626 } 627 EXPORT_SYMBOL_GPL(build_tlb_write_entry); 628 629 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, 630 unsigned int reg) 631 { 632 if (_PAGE_GLOBAL_SHIFT == 0) { 633 /* pte_t is already in EntryLo format */ 634 return; 635 } 636 637 if (cpu_has_rixi && _PAGE_NO_EXEC) { 638 if (fill_includes_sw_bits) { 639 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); 640 } else { 641 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); 642 UASM_i_ROTR(p, reg, reg, 643 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); 644 } 645 } else { 646 #ifdef CONFIG_PHYS_ADDR_T_64BIT 647 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); 648 #else 649 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); 650 #endif 651 } 652 } 653 654 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 655 656 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, 657 unsigned int tmp, enum label_id lid, 658 int restore_scratch) 659 { 660 if (restore_scratch) { 661 /* Reset default page size */ 662 if (PM_DEFAULT_MASK >> 16) { 663 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 664 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 665 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 666 uasm_il_b(p, r, lid); 667 } else if (PM_DEFAULT_MASK) { 668 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 669 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 670 uasm_il_b(p, r, lid); 671 } else { 672 uasm_i_mtc0(p, 0, C0_PAGEMASK); 673 uasm_il_b(p, r, lid); 674 } 675 if (scratch_reg >= 0) 676 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 677 else 678 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 679 } else { 680 /* Reset default page size */ 681 if (PM_DEFAULT_MASK >> 16) { 682 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 683 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 684 uasm_il_b(p, r, lid); 685 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 686 } else if (PM_DEFAULT_MASK) { 687 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 688 uasm_il_b(p, r, lid); 689 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 690 } else { 691 uasm_il_b(p, r, lid); 692 uasm_i_mtc0(p, 0, C0_PAGEMASK); 693 } 694 } 695 } 696 697 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, 698 struct uasm_reloc **r, 699 unsigned int tmp, 700 enum tlb_write_entry wmode, 701 int restore_scratch) 702 { 703 /* Set huge page tlb entry size */ 704 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); 705 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); 706 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 707 708 build_tlb_write_entry(p, l, r, wmode); 709 710 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); 711 } 712 713 /* 714 * Check if Huge PTE is present, if so then jump to LABEL. 715 */ 716 static void 717 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, 718 unsigned int pmd, int lid) 719 { 720 UASM_i_LW(p, tmp, 0, pmd); 721 if (use_bbit_insns()) { 722 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); 723 } else { 724 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); 725 uasm_il_bnez(p, r, tmp, lid); 726 } 727 } 728 729 static void build_huge_update_entries(u32 **p, unsigned int pte, 730 unsigned int tmp) 731 { 732 int small_sequence; 733 734 /* 735 * A huge PTE describes an area the size of the 736 * configured huge page size. This is twice the 737 * of the large TLB entry size we intend to use. 738 * A TLB entry half the size of the configured 739 * huge page size is configured into entrylo0 740 * and entrylo1 to cover the contiguous huge PTE 741 * address space. 742 */ 743 small_sequence = (HPAGE_SIZE >> 7) < 0x10000; 744 745 /* We can clobber tmp. It isn't used after this.*/ 746 if (!small_sequence) 747 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); 748 749 build_convert_pte_to_entrylo(p, pte); 750 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ 751 /* convert to entrylo1 */ 752 if (small_sequence) 753 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); 754 else 755 UASM_i_ADDU(p, pte, pte, tmp); 756 757 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ 758 } 759 760 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, 761 struct uasm_label **l, 762 unsigned int pte, 763 unsigned int ptr, 764 unsigned int flush) 765 { 766 #ifdef CONFIG_SMP 767 UASM_i_SC(p, pte, 0, ptr); 768 uasm_il_beqz(p, r, pte, label_tlb_huge_update); 769 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ 770 #else 771 UASM_i_SW(p, pte, 0, ptr); 772 #endif 773 if (cpu_has_ftlb && flush) { 774 BUG_ON(!cpu_has_tlbinv); 775 776 UASM_i_MFC0(p, ptr, C0_ENTRYHI); 777 uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); 778 UASM_i_MTC0(p, ptr, C0_ENTRYHI); 779 build_tlb_write_entry(p, l, r, tlb_indexed); 780 781 uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); 782 UASM_i_MTC0(p, ptr, C0_ENTRYHI); 783 build_huge_update_entries(p, pte, ptr); 784 build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0); 785 786 return; 787 } 788 789 build_huge_update_entries(p, pte, ptr); 790 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); 791 } 792 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 793 794 #ifdef CONFIG_64BIT 795 /* 796 * TMP and PTR are scratch. 797 * TMP will be clobbered, PTR will hold the pmd entry. 798 */ 799 void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 800 unsigned int tmp, unsigned int ptr) 801 { 802 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 803 long pgdc = (long)pgd_current; 804 #endif 805 /* 806 * The vmalloc handling is not in the hotpath. 807 */ 808 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 809 810 if (check_for_high_segbits) { 811 /* 812 * The kernel currently implicitely assumes that the 813 * MIPS SEGBITS parameter for the processor is 814 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never 815 * allocate virtual addresses outside the maximum 816 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But 817 * that doesn't prevent user code from accessing the 818 * higher xuseg addresses. Here, we make sure that 819 * everything but the lower xuseg addresses goes down 820 * the module_alloc/vmalloc path. 821 */ 822 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 823 uasm_il_bnez(p, r, ptr, label_vmalloc); 824 } else { 825 uasm_il_bltz(p, r, tmp, label_vmalloc); 826 } 827 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 828 829 if (pgd_reg != -1) { 830 /* pgd is in pgd_reg */ 831 if (cpu_has_ldpte) 832 UASM_i_MFC0(p, ptr, C0_PWBASE); 833 else 834 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 835 } else { 836 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT) 837 /* 838 * &pgd << 11 stored in CONTEXT [23..63]. 839 */ 840 UASM_i_MFC0(p, ptr, C0_CONTEXT); 841 842 /* Clear lower 23 bits of context. */ 843 uasm_i_dins(p, ptr, 0, 0, 23); 844 845 /* 1 0 1 0 1 << 6 xkphys cached */ 846 uasm_i_ori(p, ptr, ptr, 0x540); 847 uasm_i_drotr(p, ptr, ptr, 11); 848 #elif defined(CONFIG_SMP) 849 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); 850 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 851 UASM_i_LA_mostly(p, tmp, pgdc); 852 uasm_i_daddu(p, ptr, ptr, tmp); 853 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 854 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 855 #else 856 UASM_i_LA_mostly(p, ptr, pgdc); 857 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 858 #endif 859 } 860 861 uasm_l_vmalloc_done(l, *p); 862 863 /* get pgd offset in bytes */ 864 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); 865 866 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 867 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 868 #ifndef __PAGETABLE_PUD_FOLDED 869 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 870 uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */ 871 uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */ 872 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3); 873 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */ 874 #endif 875 #ifndef __PAGETABLE_PMD_FOLDED 876 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 877 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 878 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 879 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 880 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 881 #endif 882 } 883 EXPORT_SYMBOL_GPL(build_get_pmde64); 884 885 /* 886 * BVADDR is the faulting address, PTR is scratch. 887 * PTR will hold the pgd for vmalloc. 888 */ 889 static void 890 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 891 unsigned int bvaddr, unsigned int ptr, 892 enum vmalloc64_mode mode) 893 { 894 long swpd = (long)swapper_pg_dir; 895 int single_insn_swpd; 896 int did_vmalloc_branch = 0; 897 898 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); 899 900 uasm_l_vmalloc(l, *p); 901 902 if (mode != not_refill && check_for_high_segbits) { 903 if (single_insn_swpd) { 904 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); 905 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 906 did_vmalloc_branch = 1; 907 /* fall through */ 908 } else { 909 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); 910 } 911 } 912 if (!did_vmalloc_branch) { 913 if (single_insn_swpd) { 914 uasm_il_b(p, r, label_vmalloc_done); 915 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 916 } else { 917 UASM_i_LA_mostly(p, ptr, swpd); 918 uasm_il_b(p, r, label_vmalloc_done); 919 if (uasm_in_compat_space_p(swpd)) 920 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); 921 else 922 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); 923 } 924 } 925 if (mode != not_refill && check_for_high_segbits) { 926 uasm_l_large_segbits_fault(l, *p); 927 /* 928 * We get here if we are an xsseg address, or if we are 929 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. 930 * 931 * Ignoring xsseg (assume disabled so would generate 932 * (address errors?), the only remaining possibility 933 * is the upper xuseg addresses. On processors with 934 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these 935 * addresses would have taken an address error. We try 936 * to mimic that here by taking a load/istream page 937 * fault. 938 */ 939 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); 940 uasm_i_jr(p, ptr); 941 942 if (mode == refill_scratch) { 943 if (scratch_reg >= 0) 944 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 945 else 946 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 947 } else { 948 uasm_i_nop(p); 949 } 950 } 951 } 952 953 #else /* !CONFIG_64BIT */ 954 955 /* 956 * TMP and PTR are scratch. 957 * TMP will be clobbered, PTR will hold the pgd entry. 958 */ 959 void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 960 { 961 if (pgd_reg != -1) { 962 /* pgd is in pgd_reg */ 963 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); 964 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 965 } else { 966 long pgdc = (long)pgd_current; 967 968 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 969 #ifdef CONFIG_SMP 970 uasm_i_mfc0(p, ptr, SMP_CPUID_REG); 971 UASM_i_LA_mostly(p, tmp, pgdc); 972 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 973 uasm_i_addu(p, ptr, tmp, ptr); 974 #else 975 UASM_i_LA_mostly(p, ptr, pgdc); 976 #endif 977 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 978 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 979 } 980 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 981 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); 982 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 983 } 984 EXPORT_SYMBOL_GPL(build_get_pgde32); 985 986 #endif /* !CONFIG_64BIT */ 987 988 static void build_adjust_context(u32 **p, unsigned int ctx) 989 { 990 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 991 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 992 993 switch (current_cpu_type()) { 994 case CPU_VR41XX: 995 case CPU_VR4111: 996 case CPU_VR4121: 997 case CPU_VR4122: 998 case CPU_VR4131: 999 case CPU_VR4181: 1000 case CPU_VR4181A: 1001 case CPU_VR4133: 1002 shift += 2; 1003 break; 1004 1005 default: 1006 break; 1007 } 1008 1009 if (shift) 1010 UASM_i_SRL(p, ctx, ctx, shift); 1011 uasm_i_andi(p, ctx, ctx, mask); 1012 } 1013 1014 void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1015 { 1016 /* 1017 * Bug workaround for the Nevada. It seems as if under certain 1018 * circumstances the move from cp0_context might produce a 1019 * bogus result when the mfc0 instruction and its consumer are 1020 * in a different cacheline or a load instruction, probably any 1021 * memory reference, is between them. 1022 */ 1023 switch (current_cpu_type()) { 1024 case CPU_NEVADA: 1025 UASM_i_LW(p, ptr, 0, ptr); 1026 GET_CONTEXT(p, tmp); /* get context reg */ 1027 break; 1028 1029 default: 1030 GET_CONTEXT(p, tmp); /* get context reg */ 1031 UASM_i_LW(p, ptr, 0, ptr); 1032 break; 1033 } 1034 1035 build_adjust_context(p, tmp); 1036 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1037 } 1038 EXPORT_SYMBOL_GPL(build_get_ptep); 1039 1040 void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) 1041 { 1042 int pte_off_even = 0; 1043 int pte_off_odd = sizeof(pte_t); 1044 1045 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT) 1046 /* The low 32 bits of EntryLo is stored in pte_high */ 1047 pte_off_even += offsetof(pte_t, pte_high); 1048 pte_off_odd += offsetof(pte_t, pte_high); 1049 #endif 1050 1051 if (IS_ENABLED(CONFIG_XPA)) { 1052 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */ 1053 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1054 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); 1055 1056 if (cpu_has_xpa && !mips_xpa_disabled) { 1057 uasm_i_lw(p, tmp, 0, ptep); 1058 uasm_i_ext(p, tmp, tmp, 0, 24); 1059 uasm_i_mthc0(p, tmp, C0_ENTRYLO0); 1060 } 1061 1062 uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */ 1063 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1064 UASM_i_MTC0(p, tmp, C0_ENTRYLO1); 1065 1066 if (cpu_has_xpa && !mips_xpa_disabled) { 1067 uasm_i_lw(p, tmp, sizeof(pte_t), ptep); 1068 uasm_i_ext(p, tmp, tmp, 0, 24); 1069 uasm_i_mthc0(p, tmp, C0_ENTRYLO1); 1070 } 1071 return; 1072 } 1073 1074 UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */ 1075 UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */ 1076 if (r45k_bvahwbug()) 1077 build_tlb_probe_entry(p); 1078 build_convert_pte_to_entrylo(p, tmp); 1079 if (r4k_250MHZhwbug()) 1080 UASM_i_MTC0(p, 0, C0_ENTRYLO0); 1081 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ 1082 build_convert_pte_to_entrylo(p, ptep); 1083 if (r45k_bvahwbug()) 1084 uasm_i_mfc0(p, tmp, C0_INDEX); 1085 if (r4k_250MHZhwbug()) 1086 UASM_i_MTC0(p, 0, C0_ENTRYLO1); 1087 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ 1088 } 1089 EXPORT_SYMBOL_GPL(build_update_entries); 1090 1091 struct mips_huge_tlb_info { 1092 int huge_pte; 1093 int restore_scratch; 1094 bool need_reload_pte; 1095 }; 1096 1097 static struct mips_huge_tlb_info 1098 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, 1099 struct uasm_reloc **r, unsigned int tmp, 1100 unsigned int ptr, int c0_scratch_reg) 1101 { 1102 struct mips_huge_tlb_info rv; 1103 unsigned int even, odd; 1104 int vmalloc_branch_delay_filled = 0; 1105 const int scratch = 1; /* Our extra working register */ 1106 1107 rv.huge_pte = scratch; 1108 rv.restore_scratch = 0; 1109 rv.need_reload_pte = false; 1110 1111 if (check_for_high_segbits) { 1112 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1113 1114 if (pgd_reg != -1) 1115 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1116 else 1117 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1118 1119 if (c0_scratch_reg >= 0) 1120 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1121 else 1122 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1123 1124 uasm_i_dsrl_safe(p, scratch, tmp, 1125 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1126 uasm_il_bnez(p, r, scratch, label_vmalloc); 1127 1128 if (pgd_reg == -1) { 1129 vmalloc_branch_delay_filled = 1; 1130 /* Clear lower 23 bits of context. */ 1131 uasm_i_dins(p, ptr, 0, 0, 23); 1132 } 1133 } else { 1134 if (pgd_reg != -1) 1135 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1136 else 1137 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1138 1139 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1140 1141 if (c0_scratch_reg >= 0) 1142 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1143 else 1144 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1145 1146 if (pgd_reg == -1) 1147 /* Clear lower 23 bits of context. */ 1148 uasm_i_dins(p, ptr, 0, 0, 23); 1149 1150 uasm_il_bltz(p, r, tmp, label_vmalloc); 1151 } 1152 1153 if (pgd_reg == -1) { 1154 vmalloc_branch_delay_filled = 1; 1155 /* 1 0 1 0 1 << 6 xkphys cached */ 1156 uasm_i_ori(p, ptr, ptr, 0x540); 1157 uasm_i_drotr(p, ptr, ptr, 11); 1158 } 1159 1160 #ifdef __PAGETABLE_PMD_FOLDED 1161 #define LOC_PTEP scratch 1162 #else 1163 #define LOC_PTEP ptr 1164 #endif 1165 1166 if (!vmalloc_branch_delay_filled) 1167 /* get pgd offset in bytes */ 1168 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1169 1170 uasm_l_vmalloc_done(l, *p); 1171 1172 /* 1173 * tmp ptr 1174 * fall-through case = badvaddr *pgd_current 1175 * vmalloc case = badvaddr swapper_pg_dir 1176 */ 1177 1178 if (vmalloc_branch_delay_filled) 1179 /* get pgd offset in bytes */ 1180 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1181 1182 #ifdef __PAGETABLE_PMD_FOLDED 1183 GET_CONTEXT(p, tmp); /* get context reg */ 1184 #endif 1185 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); 1186 1187 if (use_lwx_insns()) { 1188 UASM_i_LWX(p, LOC_PTEP, scratch, ptr); 1189 } else { 1190 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ 1191 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ 1192 } 1193 1194 #ifndef __PAGETABLE_PUD_FOLDED 1195 /* get pud offset in bytes */ 1196 uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3); 1197 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3); 1198 1199 if (use_lwx_insns()) { 1200 UASM_i_LWX(p, ptr, scratch, ptr); 1201 } else { 1202 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1203 UASM_i_LW(p, ptr, 0, ptr); 1204 } 1205 /* ptr contains a pointer to PMD entry */ 1206 /* tmp contains the address */ 1207 #endif 1208 1209 #ifndef __PAGETABLE_PMD_FOLDED 1210 /* get pmd offset in bytes */ 1211 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); 1212 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); 1213 GET_CONTEXT(p, tmp); /* get context reg */ 1214 1215 if (use_lwx_insns()) { 1216 UASM_i_LWX(p, scratch, scratch, ptr); 1217 } else { 1218 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1219 UASM_i_LW(p, scratch, 0, ptr); 1220 } 1221 #endif 1222 /* Adjust the context during the load latency. */ 1223 build_adjust_context(p, tmp); 1224 1225 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1226 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); 1227 /* 1228 * The in the LWX case we don't want to do the load in the 1229 * delay slot. It cannot issue in the same cycle and may be 1230 * speculative and unneeded. 1231 */ 1232 if (use_lwx_insns()) 1233 uasm_i_nop(p); 1234 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 1235 1236 1237 /* build_update_entries */ 1238 if (use_lwx_insns()) { 1239 even = ptr; 1240 odd = tmp; 1241 UASM_i_LWX(p, even, scratch, tmp); 1242 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); 1243 UASM_i_LWX(p, odd, scratch, tmp); 1244 } else { 1245 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ 1246 even = tmp; 1247 odd = ptr; 1248 UASM_i_LW(p, even, 0, ptr); /* get even pte */ 1249 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ 1250 } 1251 if (cpu_has_rixi) { 1252 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); 1253 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1254 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1255 } else { 1256 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); 1257 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1258 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1259 } 1260 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ 1261 1262 if (c0_scratch_reg >= 0) { 1263 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1264 build_tlb_write_entry(p, l, r, tlb_random); 1265 uasm_l_leave(l, *p); 1266 rv.restore_scratch = 1; 1267 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { 1268 build_tlb_write_entry(p, l, r, tlb_random); 1269 uasm_l_leave(l, *p); 1270 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1271 } else { 1272 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1273 build_tlb_write_entry(p, l, r, tlb_random); 1274 uasm_l_leave(l, *p); 1275 rv.restore_scratch = 1; 1276 } 1277 1278 uasm_i_eret(p); /* return from trap */ 1279 1280 return rv; 1281 } 1282 1283 /* 1284 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception 1285 * because EXL == 0. If we wrap, we can also use the 32 instruction 1286 * slots before the XTLB refill exception handler which belong to the 1287 * unused TLB refill exception. 1288 */ 1289 #define MIPS64_REFILL_INSNS 32 1290 1291 static void build_r4000_tlb_refill_handler(void) 1292 { 1293 u32 *p = tlb_handler; 1294 struct uasm_label *l = labels; 1295 struct uasm_reloc *r = relocs; 1296 u32 *f; 1297 unsigned int final_len; 1298 struct mips_huge_tlb_info htlb_info __maybe_unused; 1299 enum vmalloc64_mode vmalloc_mode __maybe_unused; 1300 1301 memset(tlb_handler, 0, sizeof(tlb_handler)); 1302 memset(labels, 0, sizeof(labels)); 1303 memset(relocs, 0, sizeof(relocs)); 1304 memset(final_handler, 0, sizeof(final_handler)); 1305 1306 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { 1307 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, 1308 scratch_reg); 1309 vmalloc_mode = refill_scratch; 1310 } else { 1311 htlb_info.huge_pte = K0; 1312 htlb_info.restore_scratch = 0; 1313 htlb_info.need_reload_pte = true; 1314 vmalloc_mode = refill_noscratch; 1315 /* 1316 * create the plain linear handler 1317 */ 1318 if (bcm1250_m3_war()) { 1319 unsigned int segbits = 44; 1320 1321 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1322 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 1323 uasm_i_xor(&p, K0, K0, K1); 1324 uasm_i_dsrl_safe(&p, K1, K0, 62); 1325 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 1326 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 1327 uasm_i_or(&p, K0, K0, K1); 1328 uasm_il_bnez(&p, &r, K0, label_leave); 1329 /* No need for uasm_i_nop */ 1330 } 1331 1332 #ifdef CONFIG_64BIT 1333 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1334 #else 1335 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1336 #endif 1337 1338 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1339 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); 1340 #endif 1341 1342 build_get_ptep(&p, K0, K1); 1343 build_update_entries(&p, K0, K1); 1344 build_tlb_write_entry(&p, &l, &r, tlb_random); 1345 uasm_l_leave(&l, p); 1346 uasm_i_eret(&p); /* return from trap */ 1347 } 1348 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1349 uasm_l_tlb_huge_update(&l, p); 1350 if (htlb_info.need_reload_pte) 1351 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1); 1352 build_huge_update_entries(&p, htlb_info.huge_pte, K1); 1353 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, 1354 htlb_info.restore_scratch); 1355 #endif 1356 1357 #ifdef CONFIG_64BIT 1358 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); 1359 #endif 1360 1361 /* 1362 * Overflow check: For the 64bit handler, we need at least one 1363 * free instruction slot for the wrap-around branch. In worst 1364 * case, if the intended insertion point is a delay slot, we 1365 * need three, with the second nop'ed and the third being 1366 * unused. 1367 */ 1368 switch (boot_cpu_type()) { 1369 default: 1370 if (sizeof(long) == 4) { 1371 case CPU_LOONGSON2: 1372 /* Loongson2 ebase is different than r4k, we have more space */ 1373 if ((p - tlb_handler) > 64) 1374 panic("TLB refill handler space exceeded"); 1375 /* 1376 * Now fold the handler in the TLB refill handler space. 1377 */ 1378 f = final_handler; 1379 /* Simplest case, just copy the handler. */ 1380 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1381 final_len = p - tlb_handler; 1382 break; 1383 } else { 1384 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) 1385 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) 1386 && uasm_insn_has_bdelay(relocs, 1387 tlb_handler + MIPS64_REFILL_INSNS - 3))) 1388 panic("TLB refill handler space exceeded"); 1389 /* 1390 * Now fold the handler in the TLB refill handler space. 1391 */ 1392 f = final_handler + MIPS64_REFILL_INSNS; 1393 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { 1394 /* Just copy the handler. */ 1395 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1396 final_len = p - tlb_handler; 1397 } else { 1398 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1399 const enum label_id ls = label_tlb_huge_update; 1400 #else 1401 const enum label_id ls = label_vmalloc; 1402 #endif 1403 u32 *split; 1404 int ov = 0; 1405 int i; 1406 1407 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) 1408 ; 1409 BUG_ON(i == ARRAY_SIZE(labels)); 1410 split = labels[i].addr; 1411 1412 /* 1413 * See if we have overflown one way or the other. 1414 */ 1415 if (split > tlb_handler + MIPS64_REFILL_INSNS || 1416 split < p - MIPS64_REFILL_INSNS) 1417 ov = 1; 1418 1419 if (ov) { 1420 /* 1421 * Split two instructions before the end. One 1422 * for the branch and one for the instruction 1423 * in the delay slot. 1424 */ 1425 split = tlb_handler + MIPS64_REFILL_INSNS - 2; 1426 1427 /* 1428 * If the branch would fall in a delay slot, 1429 * we must back up an additional instruction 1430 * so that it is no longer in a delay slot. 1431 */ 1432 if (uasm_insn_has_bdelay(relocs, split - 1)) 1433 split--; 1434 } 1435 /* Copy first part of the handler. */ 1436 uasm_copy_handler(relocs, labels, tlb_handler, split, f); 1437 f += split - tlb_handler; 1438 1439 if (ov) { 1440 /* Insert branch. */ 1441 uasm_l_split(&l, final_handler); 1442 uasm_il_b(&f, &r, label_split); 1443 if (uasm_insn_has_bdelay(relocs, split)) 1444 uasm_i_nop(&f); 1445 else { 1446 uasm_copy_handler(relocs, labels, 1447 split, split + 1, f); 1448 uasm_move_labels(labels, f, f + 1, -1); 1449 f++; 1450 split++; 1451 } 1452 } 1453 1454 /* Copy the rest of the handler. */ 1455 uasm_copy_handler(relocs, labels, split, p, final_handler); 1456 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + 1457 (p - split); 1458 } 1459 } 1460 break; 1461 } 1462 1463 uasm_resolve_relocs(relocs, labels); 1464 pr_debug("Wrote TLB refill handler (%u instructions).\n", 1465 final_len); 1466 1467 memcpy((void *)ebase, final_handler, 0x100); 1468 local_flush_icache_range(ebase, ebase + 0x100); 1469 1470 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); 1471 } 1472 1473 static void setup_pw(void) 1474 { 1475 unsigned long pgd_i, pgd_w; 1476 #ifndef __PAGETABLE_PMD_FOLDED 1477 unsigned long pmd_i, pmd_w; 1478 #endif 1479 unsigned long pt_i, pt_w; 1480 unsigned long pte_i, pte_w; 1481 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1482 unsigned long psn; 1483 1484 psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */ 1485 #endif 1486 pgd_i = PGDIR_SHIFT; /* 1st level PGD */ 1487 #ifndef __PAGETABLE_PMD_FOLDED 1488 pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER; 1489 1490 pmd_i = PMD_SHIFT; /* 2nd level PMD */ 1491 pmd_w = PMD_SHIFT - PAGE_SHIFT; 1492 #else 1493 pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER; 1494 #endif 1495 1496 pt_i = PAGE_SHIFT; /* 3rd level PTE */ 1497 pt_w = PAGE_SHIFT - 3; 1498 1499 pte_i = ilog2(_PAGE_GLOBAL); 1500 pte_w = 0; 1501 1502 #ifndef __PAGETABLE_PMD_FOLDED 1503 write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i); 1504 write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w); 1505 #else 1506 write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i); 1507 write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w); 1508 #endif 1509 1510 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1511 write_c0_pwctl(1 << 6 | psn); 1512 #endif 1513 write_c0_kpgd(swapper_pg_dir); 1514 kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */ 1515 } 1516 1517 static void build_loongson3_tlb_refill_handler(void) 1518 { 1519 u32 *p = tlb_handler; 1520 struct uasm_label *l = labels; 1521 struct uasm_reloc *r = relocs; 1522 1523 memset(labels, 0, sizeof(labels)); 1524 memset(relocs, 0, sizeof(relocs)); 1525 memset(tlb_handler, 0, sizeof(tlb_handler)); 1526 1527 if (check_for_high_segbits) { 1528 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1529 uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1530 uasm_il_beqz(&p, &r, K1, label_vmalloc); 1531 uasm_i_nop(&p); 1532 1533 uasm_il_bgez(&p, &r, K0, label_large_segbits_fault); 1534 uasm_i_nop(&p); 1535 uasm_l_vmalloc(&l, p); 1536 } 1537 1538 uasm_i_dmfc0(&p, K1, C0_PGD); 1539 1540 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */ 1541 #ifndef __PAGETABLE_PMD_FOLDED 1542 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */ 1543 #endif 1544 uasm_i_ldpte(&p, K1, 0); /* even */ 1545 uasm_i_ldpte(&p, K1, 1); /* odd */ 1546 uasm_i_tlbwr(&p); 1547 1548 /* restore page mask */ 1549 if (PM_DEFAULT_MASK >> 16) { 1550 uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16); 1551 uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff); 1552 uasm_i_mtc0(&p, K0, C0_PAGEMASK); 1553 } else if (PM_DEFAULT_MASK) { 1554 uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK); 1555 uasm_i_mtc0(&p, K0, C0_PAGEMASK); 1556 } else { 1557 uasm_i_mtc0(&p, 0, C0_PAGEMASK); 1558 } 1559 1560 uasm_i_eret(&p); 1561 1562 if (check_for_high_segbits) { 1563 uasm_l_large_segbits_fault(&l, p); 1564 UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0); 1565 uasm_i_jr(&p, K1); 1566 uasm_i_nop(&p); 1567 } 1568 1569 uasm_resolve_relocs(relocs, labels); 1570 memcpy((void *)(ebase + 0x80), tlb_handler, 0x80); 1571 local_flush_icache_range(ebase + 0x80, ebase + 0x100); 1572 dump_handler("loongson3_tlb_refill", (u32 *)(ebase + 0x80), 32); 1573 } 1574 1575 extern u32 handle_tlbl[], handle_tlbl_end[]; 1576 extern u32 handle_tlbs[], handle_tlbs_end[]; 1577 extern u32 handle_tlbm[], handle_tlbm_end[]; 1578 extern u32 tlbmiss_handler_setup_pgd_start[]; 1579 extern u32 tlbmiss_handler_setup_pgd[]; 1580 EXPORT_SYMBOL_GPL(tlbmiss_handler_setup_pgd); 1581 extern u32 tlbmiss_handler_setup_pgd_end[]; 1582 1583 static void build_setup_pgd(void) 1584 { 1585 const int a0 = 4; 1586 const int __maybe_unused a1 = 5; 1587 const int __maybe_unused a2 = 6; 1588 u32 *p = tlbmiss_handler_setup_pgd_start; 1589 const int tlbmiss_handler_setup_pgd_size = 1590 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start; 1591 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1592 long pgdc = (long)pgd_current; 1593 #endif 1594 1595 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * 1596 sizeof(tlbmiss_handler_setup_pgd[0])); 1597 memset(labels, 0, sizeof(labels)); 1598 memset(relocs, 0, sizeof(relocs)); 1599 pgd_reg = allocate_kscratch(); 1600 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 1601 if (pgd_reg == -1) { 1602 struct uasm_label *l = labels; 1603 struct uasm_reloc *r = relocs; 1604 1605 /* PGD << 11 in c0_Context */ 1606 /* 1607 * If it is a ckseg0 address, convert to a physical 1608 * address. Shifting right by 29 and adding 4 will 1609 * result in zero for these addresses. 1610 * 1611 */ 1612 UASM_i_SRA(&p, a1, a0, 29); 1613 UASM_i_ADDIU(&p, a1, a1, 4); 1614 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); 1615 uasm_i_nop(&p); 1616 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); 1617 uasm_l_tlbl_goaround1(&l, p); 1618 UASM_i_SLL(&p, a0, a0, 11); 1619 uasm_i_jr(&p, 31); 1620 UASM_i_MTC0(&p, a0, C0_CONTEXT); 1621 } else { 1622 /* PGD in c0_KScratch */ 1623 uasm_i_jr(&p, 31); 1624 if (cpu_has_ldpte) 1625 UASM_i_MTC0(&p, a0, C0_PWBASE); 1626 else 1627 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1628 } 1629 #else 1630 #ifdef CONFIG_SMP 1631 /* Save PGD to pgd_current[smp_processor_id()] */ 1632 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); 1633 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); 1634 UASM_i_LA_mostly(&p, a2, pgdc); 1635 UASM_i_ADDU(&p, a2, a2, a1); 1636 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1637 #else 1638 UASM_i_LA_mostly(&p, a2, pgdc); 1639 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1640 #endif /* SMP */ 1641 uasm_i_jr(&p, 31); 1642 1643 /* if pgd_reg is allocated, save PGD also to scratch register */ 1644 if (pgd_reg != -1) 1645 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1646 else 1647 uasm_i_nop(&p); 1648 #endif 1649 if (p >= tlbmiss_handler_setup_pgd_end) 1650 panic("tlbmiss_handler_setup_pgd space exceeded"); 1651 1652 uasm_resolve_relocs(relocs, labels); 1653 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", 1654 (unsigned int)(p - tlbmiss_handler_setup_pgd)); 1655 1656 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, 1657 tlbmiss_handler_setup_pgd_size); 1658 } 1659 1660 static void 1661 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) 1662 { 1663 #ifdef CONFIG_SMP 1664 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1665 if (cpu_has_64bits) 1666 uasm_i_lld(p, pte, 0, ptr); 1667 else 1668 # endif 1669 UASM_i_LL(p, pte, 0, ptr); 1670 #else 1671 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1672 if (cpu_has_64bits) 1673 uasm_i_ld(p, pte, 0, ptr); 1674 else 1675 # endif 1676 UASM_i_LW(p, pte, 0, ptr); 1677 #endif 1678 } 1679 1680 static void 1681 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, 1682 unsigned int mode, unsigned int scratch) 1683 { 1684 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1685 unsigned int swmode = mode & ~hwmode; 1686 1687 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) { 1688 uasm_i_lui(p, scratch, swmode >> 16); 1689 uasm_i_or(p, pte, pte, scratch); 1690 BUG_ON(swmode & 0xffff); 1691 } else { 1692 uasm_i_ori(p, pte, pte, mode); 1693 } 1694 1695 #ifdef CONFIG_SMP 1696 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1697 if (cpu_has_64bits) 1698 uasm_i_scd(p, pte, 0, ptr); 1699 else 1700 # endif 1701 UASM_i_SC(p, pte, 0, ptr); 1702 1703 if (r10000_llsc_war()) 1704 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); 1705 else 1706 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1707 1708 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1709 if (!cpu_has_64bits) { 1710 /* no uasm_i_nop needed */ 1711 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1712 uasm_i_ori(p, pte, pte, hwmode); 1713 BUG_ON(hwmode & ~0xffff); 1714 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1715 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1716 /* no uasm_i_nop needed */ 1717 uasm_i_lw(p, pte, 0, ptr); 1718 } else 1719 uasm_i_nop(p); 1720 # else 1721 uasm_i_nop(p); 1722 # endif 1723 #else 1724 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1725 if (cpu_has_64bits) 1726 uasm_i_sd(p, pte, 0, ptr); 1727 else 1728 # endif 1729 UASM_i_SW(p, pte, 0, ptr); 1730 1731 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1732 if (!cpu_has_64bits) { 1733 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1734 uasm_i_ori(p, pte, pte, hwmode); 1735 BUG_ON(hwmode & ~0xffff); 1736 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1737 uasm_i_lw(p, pte, 0, ptr); 1738 } 1739 # endif 1740 #endif 1741 } 1742 1743 /* 1744 * Check if PTE is present, if not then jump to LABEL. PTR points to 1745 * the page table where this PTE is located, PTE will be re-loaded 1746 * with it's original value. 1747 */ 1748 static void 1749 build_pte_present(u32 **p, struct uasm_reloc **r, 1750 int pte, int ptr, int scratch, enum label_id lid) 1751 { 1752 int t = scratch >= 0 ? scratch : pte; 1753 int cur = pte; 1754 1755 if (cpu_has_rixi) { 1756 if (use_bbit_insns()) { 1757 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); 1758 uasm_i_nop(p); 1759 } else { 1760 if (_PAGE_PRESENT_SHIFT) { 1761 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1762 cur = t; 1763 } 1764 uasm_i_andi(p, t, cur, 1); 1765 uasm_il_beqz(p, r, t, lid); 1766 if (pte == t) 1767 /* You lose the SMP race :-(*/ 1768 iPTE_LW(p, pte, ptr); 1769 } 1770 } else { 1771 if (_PAGE_PRESENT_SHIFT) { 1772 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1773 cur = t; 1774 } 1775 uasm_i_andi(p, t, cur, 1776 (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT); 1777 uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT); 1778 uasm_il_bnez(p, r, t, lid); 1779 if (pte == t) 1780 /* You lose the SMP race :-(*/ 1781 iPTE_LW(p, pte, ptr); 1782 } 1783 } 1784 1785 /* Make PTE valid, store result in PTR. */ 1786 static void 1787 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, 1788 unsigned int ptr, unsigned int scratch) 1789 { 1790 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 1791 1792 iPTE_SW(p, r, pte, ptr, mode, scratch); 1793 } 1794 1795 /* 1796 * Check if PTE can be written to, if not branch to LABEL. Regardless 1797 * restore PTE with value from PTR when done. 1798 */ 1799 static void 1800 build_pte_writable(u32 **p, struct uasm_reloc **r, 1801 unsigned int pte, unsigned int ptr, int scratch, 1802 enum label_id lid) 1803 { 1804 int t = scratch >= 0 ? scratch : pte; 1805 int cur = pte; 1806 1807 if (_PAGE_PRESENT_SHIFT) { 1808 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1809 cur = t; 1810 } 1811 uasm_i_andi(p, t, cur, 1812 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1813 uasm_i_xori(p, t, t, 1814 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1815 uasm_il_bnez(p, r, t, lid); 1816 if (pte == t) 1817 /* You lose the SMP race :-(*/ 1818 iPTE_LW(p, pte, ptr); 1819 else 1820 uasm_i_nop(p); 1821 } 1822 1823 /* Make PTE writable, update software status bits as well, then store 1824 * at PTR. 1825 */ 1826 static void 1827 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, 1828 unsigned int ptr, unsigned int scratch) 1829 { 1830 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 1831 | _PAGE_DIRTY); 1832 1833 iPTE_SW(p, r, pte, ptr, mode, scratch); 1834 } 1835 1836 /* 1837 * Check if PTE can be modified, if not branch to LABEL. Regardless 1838 * restore PTE with value from PTR when done. 1839 */ 1840 static void 1841 build_pte_modifiable(u32 **p, struct uasm_reloc **r, 1842 unsigned int pte, unsigned int ptr, int scratch, 1843 enum label_id lid) 1844 { 1845 if (use_bbit_insns()) { 1846 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); 1847 uasm_i_nop(p); 1848 } else { 1849 int t = scratch >= 0 ? scratch : pte; 1850 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT); 1851 uasm_i_andi(p, t, t, 1); 1852 uasm_il_beqz(p, r, t, lid); 1853 if (pte == t) 1854 /* You lose the SMP race :-(*/ 1855 iPTE_LW(p, pte, ptr); 1856 } 1857 } 1858 1859 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1860 1861 1862 /* 1863 * R3000 style TLB load/store/modify handlers. 1864 */ 1865 1866 /* 1867 * This places the pte into ENTRYLO0 and writes it with tlbwi. 1868 * Then it returns. 1869 */ 1870 static void 1871 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 1872 { 1873 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1874 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 1875 uasm_i_tlbwi(p); 1876 uasm_i_jr(p, tmp); 1877 uasm_i_rfe(p); /* branch delay */ 1878 } 1879 1880 /* 1881 * This places the pte into ENTRYLO0 and writes it with tlbwi 1882 * or tlbwr as appropriate. This is because the index register 1883 * may have the probe fail bit set as a result of a trap on a 1884 * kseg2 access, i.e. without refill. Then it returns. 1885 */ 1886 static void 1887 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, 1888 struct uasm_reloc **r, unsigned int pte, 1889 unsigned int tmp) 1890 { 1891 uasm_i_mfc0(p, tmp, C0_INDEX); 1892 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1893 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 1894 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ 1895 uasm_i_tlbwi(p); /* cp0 delay */ 1896 uasm_i_jr(p, tmp); 1897 uasm_i_rfe(p); /* branch delay */ 1898 uasm_l_r3000_write_probe_fail(l, *p); 1899 uasm_i_tlbwr(p); /* cp0 delay */ 1900 uasm_i_jr(p, tmp); 1901 uasm_i_rfe(p); /* branch delay */ 1902 } 1903 1904 static void 1905 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1906 unsigned int ptr) 1907 { 1908 long pgdc = (long)pgd_current; 1909 1910 uasm_i_mfc0(p, pte, C0_BADVADDR); 1911 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ 1912 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 1913 uasm_i_srl(p, pte, pte, 22); /* load delay */ 1914 uasm_i_sll(p, pte, pte, 2); 1915 uasm_i_addu(p, ptr, ptr, pte); 1916 uasm_i_mfc0(p, pte, C0_CONTEXT); 1917 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ 1918 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ 1919 uasm_i_addu(p, ptr, ptr, pte); 1920 uasm_i_lw(p, pte, 0, ptr); 1921 uasm_i_tlbp(p); /* load delay */ 1922 } 1923 1924 static void build_r3000_tlb_load_handler(void) 1925 { 1926 u32 *p = handle_tlbl; 1927 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; 1928 struct uasm_label *l = labels; 1929 struct uasm_reloc *r = relocs; 1930 1931 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); 1932 memset(labels, 0, sizeof(labels)); 1933 memset(relocs, 0, sizeof(relocs)); 1934 1935 build_r3000_tlbchange_handler_head(&p, K0, K1); 1936 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); 1937 uasm_i_nop(&p); /* load delay */ 1938 build_make_valid(&p, &r, K0, K1, -1); 1939 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1940 1941 uasm_l_nopage_tlbl(&l, p); 1942 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1943 uasm_i_nop(&p); 1944 1945 if (p >= handle_tlbl_end) 1946 panic("TLB load handler fastpath space exceeded"); 1947 1948 uasm_resolve_relocs(relocs, labels); 1949 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1950 (unsigned int)(p - handle_tlbl)); 1951 1952 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size); 1953 } 1954 1955 static void build_r3000_tlb_store_handler(void) 1956 { 1957 u32 *p = handle_tlbs; 1958 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; 1959 struct uasm_label *l = labels; 1960 struct uasm_reloc *r = relocs; 1961 1962 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); 1963 memset(labels, 0, sizeof(labels)); 1964 memset(relocs, 0, sizeof(relocs)); 1965 1966 build_r3000_tlbchange_handler_head(&p, K0, K1); 1967 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); 1968 uasm_i_nop(&p); /* load delay */ 1969 build_make_write(&p, &r, K0, K1, -1); 1970 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1971 1972 uasm_l_nopage_tlbs(&l, p); 1973 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1974 uasm_i_nop(&p); 1975 1976 if (p >= handle_tlbs_end) 1977 panic("TLB store handler fastpath space exceeded"); 1978 1979 uasm_resolve_relocs(relocs, labels); 1980 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1981 (unsigned int)(p - handle_tlbs)); 1982 1983 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size); 1984 } 1985 1986 static void build_r3000_tlb_modify_handler(void) 1987 { 1988 u32 *p = handle_tlbm; 1989 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; 1990 struct uasm_label *l = labels; 1991 struct uasm_reloc *r = relocs; 1992 1993 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); 1994 memset(labels, 0, sizeof(labels)); 1995 memset(relocs, 0, sizeof(relocs)); 1996 1997 build_r3000_tlbchange_handler_head(&p, K0, K1); 1998 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); 1999 uasm_i_nop(&p); /* load delay */ 2000 build_make_write(&p, &r, K0, K1, -1); 2001 build_r3000_pte_reload_tlbwi(&p, K0, K1); 2002 2003 uasm_l_nopage_tlbm(&l, p); 2004 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2005 uasm_i_nop(&p); 2006 2007 if (p >= handle_tlbm_end) 2008 panic("TLB modify handler fastpath space exceeded"); 2009 2010 uasm_resolve_relocs(relocs, labels); 2011 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2012 (unsigned int)(p - handle_tlbm)); 2013 2014 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size); 2015 } 2016 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 2017 2018 /* 2019 * R4000 style TLB load/store/modify handlers. 2020 */ 2021 static struct work_registers 2022 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, 2023 struct uasm_reloc **r) 2024 { 2025 struct work_registers wr = build_get_work_registers(p); 2026 2027 #ifdef CONFIG_64BIT 2028 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ 2029 #else 2030 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ 2031 #endif 2032 2033 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2034 /* 2035 * For huge tlb entries, pmd doesn't contain an address but 2036 * instead contains the tlb pte. Check the PAGE_HUGE bit and 2037 * see if we need to jump to huge tlb processing. 2038 */ 2039 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); 2040 #endif 2041 2042 UASM_i_MFC0(p, wr.r1, C0_BADVADDR); 2043 UASM_i_LW(p, wr.r2, 0, wr.r2); 2044 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 2045 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 2046 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); 2047 2048 #ifdef CONFIG_SMP 2049 uasm_l_smp_pgtable_change(l, *p); 2050 #endif 2051 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ 2052 if (!m4kc_tlbp_war()) { 2053 build_tlb_probe_entry(p); 2054 if (cpu_has_htw) { 2055 /* race condition happens, leaving */ 2056 uasm_i_ehb(p); 2057 uasm_i_mfc0(p, wr.r3, C0_INDEX); 2058 uasm_il_bltz(p, r, wr.r3, label_leave); 2059 uasm_i_nop(p); 2060 } 2061 } 2062 return wr; 2063 } 2064 2065 static void 2066 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, 2067 struct uasm_reloc **r, unsigned int tmp, 2068 unsigned int ptr) 2069 { 2070 uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); 2071 uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); 2072 build_update_entries(p, tmp, ptr); 2073 build_tlb_write_entry(p, l, r, tlb_indexed); 2074 uasm_l_leave(l, *p); 2075 build_restore_work_registers(p); 2076 uasm_i_eret(p); /* return from trap */ 2077 2078 #ifdef CONFIG_64BIT 2079 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); 2080 #endif 2081 } 2082 2083 static void build_r4000_tlb_load_handler(void) 2084 { 2085 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl); 2086 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; 2087 struct uasm_label *l = labels; 2088 struct uasm_reloc *r = relocs; 2089 struct work_registers wr; 2090 2091 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); 2092 memset(labels, 0, sizeof(labels)); 2093 memset(relocs, 0, sizeof(relocs)); 2094 2095 if (bcm1250_m3_war()) { 2096 unsigned int segbits = 44; 2097 2098 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 2099 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 2100 uasm_i_xor(&p, K0, K0, K1); 2101 uasm_i_dsrl_safe(&p, K1, K0, 62); 2102 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 2103 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 2104 uasm_i_or(&p, K0, K0, K1); 2105 uasm_il_bnez(&p, &r, K0, label_leave); 2106 /* No need for uasm_i_nop */ 2107 } 2108 2109 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2110 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2111 if (m4kc_tlbp_war()) 2112 build_tlb_probe_entry(&p); 2113 2114 if (cpu_has_rixi && !cpu_has_rixiex) { 2115 /* 2116 * If the page is not _PAGE_VALID, RI or XI could not 2117 * have triggered it. Skip the expensive test.. 2118 */ 2119 if (use_bbit_insns()) { 2120 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2121 label_tlbl_goaround1); 2122 } else { 2123 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2124 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); 2125 } 2126 uasm_i_nop(&p); 2127 2128 uasm_i_tlbr(&p); 2129 2130 switch (current_cpu_type()) { 2131 default: 2132 if (cpu_has_mips_r2_exec_hazard) { 2133 uasm_i_ehb(&p); 2134 2135 case CPU_CAVIUM_OCTEON: 2136 case CPU_CAVIUM_OCTEON_PLUS: 2137 case CPU_CAVIUM_OCTEON2: 2138 break; 2139 } 2140 } 2141 2142 /* Examine entrylo 0 or 1 based on ptr. */ 2143 if (use_bbit_insns()) { 2144 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2145 } else { 2146 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2147 uasm_i_beqz(&p, wr.r3, 8); 2148 } 2149 /* load it in the delay slot*/ 2150 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2151 /* load it if ptr is odd */ 2152 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2153 /* 2154 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2155 * XI must have triggered it. 2156 */ 2157 if (use_bbit_insns()) { 2158 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); 2159 uasm_i_nop(&p); 2160 uasm_l_tlbl_goaround1(&l, p); 2161 } else { 2162 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2163 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); 2164 uasm_i_nop(&p); 2165 } 2166 uasm_l_tlbl_goaround1(&l, p); 2167 } 2168 build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3); 2169 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2170 2171 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2172 /* 2173 * This is the entry point when build_r4000_tlbchange_handler_head 2174 * spots a huge page. 2175 */ 2176 uasm_l_tlb_huge_update(&l, p); 2177 iPTE_LW(&p, wr.r1, wr.r2); 2178 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2179 build_tlb_probe_entry(&p); 2180 2181 if (cpu_has_rixi && !cpu_has_rixiex) { 2182 /* 2183 * If the page is not _PAGE_VALID, RI or XI could not 2184 * have triggered it. Skip the expensive test.. 2185 */ 2186 if (use_bbit_insns()) { 2187 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2188 label_tlbl_goaround2); 2189 } else { 2190 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2191 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2192 } 2193 uasm_i_nop(&p); 2194 2195 uasm_i_tlbr(&p); 2196 2197 switch (current_cpu_type()) { 2198 default: 2199 if (cpu_has_mips_r2_exec_hazard) { 2200 uasm_i_ehb(&p); 2201 2202 case CPU_CAVIUM_OCTEON: 2203 case CPU_CAVIUM_OCTEON_PLUS: 2204 case CPU_CAVIUM_OCTEON2: 2205 break; 2206 } 2207 } 2208 2209 /* Examine entrylo 0 or 1 based on ptr. */ 2210 if (use_bbit_insns()) { 2211 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2212 } else { 2213 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2214 uasm_i_beqz(&p, wr.r3, 8); 2215 } 2216 /* load it in the delay slot*/ 2217 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2218 /* load it if ptr is odd */ 2219 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2220 /* 2221 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2222 * XI must have triggered it. 2223 */ 2224 if (use_bbit_insns()) { 2225 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); 2226 } else { 2227 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2228 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2229 } 2230 if (PM_DEFAULT_MASK == 0) 2231 uasm_i_nop(&p); 2232 /* 2233 * We clobbered C0_PAGEMASK, restore it. On the other branch 2234 * it is restored in build_huge_tlb_write_entry. 2235 */ 2236 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); 2237 2238 uasm_l_tlbl_goaround2(&l, p); 2239 } 2240 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); 2241 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); 2242 #endif 2243 2244 uasm_l_nopage_tlbl(&l, p); 2245 build_restore_work_registers(&p); 2246 #ifdef CONFIG_CPU_MICROMIPS 2247 if ((unsigned long)tlb_do_page_fault_0 & 1) { 2248 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); 2249 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); 2250 uasm_i_jr(&p, K0); 2251 } else 2252 #endif 2253 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 2254 uasm_i_nop(&p); 2255 2256 if (p >= handle_tlbl_end) 2257 panic("TLB load handler fastpath space exceeded"); 2258 2259 uasm_resolve_relocs(relocs, labels); 2260 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 2261 (unsigned int)(p - handle_tlbl)); 2262 2263 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size); 2264 } 2265 2266 static void build_r4000_tlb_store_handler(void) 2267 { 2268 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs); 2269 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; 2270 struct uasm_label *l = labels; 2271 struct uasm_reloc *r = relocs; 2272 struct work_registers wr; 2273 2274 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); 2275 memset(labels, 0, sizeof(labels)); 2276 memset(relocs, 0, sizeof(relocs)); 2277 2278 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2279 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2280 if (m4kc_tlbp_war()) 2281 build_tlb_probe_entry(&p); 2282 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); 2283 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2284 2285 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2286 /* 2287 * This is the entry point when 2288 * build_r4000_tlbchange_handler_head spots a huge page. 2289 */ 2290 uasm_l_tlb_huge_update(&l, p); 2291 iPTE_LW(&p, wr.r1, wr.r2); 2292 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2293 build_tlb_probe_entry(&p); 2294 uasm_i_ori(&p, wr.r1, wr.r1, 2295 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2296 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); 2297 #endif 2298 2299 uasm_l_nopage_tlbs(&l, p); 2300 build_restore_work_registers(&p); 2301 #ifdef CONFIG_CPU_MICROMIPS 2302 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2303 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2304 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2305 uasm_i_jr(&p, K0); 2306 } else 2307 #endif 2308 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2309 uasm_i_nop(&p); 2310 2311 if (p >= handle_tlbs_end) 2312 panic("TLB store handler fastpath space exceeded"); 2313 2314 uasm_resolve_relocs(relocs, labels); 2315 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 2316 (unsigned int)(p - handle_tlbs)); 2317 2318 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size); 2319 } 2320 2321 static void build_r4000_tlb_modify_handler(void) 2322 { 2323 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm); 2324 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; 2325 struct uasm_label *l = labels; 2326 struct uasm_reloc *r = relocs; 2327 struct work_registers wr; 2328 2329 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); 2330 memset(labels, 0, sizeof(labels)); 2331 memset(relocs, 0, sizeof(relocs)); 2332 2333 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2334 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2335 if (m4kc_tlbp_war()) 2336 build_tlb_probe_entry(&p); 2337 /* Present and writable bits set, set accessed and dirty bits. */ 2338 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); 2339 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2340 2341 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2342 /* 2343 * This is the entry point when 2344 * build_r4000_tlbchange_handler_head spots a huge page. 2345 */ 2346 uasm_l_tlb_huge_update(&l, p); 2347 iPTE_LW(&p, wr.r1, wr.r2); 2348 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2349 build_tlb_probe_entry(&p); 2350 uasm_i_ori(&p, wr.r1, wr.r1, 2351 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2352 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0); 2353 #endif 2354 2355 uasm_l_nopage_tlbm(&l, p); 2356 build_restore_work_registers(&p); 2357 #ifdef CONFIG_CPU_MICROMIPS 2358 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2359 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2360 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2361 uasm_i_jr(&p, K0); 2362 } else 2363 #endif 2364 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2365 uasm_i_nop(&p); 2366 2367 if (p >= handle_tlbm_end) 2368 panic("TLB modify handler fastpath space exceeded"); 2369 2370 uasm_resolve_relocs(relocs, labels); 2371 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2372 (unsigned int)(p - handle_tlbm)); 2373 2374 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size); 2375 } 2376 2377 static void flush_tlb_handlers(void) 2378 { 2379 local_flush_icache_range((unsigned long)handle_tlbl, 2380 (unsigned long)handle_tlbl_end); 2381 local_flush_icache_range((unsigned long)handle_tlbs, 2382 (unsigned long)handle_tlbs_end); 2383 local_flush_icache_range((unsigned long)handle_tlbm, 2384 (unsigned long)handle_tlbm_end); 2385 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, 2386 (unsigned long)tlbmiss_handler_setup_pgd_end); 2387 } 2388 2389 static void print_htw_config(void) 2390 { 2391 unsigned long config; 2392 unsigned int pwctl; 2393 const int field = 2 * sizeof(unsigned long); 2394 2395 config = read_c0_pwfield(); 2396 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n", 2397 field, config, 2398 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT, 2399 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT, 2400 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT, 2401 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT, 2402 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); 2403 2404 config = read_c0_pwsize(); 2405 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", 2406 field, config, 2407 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT, 2408 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, 2409 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, 2410 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, 2411 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT, 2412 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); 2413 2414 pwctl = read_c0_pwctl(); 2415 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", 2416 pwctl, 2417 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, 2418 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT, 2419 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT, 2420 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT, 2421 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, 2422 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, 2423 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); 2424 } 2425 2426 static void config_htw_params(void) 2427 { 2428 unsigned long pwfield, pwsize, ptei; 2429 unsigned int config; 2430 2431 /* 2432 * We are using 2-level page tables, so we only need to 2433 * setup GDW and PTW appropriately. UDW and MDW will remain 0. 2434 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to 2435 * write values less than 0xc in these fields because the entire 2436 * write will be dropped. As a result of which, we must preserve 2437 * the original reset values and overwrite only what we really want. 2438 */ 2439 2440 pwfield = read_c0_pwfield(); 2441 /* re-initialize the GDI field */ 2442 pwfield &= ~MIPS_PWFIELD_GDI_MASK; 2443 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT; 2444 /* re-initialize the PTI field including the even/odd bit */ 2445 pwfield &= ~MIPS_PWFIELD_PTI_MASK; 2446 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT; 2447 if (CONFIG_PGTABLE_LEVELS >= 3) { 2448 pwfield &= ~MIPS_PWFIELD_MDI_MASK; 2449 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT; 2450 } 2451 /* Set the PTEI right shift */ 2452 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT; 2453 pwfield |= ptei; 2454 write_c0_pwfield(pwfield); 2455 /* Check whether the PTEI value is supported */ 2456 back_to_back_c0_hazard(); 2457 pwfield = read_c0_pwfield(); 2458 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT) 2459 != ptei) { 2460 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled", 2461 ptei); 2462 /* 2463 * Drop option to avoid HTW being enabled via another path 2464 * (eg htw_reset()) 2465 */ 2466 current_cpu_data.options &= ~MIPS_CPU_HTW; 2467 return; 2468 } 2469 2470 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; 2471 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; 2472 if (CONFIG_PGTABLE_LEVELS >= 3) 2473 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; 2474 2475 /* Set pointer size to size of directory pointers */ 2476 if (IS_ENABLED(CONFIG_64BIT)) 2477 pwsize |= MIPS_PWSIZE_PS_MASK; 2478 /* PTEs may be multiple pointers long (e.g. with XPA) */ 2479 pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT) 2480 & MIPS_PWSIZE_PTEW_MASK; 2481 2482 write_c0_pwsize(pwsize); 2483 2484 /* Make sure everything is set before we enable the HTW */ 2485 back_to_back_c0_hazard(); 2486 2487 /* 2488 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of 2489 * the pwctl fields. 2490 */ 2491 config = 1 << MIPS_PWCTL_PWEN_SHIFT; 2492 if (IS_ENABLED(CONFIG_64BIT)) 2493 config |= MIPS_PWCTL_XU_MASK; 2494 write_c0_pwctl(config); 2495 pr_info("Hardware Page Table Walker enabled\n"); 2496 2497 print_htw_config(); 2498 } 2499 2500 static void config_xpa_params(void) 2501 { 2502 #ifdef CONFIG_XPA 2503 unsigned int pagegrain; 2504 2505 if (mips_xpa_disabled) { 2506 pr_info("Extended Physical Addressing (XPA) disabled\n"); 2507 return; 2508 } 2509 2510 pagegrain = read_c0_pagegrain(); 2511 write_c0_pagegrain(pagegrain | PG_ELPA); 2512 back_to_back_c0_hazard(); 2513 pagegrain = read_c0_pagegrain(); 2514 2515 if (pagegrain & PG_ELPA) 2516 pr_info("Extended Physical Addressing (XPA) enabled\n"); 2517 else 2518 panic("Extended Physical Addressing (XPA) disabled"); 2519 #endif 2520 } 2521 2522 static void check_pabits(void) 2523 { 2524 unsigned long entry; 2525 unsigned pabits, fillbits; 2526 2527 if (!cpu_has_rixi || !_PAGE_NO_EXEC) { 2528 /* 2529 * We'll only be making use of the fact that we can rotate bits 2530 * into the fill if the CPU supports RIXI, so don't bother 2531 * probing this for CPUs which don't. 2532 */ 2533 return; 2534 } 2535 2536 write_c0_entrylo0(~0ul); 2537 back_to_back_c0_hazard(); 2538 entry = read_c0_entrylo0(); 2539 2540 /* clear all non-PFN bits */ 2541 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1); 2542 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); 2543 2544 /* find a lower bound on PABITS, and upper bound on fill bits */ 2545 pabits = fls_long(entry) + 6; 2546 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0); 2547 2548 /* minus the RI & XI bits */ 2549 fillbits -= min_t(unsigned, fillbits, 2); 2550 2551 if (fillbits >= ilog2(_PAGE_NO_EXEC)) 2552 fill_includes_sw_bits = true; 2553 2554 pr_debug("Entry* registers contain %u fill bits\n", fillbits); 2555 } 2556 2557 void build_tlb_refill_handler(void) 2558 { 2559 /* 2560 * The refill handler is generated per-CPU, multi-node systems 2561 * may have local storage for it. The other handlers are only 2562 * needed once. 2563 */ 2564 static int run_once = 0; 2565 2566 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi) 2567 panic("Kernels supporting XPA currently require CPUs with RIXI"); 2568 2569 output_pgtable_bits_defines(); 2570 check_pabits(); 2571 2572 #ifdef CONFIG_64BIT 2573 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 2574 #endif 2575 2576 switch (current_cpu_type()) { 2577 case CPU_R2000: 2578 case CPU_R3000: 2579 case CPU_R3000A: 2580 case CPU_R3081E: 2581 case CPU_TX3912: 2582 case CPU_TX3922: 2583 case CPU_TX3927: 2584 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 2585 if (cpu_has_local_ebase) 2586 build_r3000_tlb_refill_handler(); 2587 if (!run_once) { 2588 if (!cpu_has_local_ebase) 2589 build_r3000_tlb_refill_handler(); 2590 build_setup_pgd(); 2591 build_r3000_tlb_load_handler(); 2592 build_r3000_tlb_store_handler(); 2593 build_r3000_tlb_modify_handler(); 2594 flush_tlb_handlers(); 2595 run_once++; 2596 } 2597 #else 2598 panic("No R3000 TLB refill handler"); 2599 #endif 2600 break; 2601 2602 case CPU_R6000: 2603 case CPU_R6000A: 2604 panic("No R6000 TLB refill handler yet"); 2605 break; 2606 2607 case CPU_R8000: 2608 panic("No R8000 TLB refill handler yet"); 2609 break; 2610 2611 default: 2612 if (cpu_has_ldpte) 2613 setup_pw(); 2614 2615 if (!run_once) { 2616 scratch_reg = allocate_kscratch(); 2617 build_setup_pgd(); 2618 build_r4000_tlb_load_handler(); 2619 build_r4000_tlb_store_handler(); 2620 build_r4000_tlb_modify_handler(); 2621 if (cpu_has_ldpte) 2622 build_loongson3_tlb_refill_handler(); 2623 else if (!cpu_has_local_ebase) 2624 build_r4000_tlb_refill_handler(); 2625 flush_tlb_handlers(); 2626 run_once++; 2627 } 2628 if (cpu_has_local_ebase) 2629 build_r4000_tlb_refill_handler(); 2630 if (cpu_has_xpa) 2631 config_xpa_params(); 2632 if (cpu_has_htw) 2633 config_htw_params(); 2634 } 2635 } 2636