1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 * Copyright (C) 2008, 2009 Cavium Networks, Inc. 12 * Copyright (C) 2011 MIPS Technologies, Inc. 13 * 14 * ... and the days got worse and worse and now you see 15 * I've gone completely out of my mind. 16 * 17 * They're coming to take me a away haha 18 * they're coming to take me a away hoho hihi haha 19 * to the funny farm where code is beautiful all the time ... 20 * 21 * (Condolences to Napoleon XIV) 22 */ 23 24 #include <linux/bug.h> 25 #include <linux/export.h> 26 #include <linux/kernel.h> 27 #include <linux/types.h> 28 #include <linux/smp.h> 29 #include <linux/string.h> 30 #include <linux/cache.h> 31 32 #include <asm/cacheflush.h> 33 #include <asm/cpu-type.h> 34 #include <asm/mmu_context.h> 35 #include <asm/pgtable.h> 36 #include <asm/war.h> 37 #include <asm/uasm.h> 38 #include <asm/setup.h> 39 #include <asm/tlbex.h> 40 41 static int mips_xpa_disabled; 42 43 static int __init xpa_disable(char *s) 44 { 45 mips_xpa_disabled = 1; 46 47 return 1; 48 } 49 50 __setup("noxpa", xpa_disable); 51 52 /* 53 * TLB load/store/modify handlers. 54 * 55 * Only the fastpath gets synthesized at runtime, the slowpath for 56 * do_page_fault remains normal asm. 57 */ 58 extern void tlb_do_page_fault_0(void); 59 extern void tlb_do_page_fault_1(void); 60 61 struct work_registers { 62 int r1; 63 int r2; 64 int r3; 65 }; 66 67 struct tlb_reg_save { 68 unsigned long a; 69 unsigned long b; 70 } ____cacheline_aligned_in_smp; 71 72 static struct tlb_reg_save handler_reg_save[NR_CPUS]; 73 74 static inline int r45k_bvahwbug(void) 75 { 76 /* XXX: We should probe for the presence of this bug, but we don't. */ 77 return 0; 78 } 79 80 static inline int r4k_250MHZhwbug(void) 81 { 82 /* XXX: We should probe for the presence of this bug, but we don't. */ 83 return 0; 84 } 85 86 static inline int __maybe_unused bcm1250_m3_war(void) 87 { 88 return BCM1250_M3_WAR; 89 } 90 91 static inline int __maybe_unused r10000_llsc_war(void) 92 { 93 return R10000_LLSC_WAR; 94 } 95 96 static int use_bbit_insns(void) 97 { 98 switch (current_cpu_type()) { 99 case CPU_CAVIUM_OCTEON: 100 case CPU_CAVIUM_OCTEON_PLUS: 101 case CPU_CAVIUM_OCTEON2: 102 case CPU_CAVIUM_OCTEON3: 103 return 1; 104 default: 105 return 0; 106 } 107 } 108 109 static int use_lwx_insns(void) 110 { 111 switch (current_cpu_type()) { 112 case CPU_CAVIUM_OCTEON2: 113 case CPU_CAVIUM_OCTEON3: 114 return 1; 115 default: 116 return 0; 117 } 118 } 119 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ 120 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 121 static bool scratchpad_available(void) 122 { 123 return true; 124 } 125 static int scratchpad_offset(int i) 126 { 127 /* 128 * CVMSEG starts at address -32768 and extends for 129 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. 130 */ 131 i += 1; /* Kernel use starts at the top and works down. */ 132 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; 133 } 134 #else 135 static bool scratchpad_available(void) 136 { 137 return false; 138 } 139 static int scratchpad_offset(int i) 140 { 141 BUG(); 142 /* Really unreachable, but evidently some GCC want this. */ 143 return 0; 144 } 145 #endif 146 /* 147 * Found by experiment: At least some revisions of the 4kc throw under 148 * some circumstances a machine check exception, triggered by invalid 149 * values in the index register. Delaying the tlbp instruction until 150 * after the next branch, plus adding an additional nop in front of 151 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows 152 * why; it's not an issue caused by the core RTL. 153 * 154 */ 155 static int m4kc_tlbp_war(void) 156 { 157 return current_cpu_type() == CPU_4KC; 158 } 159 160 /* Handle labels (which must be positive integers). */ 161 enum label_id { 162 label_second_part = 1, 163 label_leave, 164 label_vmalloc, 165 label_vmalloc_done, 166 label_tlbw_hazard_0, 167 label_split = label_tlbw_hazard_0 + 8, 168 label_tlbl_goaround1, 169 label_tlbl_goaround2, 170 label_nopage_tlbl, 171 label_nopage_tlbs, 172 label_nopage_tlbm, 173 label_smp_pgtable_change, 174 label_r3000_write_probe_fail, 175 label_large_segbits_fault, 176 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 177 label_tlb_huge_update, 178 #endif 179 }; 180 181 UASM_L_LA(_second_part) 182 UASM_L_LA(_leave) 183 UASM_L_LA(_vmalloc) 184 UASM_L_LA(_vmalloc_done) 185 /* _tlbw_hazard_x is handled differently. */ 186 UASM_L_LA(_split) 187 UASM_L_LA(_tlbl_goaround1) 188 UASM_L_LA(_tlbl_goaround2) 189 UASM_L_LA(_nopage_tlbl) 190 UASM_L_LA(_nopage_tlbs) 191 UASM_L_LA(_nopage_tlbm) 192 UASM_L_LA(_smp_pgtable_change) 193 UASM_L_LA(_r3000_write_probe_fail) 194 UASM_L_LA(_large_segbits_fault) 195 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 196 UASM_L_LA(_tlb_huge_update) 197 #endif 198 199 static int hazard_instance; 200 201 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) 202 { 203 switch (instance) { 204 case 0 ... 7: 205 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); 206 return; 207 default: 208 BUG(); 209 } 210 } 211 212 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) 213 { 214 switch (instance) { 215 case 0 ... 7: 216 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); 217 break; 218 default: 219 BUG(); 220 } 221 } 222 223 /* 224 * pgtable bits are assigned dynamically depending on processor feature 225 * and statically based on kernel configuration. This spits out the actual 226 * values the kernel is using. Required to make sense from disassembled 227 * TLB exception handlers. 228 */ 229 static void output_pgtable_bits_defines(void) 230 { 231 #define pr_define(fmt, ...) \ 232 pr_debug("#define " fmt, ##__VA_ARGS__) 233 234 pr_debug("#include <asm/asm.h>\n"); 235 pr_debug("#include <asm/regdef.h>\n"); 236 pr_debug("\n"); 237 238 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); 239 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); 240 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); 241 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); 242 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); 243 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 244 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); 245 #endif 246 #ifdef _PAGE_NO_EXEC_SHIFT 247 if (cpu_has_rixi) 248 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); 249 #endif 250 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); 251 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); 252 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); 253 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); 254 pr_debug("\n"); 255 } 256 257 static inline void dump_handler(const char *symbol, const void *start, const void *end) 258 { 259 unsigned int count = (end - start) / sizeof(u32); 260 const u32 *handler = start; 261 int i; 262 263 pr_debug("LEAF(%s)\n", symbol); 264 265 pr_debug("\t.set push\n"); 266 pr_debug("\t.set noreorder\n"); 267 268 for (i = 0; i < count; i++) 269 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); 270 271 pr_debug("\t.set\tpop\n"); 272 273 pr_debug("\tEND(%s)\n", symbol); 274 } 275 276 /* The only general purpose registers allowed in TLB handlers. */ 277 #define K0 26 278 #define K1 27 279 280 /* Some CP0 registers */ 281 #define C0_INDEX 0, 0 282 #define C0_ENTRYLO0 2, 0 283 #define C0_TCBIND 2, 2 284 #define C0_ENTRYLO1 3, 0 285 #define C0_CONTEXT 4, 0 286 #define C0_PAGEMASK 5, 0 287 #define C0_PWBASE 5, 5 288 #define C0_PWFIELD 5, 6 289 #define C0_PWSIZE 5, 7 290 #define C0_PWCTL 6, 6 291 #define C0_BADVADDR 8, 0 292 #define C0_PGD 9, 7 293 #define C0_ENTRYHI 10, 0 294 #define C0_EPC 14, 0 295 #define C0_XCONTEXT 20, 0 296 297 #ifdef CONFIG_64BIT 298 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) 299 #else 300 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) 301 #endif 302 303 /* The worst case length of the handler is around 18 instructions for 304 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 305 * Maximum space available is 32 instructions for R3000 and 64 306 * instructions for R4000. 307 * 308 * We deliberately chose a buffer size of 128, so we won't scribble 309 * over anything important on overflow before we panic. 310 */ 311 static u32 tlb_handler[128]; 312 313 /* simply assume worst case size for labels and relocs */ 314 static struct uasm_label labels[128]; 315 static struct uasm_reloc relocs[128]; 316 317 static int check_for_high_segbits; 318 static bool fill_includes_sw_bits; 319 320 static unsigned int kscratch_used_mask; 321 322 static inline int __maybe_unused c0_kscratch(void) 323 { 324 switch (current_cpu_type()) { 325 case CPU_XLP: 326 case CPU_XLR: 327 return 22; 328 default: 329 return 31; 330 } 331 } 332 333 static int allocate_kscratch(void) 334 { 335 int r; 336 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; 337 338 r = ffs(a); 339 340 if (r == 0) 341 return -1; 342 343 r--; /* make it zero based */ 344 345 kscratch_used_mask |= (1 << r); 346 347 return r; 348 } 349 350 static int scratch_reg; 351 int pgd_reg; 352 EXPORT_SYMBOL_GPL(pgd_reg); 353 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; 354 355 static struct work_registers build_get_work_registers(u32 **p) 356 { 357 struct work_registers r; 358 359 if (scratch_reg >= 0) { 360 /* Save in CPU local C0_KScratch? */ 361 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); 362 r.r1 = K0; 363 r.r2 = K1; 364 r.r3 = 1; 365 return r; 366 } 367 368 if (num_possible_cpus() > 1) { 369 /* Get smp_processor_id */ 370 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); 371 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); 372 373 /* handler_reg_save index in K0 */ 374 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); 375 376 UASM_i_LA(p, K1, (long)&handler_reg_save); 377 UASM_i_ADDU(p, K0, K0, K1); 378 } else { 379 UASM_i_LA(p, K0, (long)&handler_reg_save); 380 } 381 /* K0 now points to save area, save $1 and $2 */ 382 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); 383 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); 384 385 r.r1 = K1; 386 r.r2 = 1; 387 r.r3 = 2; 388 return r; 389 } 390 391 static void build_restore_work_registers(u32 **p) 392 { 393 if (scratch_reg >= 0) { 394 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 395 return; 396 } 397 /* K0 already points to save area, restore $1 and $2 */ 398 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); 399 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); 400 } 401 402 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 403 404 /* 405 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, 406 * we cannot do r3000 under these circumstances. 407 * 408 * The R3000 TLB handler is simple. 409 */ 410 static void build_r3000_tlb_refill_handler(void) 411 { 412 long pgdc = (long)pgd_current; 413 u32 *p; 414 415 memset(tlb_handler, 0, sizeof(tlb_handler)); 416 p = tlb_handler; 417 418 uasm_i_mfc0(&p, K0, C0_BADVADDR); 419 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ 420 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); 421 uasm_i_srl(&p, K0, K0, 22); /* load delay */ 422 uasm_i_sll(&p, K0, K0, 2); 423 uasm_i_addu(&p, K1, K1, K0); 424 uasm_i_mfc0(&p, K0, C0_CONTEXT); 425 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ 426 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ 427 uasm_i_addu(&p, K1, K1, K0); 428 uasm_i_lw(&p, K0, 0, K1); 429 uasm_i_nop(&p); /* load delay */ 430 uasm_i_mtc0(&p, K0, C0_ENTRYLO0); 431 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 432 uasm_i_tlbwr(&p); /* cp0 delay */ 433 uasm_i_jr(&p, K1); 434 uasm_i_rfe(&p); /* branch delay */ 435 436 if (p > tlb_handler + 32) 437 panic("TLB refill handler space exceeded"); 438 439 pr_debug("Wrote TLB refill handler (%u instructions).\n", 440 (unsigned int)(p - tlb_handler)); 441 442 memcpy((void *)ebase, tlb_handler, 0x80); 443 local_flush_icache_range(ebase, ebase + 0x80); 444 dump_handler("r3000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x80)); 445 } 446 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 447 448 /* 449 * The R4000 TLB handler is much more complicated. We have two 450 * consecutive handler areas with 32 instructions space each. 451 * Since they aren't used at the same time, we can overflow in the 452 * other one.To keep things simple, we first assume linear space, 453 * then we relocate it to the final handler layout as needed. 454 */ 455 static u32 final_handler[64]; 456 457 /* 458 * Hazards 459 * 460 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 461 * 2. A timing hazard exists for the TLBP instruction. 462 * 463 * stalling_instruction 464 * TLBP 465 * 466 * The JTLB is being read for the TLBP throughout the stall generated by the 467 * previous instruction. This is not really correct as the stalling instruction 468 * can modify the address used to access the JTLB. The failure symptom is that 469 * the TLBP instruction will use an address created for the stalling instruction 470 * and not the address held in C0_ENHI and thus report the wrong results. 471 * 472 * The software work-around is to not allow the instruction preceding the TLBP 473 * to stall - make it an NOP or some other instruction guaranteed not to stall. 474 * 475 * Errata 2 will not be fixed. This errata is also on the R5000. 476 * 477 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 478 */ 479 static void __maybe_unused build_tlb_probe_entry(u32 **p) 480 { 481 switch (current_cpu_type()) { 482 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ 483 case CPU_R4600: 484 case CPU_R4700: 485 case CPU_R5000: 486 case CPU_NEVADA: 487 uasm_i_nop(p); 488 uasm_i_tlbp(p); 489 break; 490 491 default: 492 uasm_i_tlbp(p); 493 break; 494 } 495 } 496 497 void build_tlb_write_entry(u32 **p, struct uasm_label **l, 498 struct uasm_reloc **r, 499 enum tlb_write_entry wmode) 500 { 501 void(*tlbw)(u32 **) = NULL; 502 503 switch (wmode) { 504 case tlb_random: tlbw = uasm_i_tlbwr; break; 505 case tlb_indexed: tlbw = uasm_i_tlbwi; break; 506 } 507 508 if (cpu_has_mips_r2_r6) { 509 if (cpu_has_mips_r2_exec_hazard) 510 uasm_i_ehb(p); 511 tlbw(p); 512 return; 513 } 514 515 switch (current_cpu_type()) { 516 case CPU_R4000PC: 517 case CPU_R4000SC: 518 case CPU_R4000MC: 519 case CPU_R4400PC: 520 case CPU_R4400SC: 521 case CPU_R4400MC: 522 /* 523 * This branch uses up a mtc0 hazard nop slot and saves 524 * two nops after the tlbw instruction. 525 */ 526 uasm_bgezl_hazard(p, r, hazard_instance); 527 tlbw(p); 528 uasm_bgezl_label(l, p, hazard_instance); 529 hazard_instance++; 530 uasm_i_nop(p); 531 break; 532 533 case CPU_R4600: 534 case CPU_R4700: 535 uasm_i_nop(p); 536 tlbw(p); 537 uasm_i_nop(p); 538 break; 539 540 case CPU_R5000: 541 case CPU_NEVADA: 542 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 543 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 544 tlbw(p); 545 break; 546 547 case CPU_R4300: 548 case CPU_5KC: 549 case CPU_TX49XX: 550 case CPU_PR4450: 551 case CPU_XLR: 552 uasm_i_nop(p); 553 tlbw(p); 554 break; 555 556 case CPU_R10000: 557 case CPU_R12000: 558 case CPU_R14000: 559 case CPU_R16000: 560 case CPU_4KC: 561 case CPU_4KEC: 562 case CPU_M14KC: 563 case CPU_M14KEC: 564 case CPU_SB1: 565 case CPU_SB1A: 566 case CPU_4KSC: 567 case CPU_20KC: 568 case CPU_25KF: 569 case CPU_BMIPS32: 570 case CPU_BMIPS3300: 571 case CPU_BMIPS4350: 572 case CPU_BMIPS4380: 573 case CPU_BMIPS5000: 574 case CPU_LOONGSON2: 575 case CPU_LOONGSON3: 576 case CPU_R5500: 577 if (m4kc_tlbp_war()) 578 uasm_i_nop(p); 579 /* fall through */ 580 case CPU_ALCHEMY: 581 tlbw(p); 582 break; 583 584 case CPU_RM7000: 585 uasm_i_nop(p); 586 uasm_i_nop(p); 587 uasm_i_nop(p); 588 uasm_i_nop(p); 589 tlbw(p); 590 break; 591 592 case CPU_VR4111: 593 case CPU_VR4121: 594 case CPU_VR4122: 595 case CPU_VR4181: 596 case CPU_VR4181A: 597 uasm_i_nop(p); 598 uasm_i_nop(p); 599 tlbw(p); 600 uasm_i_nop(p); 601 uasm_i_nop(p); 602 break; 603 604 case CPU_VR4131: 605 case CPU_VR4133: 606 case CPU_R5432: 607 uasm_i_nop(p); 608 uasm_i_nop(p); 609 tlbw(p); 610 break; 611 612 case CPU_JZRISC: 613 tlbw(p); 614 uasm_i_nop(p); 615 break; 616 617 default: 618 panic("No TLB refill handler yet (CPU type: %d)", 619 current_cpu_type()); 620 break; 621 } 622 } 623 EXPORT_SYMBOL_GPL(build_tlb_write_entry); 624 625 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, 626 unsigned int reg) 627 { 628 if (_PAGE_GLOBAL_SHIFT == 0) { 629 /* pte_t is already in EntryLo format */ 630 return; 631 } 632 633 if (cpu_has_rixi && _PAGE_NO_EXEC) { 634 if (fill_includes_sw_bits) { 635 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); 636 } else { 637 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); 638 UASM_i_ROTR(p, reg, reg, 639 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); 640 } 641 } else { 642 #ifdef CONFIG_PHYS_ADDR_T_64BIT 643 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); 644 #else 645 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); 646 #endif 647 } 648 } 649 650 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 651 652 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, 653 unsigned int tmp, enum label_id lid, 654 int restore_scratch) 655 { 656 if (restore_scratch) { 657 /* Reset default page size */ 658 if (PM_DEFAULT_MASK >> 16) { 659 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 660 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 661 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 662 uasm_il_b(p, r, lid); 663 } else if (PM_DEFAULT_MASK) { 664 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 665 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 666 uasm_il_b(p, r, lid); 667 } else { 668 uasm_i_mtc0(p, 0, C0_PAGEMASK); 669 uasm_il_b(p, r, lid); 670 } 671 if (scratch_reg >= 0) 672 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 673 else 674 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 675 } else { 676 /* Reset default page size */ 677 if (PM_DEFAULT_MASK >> 16) { 678 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 679 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 680 uasm_il_b(p, r, lid); 681 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 682 } else if (PM_DEFAULT_MASK) { 683 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 684 uasm_il_b(p, r, lid); 685 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 686 } else { 687 uasm_il_b(p, r, lid); 688 uasm_i_mtc0(p, 0, C0_PAGEMASK); 689 } 690 } 691 } 692 693 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, 694 struct uasm_reloc **r, 695 unsigned int tmp, 696 enum tlb_write_entry wmode, 697 int restore_scratch) 698 { 699 /* Set huge page tlb entry size */ 700 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); 701 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); 702 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 703 704 build_tlb_write_entry(p, l, r, wmode); 705 706 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); 707 } 708 709 /* 710 * Check if Huge PTE is present, if so then jump to LABEL. 711 */ 712 static void 713 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, 714 unsigned int pmd, int lid) 715 { 716 UASM_i_LW(p, tmp, 0, pmd); 717 if (use_bbit_insns()) { 718 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); 719 } else { 720 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); 721 uasm_il_bnez(p, r, tmp, lid); 722 } 723 } 724 725 static void build_huge_update_entries(u32 **p, unsigned int pte, 726 unsigned int tmp) 727 { 728 int small_sequence; 729 730 /* 731 * A huge PTE describes an area the size of the 732 * configured huge page size. This is twice the 733 * of the large TLB entry size we intend to use. 734 * A TLB entry half the size of the configured 735 * huge page size is configured into entrylo0 736 * and entrylo1 to cover the contiguous huge PTE 737 * address space. 738 */ 739 small_sequence = (HPAGE_SIZE >> 7) < 0x10000; 740 741 /* We can clobber tmp. It isn't used after this.*/ 742 if (!small_sequence) 743 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); 744 745 build_convert_pte_to_entrylo(p, pte); 746 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ 747 /* convert to entrylo1 */ 748 if (small_sequence) 749 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); 750 else 751 UASM_i_ADDU(p, pte, pte, tmp); 752 753 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ 754 } 755 756 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, 757 struct uasm_label **l, 758 unsigned int pte, 759 unsigned int ptr, 760 unsigned int flush) 761 { 762 #ifdef CONFIG_SMP 763 UASM_i_SC(p, pte, 0, ptr); 764 uasm_il_beqz(p, r, pte, label_tlb_huge_update); 765 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ 766 #else 767 UASM_i_SW(p, pte, 0, ptr); 768 #endif 769 if (cpu_has_ftlb && flush) { 770 BUG_ON(!cpu_has_tlbinv); 771 772 UASM_i_MFC0(p, ptr, C0_ENTRYHI); 773 uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); 774 UASM_i_MTC0(p, ptr, C0_ENTRYHI); 775 build_tlb_write_entry(p, l, r, tlb_indexed); 776 777 uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); 778 UASM_i_MTC0(p, ptr, C0_ENTRYHI); 779 build_huge_update_entries(p, pte, ptr); 780 build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0); 781 782 return; 783 } 784 785 build_huge_update_entries(p, pte, ptr); 786 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); 787 } 788 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 789 790 #ifdef CONFIG_64BIT 791 /* 792 * TMP and PTR are scratch. 793 * TMP will be clobbered, PTR will hold the pmd entry. 794 */ 795 void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 796 unsigned int tmp, unsigned int ptr) 797 { 798 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 799 long pgdc = (long)pgd_current; 800 #endif 801 /* 802 * The vmalloc handling is not in the hotpath. 803 */ 804 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 805 806 if (check_for_high_segbits) { 807 /* 808 * The kernel currently implicitely assumes that the 809 * MIPS SEGBITS parameter for the processor is 810 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never 811 * allocate virtual addresses outside the maximum 812 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But 813 * that doesn't prevent user code from accessing the 814 * higher xuseg addresses. Here, we make sure that 815 * everything but the lower xuseg addresses goes down 816 * the module_alloc/vmalloc path. 817 */ 818 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 819 uasm_il_bnez(p, r, ptr, label_vmalloc); 820 } else { 821 uasm_il_bltz(p, r, tmp, label_vmalloc); 822 } 823 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 824 825 if (pgd_reg != -1) { 826 /* pgd is in pgd_reg */ 827 if (cpu_has_ldpte) 828 UASM_i_MFC0(p, ptr, C0_PWBASE); 829 else 830 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 831 } else { 832 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT) 833 /* 834 * &pgd << 11 stored in CONTEXT [23..63]. 835 */ 836 UASM_i_MFC0(p, ptr, C0_CONTEXT); 837 838 /* Clear lower 23 bits of context. */ 839 uasm_i_dins(p, ptr, 0, 0, 23); 840 841 /* 1 0 1 0 1 << 6 xkphys cached */ 842 uasm_i_ori(p, ptr, ptr, 0x540); 843 uasm_i_drotr(p, ptr, ptr, 11); 844 #elif defined(CONFIG_SMP) 845 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); 846 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 847 UASM_i_LA_mostly(p, tmp, pgdc); 848 uasm_i_daddu(p, ptr, ptr, tmp); 849 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 850 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 851 #else 852 UASM_i_LA_mostly(p, ptr, pgdc); 853 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 854 #endif 855 } 856 857 uasm_l_vmalloc_done(l, *p); 858 859 /* get pgd offset in bytes */ 860 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); 861 862 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 863 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 864 #ifndef __PAGETABLE_PUD_FOLDED 865 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 866 uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */ 867 uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */ 868 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3); 869 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */ 870 #endif 871 #ifndef __PAGETABLE_PMD_FOLDED 872 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 873 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 874 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 875 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 876 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 877 #endif 878 } 879 EXPORT_SYMBOL_GPL(build_get_pmde64); 880 881 /* 882 * BVADDR is the faulting address, PTR is scratch. 883 * PTR will hold the pgd for vmalloc. 884 */ 885 static void 886 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 887 unsigned int bvaddr, unsigned int ptr, 888 enum vmalloc64_mode mode) 889 { 890 long swpd = (long)swapper_pg_dir; 891 int single_insn_swpd; 892 int did_vmalloc_branch = 0; 893 894 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); 895 896 uasm_l_vmalloc(l, *p); 897 898 if (mode != not_refill && check_for_high_segbits) { 899 if (single_insn_swpd) { 900 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); 901 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 902 did_vmalloc_branch = 1; 903 /* fall through */ 904 } else { 905 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); 906 } 907 } 908 if (!did_vmalloc_branch) { 909 if (single_insn_swpd) { 910 uasm_il_b(p, r, label_vmalloc_done); 911 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 912 } else { 913 UASM_i_LA_mostly(p, ptr, swpd); 914 uasm_il_b(p, r, label_vmalloc_done); 915 if (uasm_in_compat_space_p(swpd)) 916 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); 917 else 918 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); 919 } 920 } 921 if (mode != not_refill && check_for_high_segbits) { 922 uasm_l_large_segbits_fault(l, *p); 923 /* 924 * We get here if we are an xsseg address, or if we are 925 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. 926 * 927 * Ignoring xsseg (assume disabled so would generate 928 * (address errors?), the only remaining possibility 929 * is the upper xuseg addresses. On processors with 930 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these 931 * addresses would have taken an address error. We try 932 * to mimic that here by taking a load/istream page 933 * fault. 934 */ 935 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 936 uasm_i_sync(p, 0); 937 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); 938 uasm_i_jr(p, ptr); 939 940 if (mode == refill_scratch) { 941 if (scratch_reg >= 0) 942 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 943 else 944 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 945 } else { 946 uasm_i_nop(p); 947 } 948 } 949 } 950 951 #else /* !CONFIG_64BIT */ 952 953 /* 954 * TMP and PTR are scratch. 955 * TMP will be clobbered, PTR will hold the pgd entry. 956 */ 957 void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 958 { 959 if (pgd_reg != -1) { 960 /* pgd is in pgd_reg */ 961 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); 962 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 963 } else { 964 long pgdc = (long)pgd_current; 965 966 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 967 #ifdef CONFIG_SMP 968 uasm_i_mfc0(p, ptr, SMP_CPUID_REG); 969 UASM_i_LA_mostly(p, tmp, pgdc); 970 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 971 uasm_i_addu(p, ptr, tmp, ptr); 972 #else 973 UASM_i_LA_mostly(p, ptr, pgdc); 974 #endif 975 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 976 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 977 } 978 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 979 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); 980 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 981 } 982 EXPORT_SYMBOL_GPL(build_get_pgde32); 983 984 #endif /* !CONFIG_64BIT */ 985 986 static void build_adjust_context(u32 **p, unsigned int ctx) 987 { 988 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 989 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 990 991 switch (current_cpu_type()) { 992 case CPU_VR41XX: 993 case CPU_VR4111: 994 case CPU_VR4121: 995 case CPU_VR4122: 996 case CPU_VR4131: 997 case CPU_VR4181: 998 case CPU_VR4181A: 999 case CPU_VR4133: 1000 shift += 2; 1001 break; 1002 1003 default: 1004 break; 1005 } 1006 1007 if (shift) 1008 UASM_i_SRL(p, ctx, ctx, shift); 1009 uasm_i_andi(p, ctx, ctx, mask); 1010 } 1011 1012 void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1013 { 1014 /* 1015 * Bug workaround for the Nevada. It seems as if under certain 1016 * circumstances the move from cp0_context might produce a 1017 * bogus result when the mfc0 instruction and its consumer are 1018 * in a different cacheline or a load instruction, probably any 1019 * memory reference, is between them. 1020 */ 1021 switch (current_cpu_type()) { 1022 case CPU_NEVADA: 1023 UASM_i_LW(p, ptr, 0, ptr); 1024 GET_CONTEXT(p, tmp); /* get context reg */ 1025 break; 1026 1027 default: 1028 GET_CONTEXT(p, tmp); /* get context reg */ 1029 UASM_i_LW(p, ptr, 0, ptr); 1030 break; 1031 } 1032 1033 build_adjust_context(p, tmp); 1034 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1035 } 1036 EXPORT_SYMBOL_GPL(build_get_ptep); 1037 1038 void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) 1039 { 1040 int pte_off_even = 0; 1041 int pte_off_odd = sizeof(pte_t); 1042 1043 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT) 1044 /* The low 32 bits of EntryLo is stored in pte_high */ 1045 pte_off_even += offsetof(pte_t, pte_high); 1046 pte_off_odd += offsetof(pte_t, pte_high); 1047 #endif 1048 1049 if (IS_ENABLED(CONFIG_XPA)) { 1050 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */ 1051 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1052 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); 1053 1054 if (cpu_has_xpa && !mips_xpa_disabled) { 1055 uasm_i_lw(p, tmp, 0, ptep); 1056 uasm_i_ext(p, tmp, tmp, 0, 24); 1057 uasm_i_mthc0(p, tmp, C0_ENTRYLO0); 1058 } 1059 1060 uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */ 1061 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1062 UASM_i_MTC0(p, tmp, C0_ENTRYLO1); 1063 1064 if (cpu_has_xpa && !mips_xpa_disabled) { 1065 uasm_i_lw(p, tmp, sizeof(pte_t), ptep); 1066 uasm_i_ext(p, tmp, tmp, 0, 24); 1067 uasm_i_mthc0(p, tmp, C0_ENTRYLO1); 1068 } 1069 return; 1070 } 1071 1072 UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */ 1073 UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */ 1074 if (r45k_bvahwbug()) 1075 build_tlb_probe_entry(p); 1076 build_convert_pte_to_entrylo(p, tmp); 1077 if (r4k_250MHZhwbug()) 1078 UASM_i_MTC0(p, 0, C0_ENTRYLO0); 1079 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ 1080 build_convert_pte_to_entrylo(p, ptep); 1081 if (r45k_bvahwbug()) 1082 uasm_i_mfc0(p, tmp, C0_INDEX); 1083 if (r4k_250MHZhwbug()) 1084 UASM_i_MTC0(p, 0, C0_ENTRYLO1); 1085 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ 1086 } 1087 EXPORT_SYMBOL_GPL(build_update_entries); 1088 1089 struct mips_huge_tlb_info { 1090 int huge_pte; 1091 int restore_scratch; 1092 bool need_reload_pte; 1093 }; 1094 1095 static struct mips_huge_tlb_info 1096 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, 1097 struct uasm_reloc **r, unsigned int tmp, 1098 unsigned int ptr, int c0_scratch_reg) 1099 { 1100 struct mips_huge_tlb_info rv; 1101 unsigned int even, odd; 1102 int vmalloc_branch_delay_filled = 0; 1103 const int scratch = 1; /* Our extra working register */ 1104 1105 rv.huge_pte = scratch; 1106 rv.restore_scratch = 0; 1107 rv.need_reload_pte = false; 1108 1109 if (check_for_high_segbits) { 1110 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1111 1112 if (pgd_reg != -1) 1113 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1114 else 1115 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1116 1117 if (c0_scratch_reg >= 0) 1118 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1119 else 1120 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1121 1122 uasm_i_dsrl_safe(p, scratch, tmp, 1123 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1124 uasm_il_bnez(p, r, scratch, label_vmalloc); 1125 1126 if (pgd_reg == -1) { 1127 vmalloc_branch_delay_filled = 1; 1128 /* Clear lower 23 bits of context. */ 1129 uasm_i_dins(p, ptr, 0, 0, 23); 1130 } 1131 } else { 1132 if (pgd_reg != -1) 1133 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1134 else 1135 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1136 1137 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1138 1139 if (c0_scratch_reg >= 0) 1140 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1141 else 1142 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1143 1144 if (pgd_reg == -1) 1145 /* Clear lower 23 bits of context. */ 1146 uasm_i_dins(p, ptr, 0, 0, 23); 1147 1148 uasm_il_bltz(p, r, tmp, label_vmalloc); 1149 } 1150 1151 if (pgd_reg == -1) { 1152 vmalloc_branch_delay_filled = 1; 1153 /* 1 0 1 0 1 << 6 xkphys cached */ 1154 uasm_i_ori(p, ptr, ptr, 0x540); 1155 uasm_i_drotr(p, ptr, ptr, 11); 1156 } 1157 1158 #ifdef __PAGETABLE_PMD_FOLDED 1159 #define LOC_PTEP scratch 1160 #else 1161 #define LOC_PTEP ptr 1162 #endif 1163 1164 if (!vmalloc_branch_delay_filled) 1165 /* get pgd offset in bytes */ 1166 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1167 1168 uasm_l_vmalloc_done(l, *p); 1169 1170 /* 1171 * tmp ptr 1172 * fall-through case = badvaddr *pgd_current 1173 * vmalloc case = badvaddr swapper_pg_dir 1174 */ 1175 1176 if (vmalloc_branch_delay_filled) 1177 /* get pgd offset in bytes */ 1178 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1179 1180 #ifdef __PAGETABLE_PMD_FOLDED 1181 GET_CONTEXT(p, tmp); /* get context reg */ 1182 #endif 1183 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); 1184 1185 if (use_lwx_insns()) { 1186 UASM_i_LWX(p, LOC_PTEP, scratch, ptr); 1187 } else { 1188 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ 1189 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ 1190 } 1191 1192 #ifndef __PAGETABLE_PUD_FOLDED 1193 /* get pud offset in bytes */ 1194 uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3); 1195 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3); 1196 1197 if (use_lwx_insns()) { 1198 UASM_i_LWX(p, ptr, scratch, ptr); 1199 } else { 1200 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1201 UASM_i_LW(p, ptr, 0, ptr); 1202 } 1203 /* ptr contains a pointer to PMD entry */ 1204 /* tmp contains the address */ 1205 #endif 1206 1207 #ifndef __PAGETABLE_PMD_FOLDED 1208 /* get pmd offset in bytes */ 1209 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); 1210 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); 1211 GET_CONTEXT(p, tmp); /* get context reg */ 1212 1213 if (use_lwx_insns()) { 1214 UASM_i_LWX(p, scratch, scratch, ptr); 1215 } else { 1216 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1217 UASM_i_LW(p, scratch, 0, ptr); 1218 } 1219 #endif 1220 /* Adjust the context during the load latency. */ 1221 build_adjust_context(p, tmp); 1222 1223 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1224 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); 1225 /* 1226 * The in the LWX case we don't want to do the load in the 1227 * delay slot. It cannot issue in the same cycle and may be 1228 * speculative and unneeded. 1229 */ 1230 if (use_lwx_insns()) 1231 uasm_i_nop(p); 1232 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 1233 1234 1235 /* build_update_entries */ 1236 if (use_lwx_insns()) { 1237 even = ptr; 1238 odd = tmp; 1239 UASM_i_LWX(p, even, scratch, tmp); 1240 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); 1241 UASM_i_LWX(p, odd, scratch, tmp); 1242 } else { 1243 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ 1244 even = tmp; 1245 odd = ptr; 1246 UASM_i_LW(p, even, 0, ptr); /* get even pte */ 1247 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ 1248 } 1249 if (cpu_has_rixi) { 1250 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); 1251 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1252 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1253 } else { 1254 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); 1255 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1256 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1257 } 1258 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ 1259 1260 if (c0_scratch_reg >= 0) { 1261 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1262 build_tlb_write_entry(p, l, r, tlb_random); 1263 uasm_l_leave(l, *p); 1264 rv.restore_scratch = 1; 1265 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { 1266 build_tlb_write_entry(p, l, r, tlb_random); 1267 uasm_l_leave(l, *p); 1268 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1269 } else { 1270 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1271 build_tlb_write_entry(p, l, r, tlb_random); 1272 uasm_l_leave(l, *p); 1273 rv.restore_scratch = 1; 1274 } 1275 1276 uasm_i_eret(p); /* return from trap */ 1277 1278 return rv; 1279 } 1280 1281 /* 1282 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception 1283 * because EXL == 0. If we wrap, we can also use the 32 instruction 1284 * slots before the XTLB refill exception handler which belong to the 1285 * unused TLB refill exception. 1286 */ 1287 #define MIPS64_REFILL_INSNS 32 1288 1289 static void build_r4000_tlb_refill_handler(void) 1290 { 1291 u32 *p = tlb_handler; 1292 struct uasm_label *l = labels; 1293 struct uasm_reloc *r = relocs; 1294 u32 *f; 1295 unsigned int final_len; 1296 struct mips_huge_tlb_info htlb_info __maybe_unused; 1297 enum vmalloc64_mode vmalloc_mode __maybe_unused; 1298 1299 memset(tlb_handler, 0, sizeof(tlb_handler)); 1300 memset(labels, 0, sizeof(labels)); 1301 memset(relocs, 0, sizeof(relocs)); 1302 memset(final_handler, 0, sizeof(final_handler)); 1303 1304 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { 1305 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, 1306 scratch_reg); 1307 vmalloc_mode = refill_scratch; 1308 } else { 1309 htlb_info.huge_pte = K0; 1310 htlb_info.restore_scratch = 0; 1311 htlb_info.need_reload_pte = true; 1312 vmalloc_mode = refill_noscratch; 1313 /* 1314 * create the plain linear handler 1315 */ 1316 if (bcm1250_m3_war()) { 1317 unsigned int segbits = 44; 1318 1319 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1320 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 1321 uasm_i_xor(&p, K0, K0, K1); 1322 uasm_i_dsrl_safe(&p, K1, K0, 62); 1323 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 1324 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 1325 uasm_i_or(&p, K0, K0, K1); 1326 uasm_il_bnez(&p, &r, K0, label_leave); 1327 /* No need for uasm_i_nop */ 1328 } 1329 1330 #ifdef CONFIG_64BIT 1331 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1332 #else 1333 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1334 #endif 1335 1336 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1337 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); 1338 #endif 1339 1340 build_get_ptep(&p, K0, K1); 1341 build_update_entries(&p, K0, K1); 1342 build_tlb_write_entry(&p, &l, &r, tlb_random); 1343 uasm_l_leave(&l, p); 1344 uasm_i_eret(&p); /* return from trap */ 1345 } 1346 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1347 uasm_l_tlb_huge_update(&l, p); 1348 if (htlb_info.need_reload_pte) 1349 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1); 1350 build_huge_update_entries(&p, htlb_info.huge_pte, K1); 1351 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, 1352 htlb_info.restore_scratch); 1353 #endif 1354 1355 #ifdef CONFIG_64BIT 1356 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); 1357 #endif 1358 1359 /* 1360 * Overflow check: For the 64bit handler, we need at least one 1361 * free instruction slot for the wrap-around branch. In worst 1362 * case, if the intended insertion point is a delay slot, we 1363 * need three, with the second nop'ed and the third being 1364 * unused. 1365 */ 1366 switch (boot_cpu_type()) { 1367 default: 1368 if (sizeof(long) == 4) { 1369 case CPU_LOONGSON2: 1370 /* Loongson2 ebase is different than r4k, we have more space */ 1371 if ((p - tlb_handler) > 64) 1372 panic("TLB refill handler space exceeded"); 1373 /* 1374 * Now fold the handler in the TLB refill handler space. 1375 */ 1376 f = final_handler; 1377 /* Simplest case, just copy the handler. */ 1378 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1379 final_len = p - tlb_handler; 1380 break; 1381 } else { 1382 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) 1383 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) 1384 && uasm_insn_has_bdelay(relocs, 1385 tlb_handler + MIPS64_REFILL_INSNS - 3))) 1386 panic("TLB refill handler space exceeded"); 1387 /* 1388 * Now fold the handler in the TLB refill handler space. 1389 */ 1390 f = final_handler + MIPS64_REFILL_INSNS; 1391 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { 1392 /* Just copy the handler. */ 1393 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1394 final_len = p - tlb_handler; 1395 } else { 1396 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1397 const enum label_id ls = label_tlb_huge_update; 1398 #else 1399 const enum label_id ls = label_vmalloc; 1400 #endif 1401 u32 *split; 1402 int ov = 0; 1403 int i; 1404 1405 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) 1406 ; 1407 BUG_ON(i == ARRAY_SIZE(labels)); 1408 split = labels[i].addr; 1409 1410 /* 1411 * See if we have overflown one way or the other. 1412 */ 1413 if (split > tlb_handler + MIPS64_REFILL_INSNS || 1414 split < p - MIPS64_REFILL_INSNS) 1415 ov = 1; 1416 1417 if (ov) { 1418 /* 1419 * Split two instructions before the end. One 1420 * for the branch and one for the instruction 1421 * in the delay slot. 1422 */ 1423 split = tlb_handler + MIPS64_REFILL_INSNS - 2; 1424 1425 /* 1426 * If the branch would fall in a delay slot, 1427 * we must back up an additional instruction 1428 * so that it is no longer in a delay slot. 1429 */ 1430 if (uasm_insn_has_bdelay(relocs, split - 1)) 1431 split--; 1432 } 1433 /* Copy first part of the handler. */ 1434 uasm_copy_handler(relocs, labels, tlb_handler, split, f); 1435 f += split - tlb_handler; 1436 1437 if (ov) { 1438 /* Insert branch. */ 1439 uasm_l_split(&l, final_handler); 1440 uasm_il_b(&f, &r, label_split); 1441 if (uasm_insn_has_bdelay(relocs, split)) 1442 uasm_i_nop(&f); 1443 else { 1444 uasm_copy_handler(relocs, labels, 1445 split, split + 1, f); 1446 uasm_move_labels(labels, f, f + 1, -1); 1447 f++; 1448 split++; 1449 } 1450 } 1451 1452 /* Copy the rest of the handler. */ 1453 uasm_copy_handler(relocs, labels, split, p, final_handler); 1454 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + 1455 (p - split); 1456 } 1457 } 1458 break; 1459 } 1460 1461 uasm_resolve_relocs(relocs, labels); 1462 pr_debug("Wrote TLB refill handler (%u instructions).\n", 1463 final_len); 1464 1465 memcpy((void *)ebase, final_handler, 0x100); 1466 local_flush_icache_range(ebase, ebase + 0x100); 1467 dump_handler("r4000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x100)); 1468 } 1469 1470 static void setup_pw(void) 1471 { 1472 unsigned long pgd_i, pgd_w; 1473 #ifndef __PAGETABLE_PMD_FOLDED 1474 unsigned long pmd_i, pmd_w; 1475 #endif 1476 unsigned long pt_i, pt_w; 1477 unsigned long pte_i, pte_w; 1478 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1479 unsigned long psn; 1480 1481 psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */ 1482 #endif 1483 pgd_i = PGDIR_SHIFT; /* 1st level PGD */ 1484 #ifndef __PAGETABLE_PMD_FOLDED 1485 pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER; 1486 1487 pmd_i = PMD_SHIFT; /* 2nd level PMD */ 1488 pmd_w = PMD_SHIFT - PAGE_SHIFT; 1489 #else 1490 pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER; 1491 #endif 1492 1493 pt_i = PAGE_SHIFT; /* 3rd level PTE */ 1494 pt_w = PAGE_SHIFT - 3; 1495 1496 pte_i = ilog2(_PAGE_GLOBAL); 1497 pte_w = 0; 1498 1499 #ifndef __PAGETABLE_PMD_FOLDED 1500 write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i); 1501 write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w); 1502 #else 1503 write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i); 1504 write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w); 1505 #endif 1506 1507 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1508 write_c0_pwctl(1 << 6 | psn); 1509 #endif 1510 write_c0_kpgd((long)swapper_pg_dir); 1511 kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */ 1512 } 1513 1514 static void build_loongson3_tlb_refill_handler(void) 1515 { 1516 u32 *p = tlb_handler; 1517 struct uasm_label *l = labels; 1518 struct uasm_reloc *r = relocs; 1519 1520 memset(labels, 0, sizeof(labels)); 1521 memset(relocs, 0, sizeof(relocs)); 1522 memset(tlb_handler, 0, sizeof(tlb_handler)); 1523 1524 if (check_for_high_segbits) { 1525 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1526 uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1527 uasm_il_beqz(&p, &r, K1, label_vmalloc); 1528 uasm_i_nop(&p); 1529 1530 uasm_il_bgez(&p, &r, K0, label_large_segbits_fault); 1531 uasm_i_nop(&p); 1532 uasm_l_vmalloc(&l, p); 1533 } 1534 1535 uasm_i_dmfc0(&p, K1, C0_PGD); 1536 1537 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */ 1538 #ifndef __PAGETABLE_PMD_FOLDED 1539 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */ 1540 #endif 1541 uasm_i_ldpte(&p, K1, 0); /* even */ 1542 uasm_i_ldpte(&p, K1, 1); /* odd */ 1543 uasm_i_tlbwr(&p); 1544 1545 /* restore page mask */ 1546 if (PM_DEFAULT_MASK >> 16) { 1547 uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16); 1548 uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff); 1549 uasm_i_mtc0(&p, K0, C0_PAGEMASK); 1550 } else if (PM_DEFAULT_MASK) { 1551 uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK); 1552 uasm_i_mtc0(&p, K0, C0_PAGEMASK); 1553 } else { 1554 uasm_i_mtc0(&p, 0, C0_PAGEMASK); 1555 } 1556 1557 uasm_i_eret(&p); 1558 1559 if (check_for_high_segbits) { 1560 uasm_l_large_segbits_fault(&l, p); 1561 UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0); 1562 uasm_i_jr(&p, K1); 1563 uasm_i_nop(&p); 1564 } 1565 1566 uasm_resolve_relocs(relocs, labels); 1567 memcpy((void *)(ebase + 0x80), tlb_handler, 0x80); 1568 local_flush_icache_range(ebase + 0x80, ebase + 0x100); 1569 dump_handler("loongson3_tlb_refill", 1570 (u32 *)(ebase + 0x80), (u32 *)(ebase + 0x100)); 1571 } 1572 1573 static void build_setup_pgd(void) 1574 { 1575 const int a0 = 4; 1576 const int __maybe_unused a1 = 5; 1577 const int __maybe_unused a2 = 6; 1578 u32 *p = (u32 *)msk_isa16_mode((ulong)tlbmiss_handler_setup_pgd); 1579 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1580 long pgdc = (long)pgd_current; 1581 #endif 1582 1583 memset(p, 0, tlbmiss_handler_setup_pgd_end - (char *)p); 1584 memset(labels, 0, sizeof(labels)); 1585 memset(relocs, 0, sizeof(relocs)); 1586 pgd_reg = allocate_kscratch(); 1587 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 1588 if (pgd_reg == -1) { 1589 struct uasm_label *l = labels; 1590 struct uasm_reloc *r = relocs; 1591 1592 /* PGD << 11 in c0_Context */ 1593 /* 1594 * If it is a ckseg0 address, convert to a physical 1595 * address. Shifting right by 29 and adding 4 will 1596 * result in zero for these addresses. 1597 * 1598 */ 1599 UASM_i_SRA(&p, a1, a0, 29); 1600 UASM_i_ADDIU(&p, a1, a1, 4); 1601 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); 1602 uasm_i_nop(&p); 1603 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); 1604 uasm_l_tlbl_goaround1(&l, p); 1605 UASM_i_SLL(&p, a0, a0, 11); 1606 uasm_i_jr(&p, 31); 1607 UASM_i_MTC0(&p, a0, C0_CONTEXT); 1608 } else { 1609 /* PGD in c0_KScratch */ 1610 uasm_i_jr(&p, 31); 1611 if (cpu_has_ldpte) 1612 UASM_i_MTC0(&p, a0, C0_PWBASE); 1613 else 1614 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1615 } 1616 #else 1617 #ifdef CONFIG_SMP 1618 /* Save PGD to pgd_current[smp_processor_id()] */ 1619 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); 1620 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); 1621 UASM_i_LA_mostly(&p, a2, pgdc); 1622 UASM_i_ADDU(&p, a2, a2, a1); 1623 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1624 #else 1625 UASM_i_LA_mostly(&p, a2, pgdc); 1626 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1627 #endif /* SMP */ 1628 uasm_i_jr(&p, 31); 1629 1630 /* if pgd_reg is allocated, save PGD also to scratch register */ 1631 if (pgd_reg != -1) 1632 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1633 else 1634 uasm_i_nop(&p); 1635 #endif 1636 if (p >= (u32 *)tlbmiss_handler_setup_pgd_end) 1637 panic("tlbmiss_handler_setup_pgd space exceeded"); 1638 1639 uasm_resolve_relocs(relocs, labels); 1640 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", 1641 (unsigned int)(p - (u32 *)tlbmiss_handler_setup_pgd)); 1642 1643 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, 1644 tlbmiss_handler_setup_pgd_end); 1645 } 1646 1647 static void 1648 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) 1649 { 1650 #ifdef CONFIG_SMP 1651 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 1652 uasm_i_sync(p, 0); 1653 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1654 if (cpu_has_64bits) 1655 uasm_i_lld(p, pte, 0, ptr); 1656 else 1657 # endif 1658 UASM_i_LL(p, pte, 0, ptr); 1659 #else 1660 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1661 if (cpu_has_64bits) 1662 uasm_i_ld(p, pte, 0, ptr); 1663 else 1664 # endif 1665 UASM_i_LW(p, pte, 0, ptr); 1666 #endif 1667 } 1668 1669 static void 1670 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, 1671 unsigned int mode, unsigned int scratch) 1672 { 1673 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1674 unsigned int swmode = mode & ~hwmode; 1675 1676 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) { 1677 uasm_i_lui(p, scratch, swmode >> 16); 1678 uasm_i_or(p, pte, pte, scratch); 1679 BUG_ON(swmode & 0xffff); 1680 } else { 1681 uasm_i_ori(p, pte, pte, mode); 1682 } 1683 1684 #ifdef CONFIG_SMP 1685 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1686 if (cpu_has_64bits) 1687 uasm_i_scd(p, pte, 0, ptr); 1688 else 1689 # endif 1690 UASM_i_SC(p, pte, 0, ptr); 1691 1692 if (r10000_llsc_war()) 1693 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); 1694 else 1695 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1696 1697 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1698 if (!cpu_has_64bits) { 1699 /* no uasm_i_nop needed */ 1700 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1701 uasm_i_ori(p, pte, pte, hwmode); 1702 BUG_ON(hwmode & ~0xffff); 1703 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1704 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1705 /* no uasm_i_nop needed */ 1706 uasm_i_lw(p, pte, 0, ptr); 1707 } else 1708 uasm_i_nop(p); 1709 # else 1710 uasm_i_nop(p); 1711 # endif 1712 #else 1713 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1714 if (cpu_has_64bits) 1715 uasm_i_sd(p, pte, 0, ptr); 1716 else 1717 # endif 1718 UASM_i_SW(p, pte, 0, ptr); 1719 1720 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1721 if (!cpu_has_64bits) { 1722 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1723 uasm_i_ori(p, pte, pte, hwmode); 1724 BUG_ON(hwmode & ~0xffff); 1725 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1726 uasm_i_lw(p, pte, 0, ptr); 1727 } 1728 # endif 1729 #endif 1730 } 1731 1732 /* 1733 * Check if PTE is present, if not then jump to LABEL. PTR points to 1734 * the page table where this PTE is located, PTE will be re-loaded 1735 * with it's original value. 1736 */ 1737 static void 1738 build_pte_present(u32 **p, struct uasm_reloc **r, 1739 int pte, int ptr, int scratch, enum label_id lid) 1740 { 1741 int t = scratch >= 0 ? scratch : pte; 1742 int cur = pte; 1743 1744 if (cpu_has_rixi) { 1745 if (use_bbit_insns()) { 1746 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); 1747 uasm_i_nop(p); 1748 } else { 1749 if (_PAGE_PRESENT_SHIFT) { 1750 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1751 cur = t; 1752 } 1753 uasm_i_andi(p, t, cur, 1); 1754 uasm_il_beqz(p, r, t, lid); 1755 if (pte == t) 1756 /* You lose the SMP race :-(*/ 1757 iPTE_LW(p, pte, ptr); 1758 } 1759 } else { 1760 if (_PAGE_PRESENT_SHIFT) { 1761 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1762 cur = t; 1763 } 1764 uasm_i_andi(p, t, cur, 1765 (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT); 1766 uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT); 1767 uasm_il_bnez(p, r, t, lid); 1768 if (pte == t) 1769 /* You lose the SMP race :-(*/ 1770 iPTE_LW(p, pte, ptr); 1771 } 1772 } 1773 1774 /* Make PTE valid, store result in PTR. */ 1775 static void 1776 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, 1777 unsigned int ptr, unsigned int scratch) 1778 { 1779 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 1780 1781 iPTE_SW(p, r, pte, ptr, mode, scratch); 1782 } 1783 1784 /* 1785 * Check if PTE can be written to, if not branch to LABEL. Regardless 1786 * restore PTE with value from PTR when done. 1787 */ 1788 static void 1789 build_pte_writable(u32 **p, struct uasm_reloc **r, 1790 unsigned int pte, unsigned int ptr, int scratch, 1791 enum label_id lid) 1792 { 1793 int t = scratch >= 0 ? scratch : pte; 1794 int cur = pte; 1795 1796 if (_PAGE_PRESENT_SHIFT) { 1797 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1798 cur = t; 1799 } 1800 uasm_i_andi(p, t, cur, 1801 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1802 uasm_i_xori(p, t, t, 1803 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1804 uasm_il_bnez(p, r, t, lid); 1805 if (pte == t) 1806 /* You lose the SMP race :-(*/ 1807 iPTE_LW(p, pte, ptr); 1808 else 1809 uasm_i_nop(p); 1810 } 1811 1812 /* Make PTE writable, update software status bits as well, then store 1813 * at PTR. 1814 */ 1815 static void 1816 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, 1817 unsigned int ptr, unsigned int scratch) 1818 { 1819 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 1820 | _PAGE_DIRTY); 1821 1822 iPTE_SW(p, r, pte, ptr, mode, scratch); 1823 } 1824 1825 /* 1826 * Check if PTE can be modified, if not branch to LABEL. Regardless 1827 * restore PTE with value from PTR when done. 1828 */ 1829 static void 1830 build_pte_modifiable(u32 **p, struct uasm_reloc **r, 1831 unsigned int pte, unsigned int ptr, int scratch, 1832 enum label_id lid) 1833 { 1834 if (use_bbit_insns()) { 1835 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); 1836 uasm_i_nop(p); 1837 } else { 1838 int t = scratch >= 0 ? scratch : pte; 1839 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT); 1840 uasm_i_andi(p, t, t, 1); 1841 uasm_il_beqz(p, r, t, lid); 1842 if (pte == t) 1843 /* You lose the SMP race :-(*/ 1844 iPTE_LW(p, pte, ptr); 1845 } 1846 } 1847 1848 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1849 1850 1851 /* 1852 * R3000 style TLB load/store/modify handlers. 1853 */ 1854 1855 /* 1856 * This places the pte into ENTRYLO0 and writes it with tlbwi. 1857 * Then it returns. 1858 */ 1859 static void 1860 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 1861 { 1862 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1863 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 1864 uasm_i_tlbwi(p); 1865 uasm_i_jr(p, tmp); 1866 uasm_i_rfe(p); /* branch delay */ 1867 } 1868 1869 /* 1870 * This places the pte into ENTRYLO0 and writes it with tlbwi 1871 * or tlbwr as appropriate. This is because the index register 1872 * may have the probe fail bit set as a result of a trap on a 1873 * kseg2 access, i.e. without refill. Then it returns. 1874 */ 1875 static void 1876 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, 1877 struct uasm_reloc **r, unsigned int pte, 1878 unsigned int tmp) 1879 { 1880 uasm_i_mfc0(p, tmp, C0_INDEX); 1881 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1882 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 1883 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ 1884 uasm_i_tlbwi(p); /* cp0 delay */ 1885 uasm_i_jr(p, tmp); 1886 uasm_i_rfe(p); /* branch delay */ 1887 uasm_l_r3000_write_probe_fail(l, *p); 1888 uasm_i_tlbwr(p); /* cp0 delay */ 1889 uasm_i_jr(p, tmp); 1890 uasm_i_rfe(p); /* branch delay */ 1891 } 1892 1893 static void 1894 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1895 unsigned int ptr) 1896 { 1897 long pgdc = (long)pgd_current; 1898 1899 uasm_i_mfc0(p, pte, C0_BADVADDR); 1900 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ 1901 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 1902 uasm_i_srl(p, pte, pte, 22); /* load delay */ 1903 uasm_i_sll(p, pte, pte, 2); 1904 uasm_i_addu(p, ptr, ptr, pte); 1905 uasm_i_mfc0(p, pte, C0_CONTEXT); 1906 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ 1907 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ 1908 uasm_i_addu(p, ptr, ptr, pte); 1909 uasm_i_lw(p, pte, 0, ptr); 1910 uasm_i_tlbp(p); /* load delay */ 1911 } 1912 1913 static void build_r3000_tlb_load_handler(void) 1914 { 1915 u32 *p = (u32 *)handle_tlbl; 1916 struct uasm_label *l = labels; 1917 struct uasm_reloc *r = relocs; 1918 1919 memset(p, 0, handle_tlbl_end - (char *)p); 1920 memset(labels, 0, sizeof(labels)); 1921 memset(relocs, 0, sizeof(relocs)); 1922 1923 build_r3000_tlbchange_handler_head(&p, K0, K1); 1924 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); 1925 uasm_i_nop(&p); /* load delay */ 1926 build_make_valid(&p, &r, K0, K1, -1); 1927 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1928 1929 uasm_l_nopage_tlbl(&l, p); 1930 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1931 uasm_i_nop(&p); 1932 1933 if (p >= (u32 *)handle_tlbl_end) 1934 panic("TLB load handler fastpath space exceeded"); 1935 1936 uasm_resolve_relocs(relocs, labels); 1937 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1938 (unsigned int)(p - (u32 *)handle_tlbl)); 1939 1940 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_end); 1941 } 1942 1943 static void build_r3000_tlb_store_handler(void) 1944 { 1945 u32 *p = (u32 *)handle_tlbs; 1946 struct uasm_label *l = labels; 1947 struct uasm_reloc *r = relocs; 1948 1949 memset(p, 0, handle_tlbs_end - (char *)p); 1950 memset(labels, 0, sizeof(labels)); 1951 memset(relocs, 0, sizeof(relocs)); 1952 1953 build_r3000_tlbchange_handler_head(&p, K0, K1); 1954 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); 1955 uasm_i_nop(&p); /* load delay */ 1956 build_make_write(&p, &r, K0, K1, -1); 1957 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1958 1959 uasm_l_nopage_tlbs(&l, p); 1960 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1961 uasm_i_nop(&p); 1962 1963 if (p >= (u32 *)handle_tlbs_end) 1964 panic("TLB store handler fastpath space exceeded"); 1965 1966 uasm_resolve_relocs(relocs, labels); 1967 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1968 (unsigned int)(p - (u32 *)handle_tlbs)); 1969 1970 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_end); 1971 } 1972 1973 static void build_r3000_tlb_modify_handler(void) 1974 { 1975 u32 *p = (u32 *)handle_tlbm; 1976 struct uasm_label *l = labels; 1977 struct uasm_reloc *r = relocs; 1978 1979 memset(p, 0, handle_tlbm_end - (char *)p); 1980 memset(labels, 0, sizeof(labels)); 1981 memset(relocs, 0, sizeof(relocs)); 1982 1983 build_r3000_tlbchange_handler_head(&p, K0, K1); 1984 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); 1985 uasm_i_nop(&p); /* load delay */ 1986 build_make_write(&p, &r, K0, K1, -1); 1987 build_r3000_pte_reload_tlbwi(&p, K0, K1); 1988 1989 uasm_l_nopage_tlbm(&l, p); 1990 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1991 uasm_i_nop(&p); 1992 1993 if (p >= (u32 *)handle_tlbm_end) 1994 panic("TLB modify handler fastpath space exceeded"); 1995 1996 uasm_resolve_relocs(relocs, labels); 1997 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 1998 (unsigned int)(p - (u32 *)handle_tlbm)); 1999 2000 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_end); 2001 } 2002 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 2003 2004 static bool cpu_has_tlbex_tlbp_race(void) 2005 { 2006 /* 2007 * When a Hardware Table Walker is running it can replace TLB entries 2008 * at any time, leading to a race between it & the CPU. 2009 */ 2010 if (cpu_has_htw) 2011 return true; 2012 2013 /* 2014 * If the CPU shares FTLB RAM with its siblings then our entry may be 2015 * replaced at any time by a sibling performing a write to the FTLB. 2016 */ 2017 if (cpu_has_shared_ftlb_ram) 2018 return true; 2019 2020 /* In all other cases there ought to be no race condition to handle */ 2021 return false; 2022 } 2023 2024 /* 2025 * R4000 style TLB load/store/modify handlers. 2026 */ 2027 static struct work_registers 2028 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, 2029 struct uasm_reloc **r) 2030 { 2031 struct work_registers wr = build_get_work_registers(p); 2032 2033 #ifdef CONFIG_64BIT 2034 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ 2035 #else 2036 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ 2037 #endif 2038 2039 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2040 /* 2041 * For huge tlb entries, pmd doesn't contain an address but 2042 * instead contains the tlb pte. Check the PAGE_HUGE bit and 2043 * see if we need to jump to huge tlb processing. 2044 */ 2045 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); 2046 #endif 2047 2048 UASM_i_MFC0(p, wr.r1, C0_BADVADDR); 2049 UASM_i_LW(p, wr.r2, 0, wr.r2); 2050 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 2051 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 2052 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); 2053 2054 #ifdef CONFIG_SMP 2055 uasm_l_smp_pgtable_change(l, *p); 2056 #endif 2057 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ 2058 if (!m4kc_tlbp_war()) { 2059 build_tlb_probe_entry(p); 2060 if (cpu_has_tlbex_tlbp_race()) { 2061 /* race condition happens, leaving */ 2062 uasm_i_ehb(p); 2063 uasm_i_mfc0(p, wr.r3, C0_INDEX); 2064 uasm_il_bltz(p, r, wr.r3, label_leave); 2065 uasm_i_nop(p); 2066 } 2067 } 2068 return wr; 2069 } 2070 2071 static void 2072 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, 2073 struct uasm_reloc **r, unsigned int tmp, 2074 unsigned int ptr) 2075 { 2076 uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); 2077 uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); 2078 build_update_entries(p, tmp, ptr); 2079 build_tlb_write_entry(p, l, r, tlb_indexed); 2080 uasm_l_leave(l, *p); 2081 build_restore_work_registers(p); 2082 uasm_i_eret(p); /* return from trap */ 2083 2084 #ifdef CONFIG_64BIT 2085 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); 2086 #endif 2087 } 2088 2089 static void build_r4000_tlb_load_handler(void) 2090 { 2091 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl); 2092 struct uasm_label *l = labels; 2093 struct uasm_reloc *r = relocs; 2094 struct work_registers wr; 2095 2096 memset(p, 0, handle_tlbl_end - (char *)p); 2097 memset(labels, 0, sizeof(labels)); 2098 memset(relocs, 0, sizeof(relocs)); 2099 2100 if (bcm1250_m3_war()) { 2101 unsigned int segbits = 44; 2102 2103 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 2104 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 2105 uasm_i_xor(&p, K0, K0, K1); 2106 uasm_i_dsrl_safe(&p, K1, K0, 62); 2107 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 2108 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 2109 uasm_i_or(&p, K0, K0, K1); 2110 uasm_il_bnez(&p, &r, K0, label_leave); 2111 /* No need for uasm_i_nop */ 2112 } 2113 2114 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2115 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2116 if (m4kc_tlbp_war()) 2117 build_tlb_probe_entry(&p); 2118 2119 if (cpu_has_rixi && !cpu_has_rixiex) { 2120 /* 2121 * If the page is not _PAGE_VALID, RI or XI could not 2122 * have triggered it. Skip the expensive test.. 2123 */ 2124 if (use_bbit_insns()) { 2125 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2126 label_tlbl_goaround1); 2127 } else { 2128 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2129 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); 2130 } 2131 uasm_i_nop(&p); 2132 2133 /* 2134 * Warn if something may race with us & replace the TLB entry 2135 * before we read it here. Everything with such races should 2136 * also have dedicated RiXi exception handlers, so this 2137 * shouldn't be hit. 2138 */ 2139 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path"); 2140 2141 uasm_i_tlbr(&p); 2142 2143 switch (current_cpu_type()) { 2144 default: 2145 if (cpu_has_mips_r2_exec_hazard) { 2146 uasm_i_ehb(&p); 2147 2148 case CPU_CAVIUM_OCTEON: 2149 case CPU_CAVIUM_OCTEON_PLUS: 2150 case CPU_CAVIUM_OCTEON2: 2151 break; 2152 } 2153 } 2154 2155 /* Examine entrylo 0 or 1 based on ptr. */ 2156 if (use_bbit_insns()) { 2157 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2158 } else { 2159 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2160 uasm_i_beqz(&p, wr.r3, 8); 2161 } 2162 /* load it in the delay slot*/ 2163 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2164 /* load it if ptr is odd */ 2165 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2166 /* 2167 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2168 * XI must have triggered it. 2169 */ 2170 if (use_bbit_insns()) { 2171 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); 2172 uasm_i_nop(&p); 2173 uasm_l_tlbl_goaround1(&l, p); 2174 } else { 2175 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2176 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); 2177 uasm_i_nop(&p); 2178 } 2179 uasm_l_tlbl_goaround1(&l, p); 2180 } 2181 build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3); 2182 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2183 2184 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2185 /* 2186 * This is the entry point when build_r4000_tlbchange_handler_head 2187 * spots a huge page. 2188 */ 2189 uasm_l_tlb_huge_update(&l, p); 2190 iPTE_LW(&p, wr.r1, wr.r2); 2191 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2192 build_tlb_probe_entry(&p); 2193 2194 if (cpu_has_rixi && !cpu_has_rixiex) { 2195 /* 2196 * If the page is not _PAGE_VALID, RI or XI could not 2197 * have triggered it. Skip the expensive test.. 2198 */ 2199 if (use_bbit_insns()) { 2200 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2201 label_tlbl_goaround2); 2202 } else { 2203 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2204 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2205 } 2206 uasm_i_nop(&p); 2207 2208 /* 2209 * Warn if something may race with us & replace the TLB entry 2210 * before we read it here. Everything with such races should 2211 * also have dedicated RiXi exception handlers, so this 2212 * shouldn't be hit. 2213 */ 2214 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path"); 2215 2216 uasm_i_tlbr(&p); 2217 2218 switch (current_cpu_type()) { 2219 default: 2220 if (cpu_has_mips_r2_exec_hazard) { 2221 uasm_i_ehb(&p); 2222 2223 case CPU_CAVIUM_OCTEON: 2224 case CPU_CAVIUM_OCTEON_PLUS: 2225 case CPU_CAVIUM_OCTEON2: 2226 break; 2227 } 2228 } 2229 2230 /* Examine entrylo 0 or 1 based on ptr. */ 2231 if (use_bbit_insns()) { 2232 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2233 } else { 2234 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2235 uasm_i_beqz(&p, wr.r3, 8); 2236 } 2237 /* load it in the delay slot*/ 2238 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2239 /* load it if ptr is odd */ 2240 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2241 /* 2242 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2243 * XI must have triggered it. 2244 */ 2245 if (use_bbit_insns()) { 2246 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); 2247 } else { 2248 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2249 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2250 } 2251 if (PM_DEFAULT_MASK == 0) 2252 uasm_i_nop(&p); 2253 /* 2254 * We clobbered C0_PAGEMASK, restore it. On the other branch 2255 * it is restored in build_huge_tlb_write_entry. 2256 */ 2257 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); 2258 2259 uasm_l_tlbl_goaround2(&l, p); 2260 } 2261 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); 2262 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); 2263 #endif 2264 2265 uasm_l_nopage_tlbl(&l, p); 2266 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2267 uasm_i_sync(&p, 0); 2268 build_restore_work_registers(&p); 2269 #ifdef CONFIG_CPU_MICROMIPS 2270 if ((unsigned long)tlb_do_page_fault_0 & 1) { 2271 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); 2272 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); 2273 uasm_i_jr(&p, K0); 2274 } else 2275 #endif 2276 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 2277 uasm_i_nop(&p); 2278 2279 if (p >= (u32 *)handle_tlbl_end) 2280 panic("TLB load handler fastpath space exceeded"); 2281 2282 uasm_resolve_relocs(relocs, labels); 2283 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 2284 (unsigned int)(p - (u32 *)handle_tlbl)); 2285 2286 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_end); 2287 } 2288 2289 static void build_r4000_tlb_store_handler(void) 2290 { 2291 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs); 2292 struct uasm_label *l = labels; 2293 struct uasm_reloc *r = relocs; 2294 struct work_registers wr; 2295 2296 memset(p, 0, handle_tlbs_end - (char *)p); 2297 memset(labels, 0, sizeof(labels)); 2298 memset(relocs, 0, sizeof(relocs)); 2299 2300 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2301 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2302 if (m4kc_tlbp_war()) 2303 build_tlb_probe_entry(&p); 2304 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); 2305 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2306 2307 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2308 /* 2309 * This is the entry point when 2310 * build_r4000_tlbchange_handler_head spots a huge page. 2311 */ 2312 uasm_l_tlb_huge_update(&l, p); 2313 iPTE_LW(&p, wr.r1, wr.r2); 2314 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2315 build_tlb_probe_entry(&p); 2316 uasm_i_ori(&p, wr.r1, wr.r1, 2317 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2318 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); 2319 #endif 2320 2321 uasm_l_nopage_tlbs(&l, p); 2322 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2323 uasm_i_sync(&p, 0); 2324 build_restore_work_registers(&p); 2325 #ifdef CONFIG_CPU_MICROMIPS 2326 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2327 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2328 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2329 uasm_i_jr(&p, K0); 2330 } else 2331 #endif 2332 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2333 uasm_i_nop(&p); 2334 2335 if (p >= (u32 *)handle_tlbs_end) 2336 panic("TLB store handler fastpath space exceeded"); 2337 2338 uasm_resolve_relocs(relocs, labels); 2339 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 2340 (unsigned int)(p - (u32 *)handle_tlbs)); 2341 2342 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_end); 2343 } 2344 2345 static void build_r4000_tlb_modify_handler(void) 2346 { 2347 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm); 2348 struct uasm_label *l = labels; 2349 struct uasm_reloc *r = relocs; 2350 struct work_registers wr; 2351 2352 memset(p, 0, handle_tlbm_end - (char *)p); 2353 memset(labels, 0, sizeof(labels)); 2354 memset(relocs, 0, sizeof(relocs)); 2355 2356 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2357 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2358 if (m4kc_tlbp_war()) 2359 build_tlb_probe_entry(&p); 2360 /* Present and writable bits set, set accessed and dirty bits. */ 2361 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); 2362 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2363 2364 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2365 /* 2366 * This is the entry point when 2367 * build_r4000_tlbchange_handler_head spots a huge page. 2368 */ 2369 uasm_l_tlb_huge_update(&l, p); 2370 iPTE_LW(&p, wr.r1, wr.r2); 2371 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2372 build_tlb_probe_entry(&p); 2373 uasm_i_ori(&p, wr.r1, wr.r1, 2374 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2375 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0); 2376 #endif 2377 2378 uasm_l_nopage_tlbm(&l, p); 2379 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2380 uasm_i_sync(&p, 0); 2381 build_restore_work_registers(&p); 2382 #ifdef CONFIG_CPU_MICROMIPS 2383 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2384 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2385 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2386 uasm_i_jr(&p, K0); 2387 } else 2388 #endif 2389 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2390 uasm_i_nop(&p); 2391 2392 if (p >= (u32 *)handle_tlbm_end) 2393 panic("TLB modify handler fastpath space exceeded"); 2394 2395 uasm_resolve_relocs(relocs, labels); 2396 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2397 (unsigned int)(p - (u32 *)handle_tlbm)); 2398 2399 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_end); 2400 } 2401 2402 static void flush_tlb_handlers(void) 2403 { 2404 local_flush_icache_range((unsigned long)handle_tlbl, 2405 (unsigned long)handle_tlbl_end); 2406 local_flush_icache_range((unsigned long)handle_tlbs, 2407 (unsigned long)handle_tlbs_end); 2408 local_flush_icache_range((unsigned long)handle_tlbm, 2409 (unsigned long)handle_tlbm_end); 2410 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, 2411 (unsigned long)tlbmiss_handler_setup_pgd_end); 2412 } 2413 2414 static void print_htw_config(void) 2415 { 2416 unsigned long config; 2417 unsigned int pwctl; 2418 const int field = 2 * sizeof(unsigned long); 2419 2420 config = read_c0_pwfield(); 2421 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n", 2422 field, config, 2423 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT, 2424 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT, 2425 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT, 2426 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT, 2427 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); 2428 2429 config = read_c0_pwsize(); 2430 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", 2431 field, config, 2432 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT, 2433 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, 2434 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, 2435 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, 2436 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT, 2437 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); 2438 2439 pwctl = read_c0_pwctl(); 2440 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", 2441 pwctl, 2442 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, 2443 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT, 2444 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT, 2445 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT, 2446 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, 2447 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, 2448 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); 2449 } 2450 2451 static void config_htw_params(void) 2452 { 2453 unsigned long pwfield, pwsize, ptei; 2454 unsigned int config; 2455 2456 /* 2457 * We are using 2-level page tables, so we only need to 2458 * setup GDW and PTW appropriately. UDW and MDW will remain 0. 2459 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to 2460 * write values less than 0xc in these fields because the entire 2461 * write will be dropped. As a result of which, we must preserve 2462 * the original reset values and overwrite only what we really want. 2463 */ 2464 2465 pwfield = read_c0_pwfield(); 2466 /* re-initialize the GDI field */ 2467 pwfield &= ~MIPS_PWFIELD_GDI_MASK; 2468 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT; 2469 /* re-initialize the PTI field including the even/odd bit */ 2470 pwfield &= ~MIPS_PWFIELD_PTI_MASK; 2471 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT; 2472 if (CONFIG_PGTABLE_LEVELS >= 3) { 2473 pwfield &= ~MIPS_PWFIELD_MDI_MASK; 2474 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT; 2475 } 2476 /* Set the PTEI right shift */ 2477 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT; 2478 pwfield |= ptei; 2479 write_c0_pwfield(pwfield); 2480 /* Check whether the PTEI value is supported */ 2481 back_to_back_c0_hazard(); 2482 pwfield = read_c0_pwfield(); 2483 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT) 2484 != ptei) { 2485 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled", 2486 ptei); 2487 /* 2488 * Drop option to avoid HTW being enabled via another path 2489 * (eg htw_reset()) 2490 */ 2491 current_cpu_data.options &= ~MIPS_CPU_HTW; 2492 return; 2493 } 2494 2495 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; 2496 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; 2497 if (CONFIG_PGTABLE_LEVELS >= 3) 2498 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; 2499 2500 /* Set pointer size to size of directory pointers */ 2501 if (IS_ENABLED(CONFIG_64BIT)) 2502 pwsize |= MIPS_PWSIZE_PS_MASK; 2503 /* PTEs may be multiple pointers long (e.g. with XPA) */ 2504 pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT) 2505 & MIPS_PWSIZE_PTEW_MASK; 2506 2507 write_c0_pwsize(pwsize); 2508 2509 /* Make sure everything is set before we enable the HTW */ 2510 back_to_back_c0_hazard(); 2511 2512 /* 2513 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of 2514 * the pwctl fields. 2515 */ 2516 config = 1 << MIPS_PWCTL_PWEN_SHIFT; 2517 if (IS_ENABLED(CONFIG_64BIT)) 2518 config |= MIPS_PWCTL_XU_MASK; 2519 write_c0_pwctl(config); 2520 pr_info("Hardware Page Table Walker enabled\n"); 2521 2522 print_htw_config(); 2523 } 2524 2525 static void config_xpa_params(void) 2526 { 2527 #ifdef CONFIG_XPA 2528 unsigned int pagegrain; 2529 2530 if (mips_xpa_disabled) { 2531 pr_info("Extended Physical Addressing (XPA) disabled\n"); 2532 return; 2533 } 2534 2535 pagegrain = read_c0_pagegrain(); 2536 write_c0_pagegrain(pagegrain | PG_ELPA); 2537 back_to_back_c0_hazard(); 2538 pagegrain = read_c0_pagegrain(); 2539 2540 if (pagegrain & PG_ELPA) 2541 pr_info("Extended Physical Addressing (XPA) enabled\n"); 2542 else 2543 panic("Extended Physical Addressing (XPA) disabled"); 2544 #endif 2545 } 2546 2547 static void check_pabits(void) 2548 { 2549 unsigned long entry; 2550 unsigned pabits, fillbits; 2551 2552 if (!cpu_has_rixi || !_PAGE_NO_EXEC) { 2553 /* 2554 * We'll only be making use of the fact that we can rotate bits 2555 * into the fill if the CPU supports RIXI, so don't bother 2556 * probing this for CPUs which don't. 2557 */ 2558 return; 2559 } 2560 2561 write_c0_entrylo0(~0ul); 2562 back_to_back_c0_hazard(); 2563 entry = read_c0_entrylo0(); 2564 2565 /* clear all non-PFN bits */ 2566 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1); 2567 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); 2568 2569 /* find a lower bound on PABITS, and upper bound on fill bits */ 2570 pabits = fls_long(entry) + 6; 2571 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0); 2572 2573 /* minus the RI & XI bits */ 2574 fillbits -= min_t(unsigned, fillbits, 2); 2575 2576 if (fillbits >= ilog2(_PAGE_NO_EXEC)) 2577 fill_includes_sw_bits = true; 2578 2579 pr_debug("Entry* registers contain %u fill bits\n", fillbits); 2580 } 2581 2582 void build_tlb_refill_handler(void) 2583 { 2584 /* 2585 * The refill handler is generated per-CPU, multi-node systems 2586 * may have local storage for it. The other handlers are only 2587 * needed once. 2588 */ 2589 static int run_once = 0; 2590 2591 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi) 2592 panic("Kernels supporting XPA currently require CPUs with RIXI"); 2593 2594 output_pgtable_bits_defines(); 2595 check_pabits(); 2596 2597 #ifdef CONFIG_64BIT 2598 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 2599 #endif 2600 2601 switch (current_cpu_type()) { 2602 case CPU_R2000: 2603 case CPU_R3000: 2604 case CPU_R3000A: 2605 case CPU_R3081E: 2606 case CPU_TX3912: 2607 case CPU_TX3922: 2608 case CPU_TX3927: 2609 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 2610 if (cpu_has_local_ebase) 2611 build_r3000_tlb_refill_handler(); 2612 if (!run_once) { 2613 if (!cpu_has_local_ebase) 2614 build_r3000_tlb_refill_handler(); 2615 build_setup_pgd(); 2616 build_r3000_tlb_load_handler(); 2617 build_r3000_tlb_store_handler(); 2618 build_r3000_tlb_modify_handler(); 2619 flush_tlb_handlers(); 2620 run_once++; 2621 } 2622 #else 2623 panic("No R3000 TLB refill handler"); 2624 #endif 2625 break; 2626 2627 case CPU_R8000: 2628 panic("No R8000 TLB refill handler yet"); 2629 break; 2630 2631 default: 2632 if (cpu_has_ldpte) 2633 setup_pw(); 2634 2635 if (!run_once) { 2636 scratch_reg = allocate_kscratch(); 2637 build_setup_pgd(); 2638 build_r4000_tlb_load_handler(); 2639 build_r4000_tlb_store_handler(); 2640 build_r4000_tlb_modify_handler(); 2641 if (cpu_has_ldpte) 2642 build_loongson3_tlb_refill_handler(); 2643 else if (!cpu_has_local_ebase) 2644 build_r4000_tlb_refill_handler(); 2645 flush_tlb_handlers(); 2646 run_once++; 2647 } 2648 if (cpu_has_local_ebase) 2649 build_r4000_tlb_refill_handler(); 2650 if (cpu_has_xpa) 2651 config_xpa_params(); 2652 if (cpu_has_htw) 2653 config_htw_params(); 2654 } 2655 } 2656