1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 * Copyright (C) 2008, 2009 Cavium Networks, Inc. 12 * Copyright (C) 2011 MIPS Technologies, Inc. 13 * 14 * ... and the days got worse and worse and now you see 15 * I've gone completely out of my mind. 16 * 17 * They're coming to take me a away haha 18 * they're coming to take me a away hoho hihi haha 19 * to the funny farm where code is beautiful all the time ... 20 * 21 * (Condolences to Napoleon XIV) 22 */ 23 24 #include <linux/bug.h> 25 #include <linux/export.h> 26 #include <linux/kernel.h> 27 #include <linux/types.h> 28 #include <linux/smp.h> 29 #include <linux/string.h> 30 #include <linux/cache.h> 31 32 #include <asm/cacheflush.h> 33 #include <asm/cpu-type.h> 34 #include <asm/mmu_context.h> 35 #include <asm/pgtable.h> 36 #include <asm/war.h> 37 #include <asm/uasm.h> 38 #include <asm/setup.h> 39 #include <asm/tlbex.h> 40 41 static int mips_xpa_disabled; 42 43 static int __init xpa_disable(char *s) 44 { 45 mips_xpa_disabled = 1; 46 47 return 1; 48 } 49 50 __setup("noxpa", xpa_disable); 51 52 /* 53 * TLB load/store/modify handlers. 54 * 55 * Only the fastpath gets synthesized at runtime, the slowpath for 56 * do_page_fault remains normal asm. 57 */ 58 extern void tlb_do_page_fault_0(void); 59 extern void tlb_do_page_fault_1(void); 60 61 struct work_registers { 62 int r1; 63 int r2; 64 int r3; 65 }; 66 67 struct tlb_reg_save { 68 unsigned long a; 69 unsigned long b; 70 } ____cacheline_aligned_in_smp; 71 72 static struct tlb_reg_save handler_reg_save[NR_CPUS]; 73 74 static inline int r45k_bvahwbug(void) 75 { 76 /* XXX: We should probe for the presence of this bug, but we don't. */ 77 return 0; 78 } 79 80 static inline int r4k_250MHZhwbug(void) 81 { 82 /* XXX: We should probe for the presence of this bug, but we don't. */ 83 return 0; 84 } 85 86 static inline int __maybe_unused bcm1250_m3_war(void) 87 { 88 return BCM1250_M3_WAR; 89 } 90 91 static inline int __maybe_unused r10000_llsc_war(void) 92 { 93 return R10000_LLSC_WAR; 94 } 95 96 static int use_bbit_insns(void) 97 { 98 switch (current_cpu_type()) { 99 case CPU_CAVIUM_OCTEON: 100 case CPU_CAVIUM_OCTEON_PLUS: 101 case CPU_CAVIUM_OCTEON2: 102 case CPU_CAVIUM_OCTEON3: 103 return 1; 104 default: 105 return 0; 106 } 107 } 108 109 static int use_lwx_insns(void) 110 { 111 switch (current_cpu_type()) { 112 case CPU_CAVIUM_OCTEON2: 113 case CPU_CAVIUM_OCTEON3: 114 return 1; 115 default: 116 return 0; 117 } 118 } 119 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ 120 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 121 static bool scratchpad_available(void) 122 { 123 return true; 124 } 125 static int scratchpad_offset(int i) 126 { 127 /* 128 * CVMSEG starts at address -32768 and extends for 129 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. 130 */ 131 i += 1; /* Kernel use starts at the top and works down. */ 132 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; 133 } 134 #else 135 static bool scratchpad_available(void) 136 { 137 return false; 138 } 139 static int scratchpad_offset(int i) 140 { 141 BUG(); 142 /* Really unreachable, but evidently some GCC want this. */ 143 return 0; 144 } 145 #endif 146 /* 147 * Found by experiment: At least some revisions of the 4kc throw under 148 * some circumstances a machine check exception, triggered by invalid 149 * values in the index register. Delaying the tlbp instruction until 150 * after the next branch, plus adding an additional nop in front of 151 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows 152 * why; it's not an issue caused by the core RTL. 153 * 154 */ 155 static int m4kc_tlbp_war(void) 156 { 157 return current_cpu_type() == CPU_4KC; 158 } 159 160 /* Handle labels (which must be positive integers). */ 161 enum label_id { 162 label_second_part = 1, 163 label_leave, 164 label_vmalloc, 165 label_vmalloc_done, 166 label_tlbw_hazard_0, 167 label_split = label_tlbw_hazard_0 + 8, 168 label_tlbl_goaround1, 169 label_tlbl_goaround2, 170 label_nopage_tlbl, 171 label_nopage_tlbs, 172 label_nopage_tlbm, 173 label_smp_pgtable_change, 174 label_r3000_write_probe_fail, 175 label_large_segbits_fault, 176 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 177 label_tlb_huge_update, 178 #endif 179 }; 180 181 UASM_L_LA(_second_part) 182 UASM_L_LA(_leave) 183 UASM_L_LA(_vmalloc) 184 UASM_L_LA(_vmalloc_done) 185 /* _tlbw_hazard_x is handled differently. */ 186 UASM_L_LA(_split) 187 UASM_L_LA(_tlbl_goaround1) 188 UASM_L_LA(_tlbl_goaround2) 189 UASM_L_LA(_nopage_tlbl) 190 UASM_L_LA(_nopage_tlbs) 191 UASM_L_LA(_nopage_tlbm) 192 UASM_L_LA(_smp_pgtable_change) 193 UASM_L_LA(_r3000_write_probe_fail) 194 UASM_L_LA(_large_segbits_fault) 195 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 196 UASM_L_LA(_tlb_huge_update) 197 #endif 198 199 static int hazard_instance; 200 201 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) 202 { 203 switch (instance) { 204 case 0 ... 7: 205 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); 206 return; 207 default: 208 BUG(); 209 } 210 } 211 212 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) 213 { 214 switch (instance) { 215 case 0 ... 7: 216 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); 217 break; 218 default: 219 BUG(); 220 } 221 } 222 223 /* 224 * pgtable bits are assigned dynamically depending on processor feature 225 * and statically based on kernel configuration. This spits out the actual 226 * values the kernel is using. Required to make sense from disassembled 227 * TLB exception handlers. 228 */ 229 static void output_pgtable_bits_defines(void) 230 { 231 #define pr_define(fmt, ...) \ 232 pr_debug("#define " fmt, ##__VA_ARGS__) 233 234 pr_debug("#include <asm/asm.h>\n"); 235 pr_debug("#include <asm/regdef.h>\n"); 236 pr_debug("\n"); 237 238 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); 239 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); 240 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); 241 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); 242 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); 243 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 244 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); 245 #endif 246 #ifdef _PAGE_NO_EXEC_SHIFT 247 if (cpu_has_rixi) 248 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); 249 #endif 250 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); 251 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); 252 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); 253 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); 254 pr_debug("\n"); 255 } 256 257 static inline void dump_handler(const char *symbol, const void *start, const void *end) 258 { 259 unsigned int count = (end - start) / sizeof(u32); 260 const u32 *handler = start; 261 int i; 262 263 pr_debug("LEAF(%s)\n", symbol); 264 265 pr_debug("\t.set push\n"); 266 pr_debug("\t.set noreorder\n"); 267 268 for (i = 0; i < count; i++) 269 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); 270 271 pr_debug("\t.set\tpop\n"); 272 273 pr_debug("\tEND(%s)\n", symbol); 274 } 275 276 /* The only general purpose registers allowed in TLB handlers. */ 277 #define K0 26 278 #define K1 27 279 280 /* Some CP0 registers */ 281 #define C0_INDEX 0, 0 282 #define C0_ENTRYLO0 2, 0 283 #define C0_TCBIND 2, 2 284 #define C0_ENTRYLO1 3, 0 285 #define C0_CONTEXT 4, 0 286 #define C0_PAGEMASK 5, 0 287 #define C0_PWBASE 5, 5 288 #define C0_PWFIELD 5, 6 289 #define C0_PWSIZE 5, 7 290 #define C0_PWCTL 6, 6 291 #define C0_BADVADDR 8, 0 292 #define C0_PGD 9, 7 293 #define C0_ENTRYHI 10, 0 294 #define C0_EPC 14, 0 295 #define C0_XCONTEXT 20, 0 296 297 #ifdef CONFIG_64BIT 298 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) 299 #else 300 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) 301 #endif 302 303 /* The worst case length of the handler is around 18 instructions for 304 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 305 * Maximum space available is 32 instructions for R3000 and 64 306 * instructions for R4000. 307 * 308 * We deliberately chose a buffer size of 128, so we won't scribble 309 * over anything important on overflow before we panic. 310 */ 311 static u32 tlb_handler[128]; 312 313 /* simply assume worst case size for labels and relocs */ 314 static struct uasm_label labels[128]; 315 static struct uasm_reloc relocs[128]; 316 317 static int check_for_high_segbits; 318 static bool fill_includes_sw_bits; 319 320 static unsigned int kscratch_used_mask; 321 322 static inline int __maybe_unused c0_kscratch(void) 323 { 324 switch (current_cpu_type()) { 325 case CPU_XLP: 326 case CPU_XLR: 327 return 22; 328 default: 329 return 31; 330 } 331 } 332 333 static int allocate_kscratch(void) 334 { 335 int r; 336 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; 337 338 r = ffs(a); 339 340 if (r == 0) 341 return -1; 342 343 r--; /* make it zero based */ 344 345 kscratch_used_mask |= (1 << r); 346 347 return r; 348 } 349 350 static int scratch_reg; 351 int pgd_reg; 352 EXPORT_SYMBOL_GPL(pgd_reg); 353 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; 354 355 static struct work_registers build_get_work_registers(u32 **p) 356 { 357 struct work_registers r; 358 359 if (scratch_reg >= 0) { 360 /* Save in CPU local C0_KScratch? */ 361 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); 362 r.r1 = K0; 363 r.r2 = K1; 364 r.r3 = 1; 365 return r; 366 } 367 368 if (num_possible_cpus() > 1) { 369 /* Get smp_processor_id */ 370 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); 371 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); 372 373 /* handler_reg_save index in K0 */ 374 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); 375 376 UASM_i_LA(p, K1, (long)&handler_reg_save); 377 UASM_i_ADDU(p, K0, K0, K1); 378 } else { 379 UASM_i_LA(p, K0, (long)&handler_reg_save); 380 } 381 /* K0 now points to save area, save $1 and $2 */ 382 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); 383 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); 384 385 r.r1 = K1; 386 r.r2 = 1; 387 r.r3 = 2; 388 return r; 389 } 390 391 static void build_restore_work_registers(u32 **p) 392 { 393 if (scratch_reg >= 0) { 394 uasm_i_ehb(p); 395 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 396 return; 397 } 398 /* K0 already points to save area, restore $1 and $2 */ 399 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); 400 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); 401 } 402 403 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 404 405 /* 406 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, 407 * we cannot do r3000 under these circumstances. 408 * 409 * The R3000 TLB handler is simple. 410 */ 411 static void build_r3000_tlb_refill_handler(void) 412 { 413 long pgdc = (long)pgd_current; 414 u32 *p; 415 416 memset(tlb_handler, 0, sizeof(tlb_handler)); 417 p = tlb_handler; 418 419 uasm_i_mfc0(&p, K0, C0_BADVADDR); 420 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ 421 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); 422 uasm_i_srl(&p, K0, K0, 22); /* load delay */ 423 uasm_i_sll(&p, K0, K0, 2); 424 uasm_i_addu(&p, K1, K1, K0); 425 uasm_i_mfc0(&p, K0, C0_CONTEXT); 426 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ 427 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ 428 uasm_i_addu(&p, K1, K1, K0); 429 uasm_i_lw(&p, K0, 0, K1); 430 uasm_i_nop(&p); /* load delay */ 431 uasm_i_mtc0(&p, K0, C0_ENTRYLO0); 432 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 433 uasm_i_tlbwr(&p); /* cp0 delay */ 434 uasm_i_jr(&p, K1); 435 uasm_i_rfe(&p); /* branch delay */ 436 437 if (p > tlb_handler + 32) 438 panic("TLB refill handler space exceeded"); 439 440 pr_debug("Wrote TLB refill handler (%u instructions).\n", 441 (unsigned int)(p - tlb_handler)); 442 443 memcpy((void *)ebase, tlb_handler, 0x80); 444 local_flush_icache_range(ebase, ebase + 0x80); 445 dump_handler("r3000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x80)); 446 } 447 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 448 449 /* 450 * The R4000 TLB handler is much more complicated. We have two 451 * consecutive handler areas with 32 instructions space each. 452 * Since they aren't used at the same time, we can overflow in the 453 * other one.To keep things simple, we first assume linear space, 454 * then we relocate it to the final handler layout as needed. 455 */ 456 static u32 final_handler[64]; 457 458 /* 459 * Hazards 460 * 461 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 462 * 2. A timing hazard exists for the TLBP instruction. 463 * 464 * stalling_instruction 465 * TLBP 466 * 467 * The JTLB is being read for the TLBP throughout the stall generated by the 468 * previous instruction. This is not really correct as the stalling instruction 469 * can modify the address used to access the JTLB. The failure symptom is that 470 * the TLBP instruction will use an address created for the stalling instruction 471 * and not the address held in C0_ENHI and thus report the wrong results. 472 * 473 * The software work-around is to not allow the instruction preceding the TLBP 474 * to stall - make it an NOP or some other instruction guaranteed not to stall. 475 * 476 * Errata 2 will not be fixed. This errata is also on the R5000. 477 * 478 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 479 */ 480 static void __maybe_unused build_tlb_probe_entry(u32 **p) 481 { 482 switch (current_cpu_type()) { 483 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ 484 case CPU_R4600: 485 case CPU_R4700: 486 case CPU_R5000: 487 case CPU_NEVADA: 488 uasm_i_nop(p); 489 uasm_i_tlbp(p); 490 break; 491 492 default: 493 uasm_i_tlbp(p); 494 break; 495 } 496 } 497 498 void build_tlb_write_entry(u32 **p, struct uasm_label **l, 499 struct uasm_reloc **r, 500 enum tlb_write_entry wmode) 501 { 502 void(*tlbw)(u32 **) = NULL; 503 504 switch (wmode) { 505 case tlb_random: tlbw = uasm_i_tlbwr; break; 506 case tlb_indexed: tlbw = uasm_i_tlbwi; break; 507 } 508 509 if (cpu_has_mips_r2_r6) { 510 if (cpu_has_mips_r2_exec_hazard) 511 uasm_i_ehb(p); 512 tlbw(p); 513 return; 514 } 515 516 switch (current_cpu_type()) { 517 case CPU_R4000PC: 518 case CPU_R4000SC: 519 case CPU_R4000MC: 520 case CPU_R4400PC: 521 case CPU_R4400SC: 522 case CPU_R4400MC: 523 /* 524 * This branch uses up a mtc0 hazard nop slot and saves 525 * two nops after the tlbw instruction. 526 */ 527 uasm_bgezl_hazard(p, r, hazard_instance); 528 tlbw(p); 529 uasm_bgezl_label(l, p, hazard_instance); 530 hazard_instance++; 531 uasm_i_nop(p); 532 break; 533 534 case CPU_R4600: 535 case CPU_R4700: 536 uasm_i_nop(p); 537 tlbw(p); 538 uasm_i_nop(p); 539 break; 540 541 case CPU_R5000: 542 case CPU_NEVADA: 543 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 544 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 545 tlbw(p); 546 break; 547 548 case CPU_5KC: 549 case CPU_TX49XX: 550 case CPU_PR4450: 551 case CPU_XLR: 552 uasm_i_nop(p); 553 tlbw(p); 554 break; 555 556 case CPU_R10000: 557 case CPU_R12000: 558 case CPU_R14000: 559 case CPU_R16000: 560 case CPU_4KC: 561 case CPU_4KEC: 562 case CPU_M14KC: 563 case CPU_M14KEC: 564 case CPU_SB1: 565 case CPU_SB1A: 566 case CPU_4KSC: 567 case CPU_20KC: 568 case CPU_25KF: 569 case CPU_BMIPS32: 570 case CPU_BMIPS3300: 571 case CPU_BMIPS4350: 572 case CPU_BMIPS4380: 573 case CPU_BMIPS5000: 574 case CPU_LOONGSON2: 575 case CPU_LOONGSON3: 576 case CPU_R5500: 577 if (m4kc_tlbp_war()) 578 uasm_i_nop(p); 579 /* fall through */ 580 case CPU_ALCHEMY: 581 tlbw(p); 582 break; 583 584 case CPU_RM7000: 585 uasm_i_nop(p); 586 uasm_i_nop(p); 587 uasm_i_nop(p); 588 uasm_i_nop(p); 589 tlbw(p); 590 break; 591 592 case CPU_VR4111: 593 case CPU_VR4121: 594 case CPU_VR4122: 595 case CPU_VR4181: 596 case CPU_VR4181A: 597 uasm_i_nop(p); 598 uasm_i_nop(p); 599 tlbw(p); 600 uasm_i_nop(p); 601 uasm_i_nop(p); 602 break; 603 604 case CPU_VR4131: 605 case CPU_VR4133: 606 uasm_i_nop(p); 607 uasm_i_nop(p); 608 tlbw(p); 609 break; 610 611 case CPU_XBURST: 612 tlbw(p); 613 uasm_i_nop(p); 614 break; 615 616 default: 617 panic("No TLB refill handler yet (CPU type: %d)", 618 current_cpu_type()); 619 break; 620 } 621 } 622 EXPORT_SYMBOL_GPL(build_tlb_write_entry); 623 624 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, 625 unsigned int reg) 626 { 627 if (_PAGE_GLOBAL_SHIFT == 0) { 628 /* pte_t is already in EntryLo format */ 629 return; 630 } 631 632 if (cpu_has_rixi && !!_PAGE_NO_EXEC) { 633 if (fill_includes_sw_bits) { 634 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); 635 } else { 636 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); 637 UASM_i_ROTR(p, reg, reg, 638 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); 639 } 640 } else { 641 #ifdef CONFIG_PHYS_ADDR_T_64BIT 642 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); 643 #else 644 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); 645 #endif 646 } 647 } 648 649 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 650 651 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, 652 unsigned int tmp, enum label_id lid, 653 int restore_scratch) 654 { 655 if (restore_scratch) { 656 /* Reset default page size */ 657 if (PM_DEFAULT_MASK >> 16) { 658 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 659 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 660 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 661 uasm_il_b(p, r, lid); 662 } else if (PM_DEFAULT_MASK) { 663 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 664 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 665 uasm_il_b(p, r, lid); 666 } else { 667 uasm_i_mtc0(p, 0, C0_PAGEMASK); 668 uasm_il_b(p, r, lid); 669 } 670 if (scratch_reg >= 0) { 671 uasm_i_ehb(p); 672 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 673 } else { 674 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 675 } 676 } else { 677 /* Reset default page size */ 678 if (PM_DEFAULT_MASK >> 16) { 679 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 680 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 681 uasm_il_b(p, r, lid); 682 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 683 } else if (PM_DEFAULT_MASK) { 684 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 685 uasm_il_b(p, r, lid); 686 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 687 } else { 688 uasm_il_b(p, r, lid); 689 uasm_i_mtc0(p, 0, C0_PAGEMASK); 690 } 691 } 692 } 693 694 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, 695 struct uasm_reloc **r, 696 unsigned int tmp, 697 enum tlb_write_entry wmode, 698 int restore_scratch) 699 { 700 /* Set huge page tlb entry size */ 701 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); 702 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); 703 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 704 705 build_tlb_write_entry(p, l, r, wmode); 706 707 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); 708 } 709 710 /* 711 * Check if Huge PTE is present, if so then jump to LABEL. 712 */ 713 static void 714 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, 715 unsigned int pmd, int lid) 716 { 717 UASM_i_LW(p, tmp, 0, pmd); 718 if (use_bbit_insns()) { 719 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); 720 } else { 721 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); 722 uasm_il_bnez(p, r, tmp, lid); 723 } 724 } 725 726 static void build_huge_update_entries(u32 **p, unsigned int pte, 727 unsigned int tmp) 728 { 729 int small_sequence; 730 731 /* 732 * A huge PTE describes an area the size of the 733 * configured huge page size. This is twice the 734 * of the large TLB entry size we intend to use. 735 * A TLB entry half the size of the configured 736 * huge page size is configured into entrylo0 737 * and entrylo1 to cover the contiguous huge PTE 738 * address space. 739 */ 740 small_sequence = (HPAGE_SIZE >> 7) < 0x10000; 741 742 /* We can clobber tmp. It isn't used after this.*/ 743 if (!small_sequence) 744 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); 745 746 build_convert_pte_to_entrylo(p, pte); 747 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ 748 /* convert to entrylo1 */ 749 if (small_sequence) 750 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); 751 else 752 UASM_i_ADDU(p, pte, pte, tmp); 753 754 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ 755 } 756 757 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, 758 struct uasm_label **l, 759 unsigned int pte, 760 unsigned int ptr, 761 unsigned int flush) 762 { 763 #ifdef CONFIG_SMP 764 UASM_i_SC(p, pte, 0, ptr); 765 uasm_il_beqz(p, r, pte, label_tlb_huge_update); 766 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ 767 #else 768 UASM_i_SW(p, pte, 0, ptr); 769 #endif 770 if (cpu_has_ftlb && flush) { 771 BUG_ON(!cpu_has_tlbinv); 772 773 UASM_i_MFC0(p, ptr, C0_ENTRYHI); 774 uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); 775 UASM_i_MTC0(p, ptr, C0_ENTRYHI); 776 build_tlb_write_entry(p, l, r, tlb_indexed); 777 778 uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); 779 UASM_i_MTC0(p, ptr, C0_ENTRYHI); 780 build_huge_update_entries(p, pte, ptr); 781 build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0); 782 783 return; 784 } 785 786 build_huge_update_entries(p, pte, ptr); 787 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); 788 } 789 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 790 791 #ifdef CONFIG_64BIT 792 /* 793 * TMP and PTR are scratch. 794 * TMP will be clobbered, PTR will hold the pmd entry. 795 */ 796 void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 797 unsigned int tmp, unsigned int ptr) 798 { 799 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 800 long pgdc = (long)pgd_current; 801 #endif 802 /* 803 * The vmalloc handling is not in the hotpath. 804 */ 805 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 806 807 if (check_for_high_segbits) { 808 /* 809 * The kernel currently implicitely assumes that the 810 * MIPS SEGBITS parameter for the processor is 811 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never 812 * allocate virtual addresses outside the maximum 813 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But 814 * that doesn't prevent user code from accessing the 815 * higher xuseg addresses. Here, we make sure that 816 * everything but the lower xuseg addresses goes down 817 * the module_alloc/vmalloc path. 818 */ 819 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 820 uasm_il_bnez(p, r, ptr, label_vmalloc); 821 } else { 822 uasm_il_bltz(p, r, tmp, label_vmalloc); 823 } 824 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 825 826 if (pgd_reg != -1) { 827 /* pgd is in pgd_reg */ 828 if (cpu_has_ldpte) 829 UASM_i_MFC0(p, ptr, C0_PWBASE); 830 else 831 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 832 } else { 833 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT) 834 /* 835 * &pgd << 11 stored in CONTEXT [23..63]. 836 */ 837 UASM_i_MFC0(p, ptr, C0_CONTEXT); 838 839 /* Clear lower 23 bits of context. */ 840 uasm_i_dins(p, ptr, 0, 0, 23); 841 842 /* 1 0 1 0 1 << 6 xkphys cached */ 843 uasm_i_ori(p, ptr, ptr, 0x540); 844 uasm_i_drotr(p, ptr, ptr, 11); 845 #elif defined(CONFIG_SMP) 846 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); 847 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 848 UASM_i_LA_mostly(p, tmp, pgdc); 849 uasm_i_daddu(p, ptr, ptr, tmp); 850 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 851 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 852 #else 853 UASM_i_LA_mostly(p, ptr, pgdc); 854 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 855 #endif 856 } 857 858 uasm_l_vmalloc_done(l, *p); 859 860 /* get pgd offset in bytes */ 861 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); 862 863 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 864 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 865 #ifndef __PAGETABLE_PUD_FOLDED 866 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 867 uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */ 868 uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */ 869 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3); 870 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */ 871 #endif 872 #ifndef __PAGETABLE_PMD_FOLDED 873 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 874 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 875 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 876 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 877 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 878 #endif 879 } 880 EXPORT_SYMBOL_GPL(build_get_pmde64); 881 882 /* 883 * BVADDR is the faulting address, PTR is scratch. 884 * PTR will hold the pgd for vmalloc. 885 */ 886 static void 887 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 888 unsigned int bvaddr, unsigned int ptr, 889 enum vmalloc64_mode mode) 890 { 891 long swpd = (long)swapper_pg_dir; 892 int single_insn_swpd; 893 int did_vmalloc_branch = 0; 894 895 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); 896 897 uasm_l_vmalloc(l, *p); 898 899 if (mode != not_refill && check_for_high_segbits) { 900 if (single_insn_swpd) { 901 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); 902 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 903 did_vmalloc_branch = 1; 904 /* fall through */ 905 } else { 906 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); 907 } 908 } 909 if (!did_vmalloc_branch) { 910 if (single_insn_swpd) { 911 uasm_il_b(p, r, label_vmalloc_done); 912 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 913 } else { 914 UASM_i_LA_mostly(p, ptr, swpd); 915 uasm_il_b(p, r, label_vmalloc_done); 916 if (uasm_in_compat_space_p(swpd)) 917 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); 918 else 919 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); 920 } 921 } 922 if (mode != not_refill && check_for_high_segbits) { 923 uasm_l_large_segbits_fault(l, *p); 924 /* 925 * We get here if we are an xsseg address, or if we are 926 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. 927 * 928 * Ignoring xsseg (assume disabled so would generate 929 * (address errors?), the only remaining possibility 930 * is the upper xuseg addresses. On processors with 931 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these 932 * addresses would have taken an address error. We try 933 * to mimic that here by taking a load/istream page 934 * fault. 935 */ 936 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 937 uasm_i_sync(p, 0); 938 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); 939 uasm_i_jr(p, ptr); 940 941 if (mode == refill_scratch) { 942 if (scratch_reg >= 0) { 943 uasm_i_ehb(p); 944 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 945 } else { 946 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 947 } 948 } else { 949 uasm_i_nop(p); 950 } 951 } 952 } 953 954 #else /* !CONFIG_64BIT */ 955 956 /* 957 * TMP and PTR are scratch. 958 * TMP will be clobbered, PTR will hold the pgd entry. 959 */ 960 void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 961 { 962 if (pgd_reg != -1) { 963 /* pgd is in pgd_reg */ 964 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); 965 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 966 } else { 967 long pgdc = (long)pgd_current; 968 969 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 970 #ifdef CONFIG_SMP 971 uasm_i_mfc0(p, ptr, SMP_CPUID_REG); 972 UASM_i_LA_mostly(p, tmp, pgdc); 973 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 974 uasm_i_addu(p, ptr, tmp, ptr); 975 #else 976 UASM_i_LA_mostly(p, ptr, pgdc); 977 #endif 978 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 979 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 980 } 981 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 982 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); 983 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 984 } 985 EXPORT_SYMBOL_GPL(build_get_pgde32); 986 987 #endif /* !CONFIG_64BIT */ 988 989 static void build_adjust_context(u32 **p, unsigned int ctx) 990 { 991 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 992 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 993 994 switch (current_cpu_type()) { 995 case CPU_VR41XX: 996 case CPU_VR4111: 997 case CPU_VR4121: 998 case CPU_VR4122: 999 case CPU_VR4131: 1000 case CPU_VR4181: 1001 case CPU_VR4181A: 1002 case CPU_VR4133: 1003 shift += 2; 1004 break; 1005 1006 default: 1007 break; 1008 } 1009 1010 if (shift) 1011 UASM_i_SRL(p, ctx, ctx, shift); 1012 uasm_i_andi(p, ctx, ctx, mask); 1013 } 1014 1015 void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1016 { 1017 /* 1018 * Bug workaround for the Nevada. It seems as if under certain 1019 * circumstances the move from cp0_context might produce a 1020 * bogus result when the mfc0 instruction and its consumer are 1021 * in a different cacheline or a load instruction, probably any 1022 * memory reference, is between them. 1023 */ 1024 switch (current_cpu_type()) { 1025 case CPU_NEVADA: 1026 UASM_i_LW(p, ptr, 0, ptr); 1027 GET_CONTEXT(p, tmp); /* get context reg */ 1028 break; 1029 1030 default: 1031 GET_CONTEXT(p, tmp); /* get context reg */ 1032 UASM_i_LW(p, ptr, 0, ptr); 1033 break; 1034 } 1035 1036 build_adjust_context(p, tmp); 1037 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1038 } 1039 EXPORT_SYMBOL_GPL(build_get_ptep); 1040 1041 void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) 1042 { 1043 int pte_off_even = 0; 1044 int pte_off_odd = sizeof(pte_t); 1045 1046 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT) 1047 /* The low 32 bits of EntryLo is stored in pte_high */ 1048 pte_off_even += offsetof(pte_t, pte_high); 1049 pte_off_odd += offsetof(pte_t, pte_high); 1050 #endif 1051 1052 if (IS_ENABLED(CONFIG_XPA)) { 1053 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */ 1054 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1055 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); 1056 1057 if (cpu_has_xpa && !mips_xpa_disabled) { 1058 uasm_i_lw(p, tmp, 0, ptep); 1059 uasm_i_ext(p, tmp, tmp, 0, 24); 1060 uasm_i_mthc0(p, tmp, C0_ENTRYLO0); 1061 } 1062 1063 uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */ 1064 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1065 UASM_i_MTC0(p, tmp, C0_ENTRYLO1); 1066 1067 if (cpu_has_xpa && !mips_xpa_disabled) { 1068 uasm_i_lw(p, tmp, sizeof(pte_t), ptep); 1069 uasm_i_ext(p, tmp, tmp, 0, 24); 1070 uasm_i_mthc0(p, tmp, C0_ENTRYLO1); 1071 } 1072 return; 1073 } 1074 1075 UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */ 1076 UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */ 1077 if (r45k_bvahwbug()) 1078 build_tlb_probe_entry(p); 1079 build_convert_pte_to_entrylo(p, tmp); 1080 if (r4k_250MHZhwbug()) 1081 UASM_i_MTC0(p, 0, C0_ENTRYLO0); 1082 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ 1083 build_convert_pte_to_entrylo(p, ptep); 1084 if (r45k_bvahwbug()) 1085 uasm_i_mfc0(p, tmp, C0_INDEX); 1086 if (r4k_250MHZhwbug()) 1087 UASM_i_MTC0(p, 0, C0_ENTRYLO1); 1088 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ 1089 } 1090 EXPORT_SYMBOL_GPL(build_update_entries); 1091 1092 struct mips_huge_tlb_info { 1093 int huge_pte; 1094 int restore_scratch; 1095 bool need_reload_pte; 1096 }; 1097 1098 static struct mips_huge_tlb_info 1099 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, 1100 struct uasm_reloc **r, unsigned int tmp, 1101 unsigned int ptr, int c0_scratch_reg) 1102 { 1103 struct mips_huge_tlb_info rv; 1104 unsigned int even, odd; 1105 int vmalloc_branch_delay_filled = 0; 1106 const int scratch = 1; /* Our extra working register */ 1107 1108 rv.huge_pte = scratch; 1109 rv.restore_scratch = 0; 1110 rv.need_reload_pte = false; 1111 1112 if (check_for_high_segbits) { 1113 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1114 1115 if (pgd_reg != -1) 1116 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1117 else 1118 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1119 1120 if (c0_scratch_reg >= 0) 1121 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1122 else 1123 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1124 1125 uasm_i_dsrl_safe(p, scratch, tmp, 1126 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1127 uasm_il_bnez(p, r, scratch, label_vmalloc); 1128 1129 if (pgd_reg == -1) { 1130 vmalloc_branch_delay_filled = 1; 1131 /* Clear lower 23 bits of context. */ 1132 uasm_i_dins(p, ptr, 0, 0, 23); 1133 } 1134 } else { 1135 if (pgd_reg != -1) 1136 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1137 else 1138 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1139 1140 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1141 1142 if (c0_scratch_reg >= 0) 1143 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1144 else 1145 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1146 1147 if (pgd_reg == -1) 1148 /* Clear lower 23 bits of context. */ 1149 uasm_i_dins(p, ptr, 0, 0, 23); 1150 1151 uasm_il_bltz(p, r, tmp, label_vmalloc); 1152 } 1153 1154 if (pgd_reg == -1) { 1155 vmalloc_branch_delay_filled = 1; 1156 /* 1 0 1 0 1 << 6 xkphys cached */ 1157 uasm_i_ori(p, ptr, ptr, 0x540); 1158 uasm_i_drotr(p, ptr, ptr, 11); 1159 } 1160 1161 #ifdef __PAGETABLE_PMD_FOLDED 1162 #define LOC_PTEP scratch 1163 #else 1164 #define LOC_PTEP ptr 1165 #endif 1166 1167 if (!vmalloc_branch_delay_filled) 1168 /* get pgd offset in bytes */ 1169 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1170 1171 uasm_l_vmalloc_done(l, *p); 1172 1173 /* 1174 * tmp ptr 1175 * fall-through case = badvaddr *pgd_current 1176 * vmalloc case = badvaddr swapper_pg_dir 1177 */ 1178 1179 if (vmalloc_branch_delay_filled) 1180 /* get pgd offset in bytes */ 1181 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1182 1183 #ifdef __PAGETABLE_PMD_FOLDED 1184 GET_CONTEXT(p, tmp); /* get context reg */ 1185 #endif 1186 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); 1187 1188 if (use_lwx_insns()) { 1189 UASM_i_LWX(p, LOC_PTEP, scratch, ptr); 1190 } else { 1191 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ 1192 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ 1193 } 1194 1195 #ifndef __PAGETABLE_PUD_FOLDED 1196 /* get pud offset in bytes */ 1197 uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3); 1198 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3); 1199 1200 if (use_lwx_insns()) { 1201 UASM_i_LWX(p, ptr, scratch, ptr); 1202 } else { 1203 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1204 UASM_i_LW(p, ptr, 0, ptr); 1205 } 1206 /* ptr contains a pointer to PMD entry */ 1207 /* tmp contains the address */ 1208 #endif 1209 1210 #ifndef __PAGETABLE_PMD_FOLDED 1211 /* get pmd offset in bytes */ 1212 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); 1213 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); 1214 GET_CONTEXT(p, tmp); /* get context reg */ 1215 1216 if (use_lwx_insns()) { 1217 UASM_i_LWX(p, scratch, scratch, ptr); 1218 } else { 1219 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1220 UASM_i_LW(p, scratch, 0, ptr); 1221 } 1222 #endif 1223 /* Adjust the context during the load latency. */ 1224 build_adjust_context(p, tmp); 1225 1226 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1227 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); 1228 /* 1229 * The in the LWX case we don't want to do the load in the 1230 * delay slot. It cannot issue in the same cycle and may be 1231 * speculative and unneeded. 1232 */ 1233 if (use_lwx_insns()) 1234 uasm_i_nop(p); 1235 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 1236 1237 1238 /* build_update_entries */ 1239 if (use_lwx_insns()) { 1240 even = ptr; 1241 odd = tmp; 1242 UASM_i_LWX(p, even, scratch, tmp); 1243 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); 1244 UASM_i_LWX(p, odd, scratch, tmp); 1245 } else { 1246 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ 1247 even = tmp; 1248 odd = ptr; 1249 UASM_i_LW(p, even, 0, ptr); /* get even pte */ 1250 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ 1251 } 1252 if (cpu_has_rixi) { 1253 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); 1254 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1255 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1256 } else { 1257 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); 1258 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1259 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1260 } 1261 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ 1262 1263 if (c0_scratch_reg >= 0) { 1264 uasm_i_ehb(p); 1265 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1266 build_tlb_write_entry(p, l, r, tlb_random); 1267 uasm_l_leave(l, *p); 1268 rv.restore_scratch = 1; 1269 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { 1270 build_tlb_write_entry(p, l, r, tlb_random); 1271 uasm_l_leave(l, *p); 1272 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1273 } else { 1274 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1275 build_tlb_write_entry(p, l, r, tlb_random); 1276 uasm_l_leave(l, *p); 1277 rv.restore_scratch = 1; 1278 } 1279 1280 uasm_i_eret(p); /* return from trap */ 1281 1282 return rv; 1283 } 1284 1285 /* 1286 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception 1287 * because EXL == 0. If we wrap, we can also use the 32 instruction 1288 * slots before the XTLB refill exception handler which belong to the 1289 * unused TLB refill exception. 1290 */ 1291 #define MIPS64_REFILL_INSNS 32 1292 1293 static void build_r4000_tlb_refill_handler(void) 1294 { 1295 u32 *p = tlb_handler; 1296 struct uasm_label *l = labels; 1297 struct uasm_reloc *r = relocs; 1298 u32 *f; 1299 unsigned int final_len; 1300 struct mips_huge_tlb_info htlb_info __maybe_unused; 1301 enum vmalloc64_mode vmalloc_mode __maybe_unused; 1302 1303 memset(tlb_handler, 0, sizeof(tlb_handler)); 1304 memset(labels, 0, sizeof(labels)); 1305 memset(relocs, 0, sizeof(relocs)); 1306 memset(final_handler, 0, sizeof(final_handler)); 1307 1308 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { 1309 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, 1310 scratch_reg); 1311 vmalloc_mode = refill_scratch; 1312 } else { 1313 htlb_info.huge_pte = K0; 1314 htlb_info.restore_scratch = 0; 1315 htlb_info.need_reload_pte = true; 1316 vmalloc_mode = refill_noscratch; 1317 /* 1318 * create the plain linear handler 1319 */ 1320 if (bcm1250_m3_war()) { 1321 unsigned int segbits = 44; 1322 1323 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1324 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 1325 uasm_i_xor(&p, K0, K0, K1); 1326 uasm_i_dsrl_safe(&p, K1, K0, 62); 1327 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 1328 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 1329 uasm_i_or(&p, K0, K0, K1); 1330 uasm_il_bnez(&p, &r, K0, label_leave); 1331 /* No need for uasm_i_nop */ 1332 } 1333 1334 #ifdef CONFIG_64BIT 1335 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1336 #else 1337 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1338 #endif 1339 1340 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1341 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); 1342 #endif 1343 1344 build_get_ptep(&p, K0, K1); 1345 build_update_entries(&p, K0, K1); 1346 build_tlb_write_entry(&p, &l, &r, tlb_random); 1347 uasm_l_leave(&l, p); 1348 uasm_i_eret(&p); /* return from trap */ 1349 } 1350 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1351 uasm_l_tlb_huge_update(&l, p); 1352 if (htlb_info.need_reload_pte) 1353 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1); 1354 build_huge_update_entries(&p, htlb_info.huge_pte, K1); 1355 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, 1356 htlb_info.restore_scratch); 1357 #endif 1358 1359 #ifdef CONFIG_64BIT 1360 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); 1361 #endif 1362 1363 /* 1364 * Overflow check: For the 64bit handler, we need at least one 1365 * free instruction slot for the wrap-around branch. In worst 1366 * case, if the intended insertion point is a delay slot, we 1367 * need three, with the second nop'ed and the third being 1368 * unused. 1369 */ 1370 switch (boot_cpu_type()) { 1371 default: 1372 if (sizeof(long) == 4) { 1373 case CPU_LOONGSON2: 1374 /* Loongson2 ebase is different than r4k, we have more space */ 1375 if ((p - tlb_handler) > 64) 1376 panic("TLB refill handler space exceeded"); 1377 /* 1378 * Now fold the handler in the TLB refill handler space. 1379 */ 1380 f = final_handler; 1381 /* Simplest case, just copy the handler. */ 1382 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1383 final_len = p - tlb_handler; 1384 break; 1385 } else { 1386 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) 1387 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) 1388 && uasm_insn_has_bdelay(relocs, 1389 tlb_handler + MIPS64_REFILL_INSNS - 3))) 1390 panic("TLB refill handler space exceeded"); 1391 /* 1392 * Now fold the handler in the TLB refill handler space. 1393 */ 1394 f = final_handler + MIPS64_REFILL_INSNS; 1395 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { 1396 /* Just copy the handler. */ 1397 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1398 final_len = p - tlb_handler; 1399 } else { 1400 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1401 const enum label_id ls = label_tlb_huge_update; 1402 #else 1403 const enum label_id ls = label_vmalloc; 1404 #endif 1405 u32 *split; 1406 int ov = 0; 1407 int i; 1408 1409 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) 1410 ; 1411 BUG_ON(i == ARRAY_SIZE(labels)); 1412 split = labels[i].addr; 1413 1414 /* 1415 * See if we have overflown one way or the other. 1416 */ 1417 if (split > tlb_handler + MIPS64_REFILL_INSNS || 1418 split < p - MIPS64_REFILL_INSNS) 1419 ov = 1; 1420 1421 if (ov) { 1422 /* 1423 * Split two instructions before the end. One 1424 * for the branch and one for the instruction 1425 * in the delay slot. 1426 */ 1427 split = tlb_handler + MIPS64_REFILL_INSNS - 2; 1428 1429 /* 1430 * If the branch would fall in a delay slot, 1431 * we must back up an additional instruction 1432 * so that it is no longer in a delay slot. 1433 */ 1434 if (uasm_insn_has_bdelay(relocs, split - 1)) 1435 split--; 1436 } 1437 /* Copy first part of the handler. */ 1438 uasm_copy_handler(relocs, labels, tlb_handler, split, f); 1439 f += split - tlb_handler; 1440 1441 if (ov) { 1442 /* Insert branch. */ 1443 uasm_l_split(&l, final_handler); 1444 uasm_il_b(&f, &r, label_split); 1445 if (uasm_insn_has_bdelay(relocs, split)) 1446 uasm_i_nop(&f); 1447 else { 1448 uasm_copy_handler(relocs, labels, 1449 split, split + 1, f); 1450 uasm_move_labels(labels, f, f + 1, -1); 1451 f++; 1452 split++; 1453 } 1454 } 1455 1456 /* Copy the rest of the handler. */ 1457 uasm_copy_handler(relocs, labels, split, p, final_handler); 1458 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + 1459 (p - split); 1460 } 1461 } 1462 break; 1463 } 1464 1465 uasm_resolve_relocs(relocs, labels); 1466 pr_debug("Wrote TLB refill handler (%u instructions).\n", 1467 final_len); 1468 1469 memcpy((void *)ebase, final_handler, 0x100); 1470 local_flush_icache_range(ebase, ebase + 0x100); 1471 dump_handler("r4000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x100)); 1472 } 1473 1474 static void setup_pw(void) 1475 { 1476 unsigned long pgd_i, pgd_w; 1477 #ifndef __PAGETABLE_PMD_FOLDED 1478 unsigned long pmd_i, pmd_w; 1479 #endif 1480 unsigned long pt_i, pt_w; 1481 unsigned long pte_i, pte_w; 1482 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1483 unsigned long psn; 1484 1485 psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */ 1486 #endif 1487 pgd_i = PGDIR_SHIFT; /* 1st level PGD */ 1488 #ifndef __PAGETABLE_PMD_FOLDED 1489 pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER; 1490 1491 pmd_i = PMD_SHIFT; /* 2nd level PMD */ 1492 pmd_w = PMD_SHIFT - PAGE_SHIFT; 1493 #else 1494 pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER; 1495 #endif 1496 1497 pt_i = PAGE_SHIFT; /* 3rd level PTE */ 1498 pt_w = PAGE_SHIFT - 3; 1499 1500 pte_i = ilog2(_PAGE_GLOBAL); 1501 pte_w = 0; 1502 1503 #ifndef __PAGETABLE_PMD_FOLDED 1504 write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i); 1505 write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w); 1506 #else 1507 write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i); 1508 write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w); 1509 #endif 1510 1511 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1512 write_c0_pwctl(1 << 6 | psn); 1513 #endif 1514 write_c0_kpgd((long)swapper_pg_dir); 1515 kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */ 1516 } 1517 1518 static void build_loongson3_tlb_refill_handler(void) 1519 { 1520 u32 *p = tlb_handler; 1521 struct uasm_label *l = labels; 1522 struct uasm_reloc *r = relocs; 1523 1524 memset(labels, 0, sizeof(labels)); 1525 memset(relocs, 0, sizeof(relocs)); 1526 memset(tlb_handler, 0, sizeof(tlb_handler)); 1527 1528 if (check_for_high_segbits) { 1529 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1530 uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1531 uasm_il_beqz(&p, &r, K1, label_vmalloc); 1532 uasm_i_nop(&p); 1533 1534 uasm_il_bgez(&p, &r, K0, label_large_segbits_fault); 1535 uasm_i_nop(&p); 1536 uasm_l_vmalloc(&l, p); 1537 } 1538 1539 uasm_i_dmfc0(&p, K1, C0_PGD); 1540 1541 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */ 1542 #ifndef __PAGETABLE_PMD_FOLDED 1543 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */ 1544 #endif 1545 uasm_i_ldpte(&p, K1, 0); /* even */ 1546 uasm_i_ldpte(&p, K1, 1); /* odd */ 1547 uasm_i_tlbwr(&p); 1548 1549 /* restore page mask */ 1550 if (PM_DEFAULT_MASK >> 16) { 1551 uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16); 1552 uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff); 1553 uasm_i_mtc0(&p, K0, C0_PAGEMASK); 1554 } else if (PM_DEFAULT_MASK) { 1555 uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK); 1556 uasm_i_mtc0(&p, K0, C0_PAGEMASK); 1557 } else { 1558 uasm_i_mtc0(&p, 0, C0_PAGEMASK); 1559 } 1560 1561 uasm_i_eret(&p); 1562 1563 if (check_for_high_segbits) { 1564 uasm_l_large_segbits_fault(&l, p); 1565 UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0); 1566 uasm_i_jr(&p, K1); 1567 uasm_i_nop(&p); 1568 } 1569 1570 uasm_resolve_relocs(relocs, labels); 1571 memcpy((void *)(ebase + 0x80), tlb_handler, 0x80); 1572 local_flush_icache_range(ebase + 0x80, ebase + 0x100); 1573 dump_handler("loongson3_tlb_refill", 1574 (u32 *)(ebase + 0x80), (u32 *)(ebase + 0x100)); 1575 } 1576 1577 static void build_setup_pgd(void) 1578 { 1579 const int a0 = 4; 1580 const int __maybe_unused a1 = 5; 1581 const int __maybe_unused a2 = 6; 1582 u32 *p = (u32 *)msk_isa16_mode((ulong)tlbmiss_handler_setup_pgd); 1583 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1584 long pgdc = (long)pgd_current; 1585 #endif 1586 1587 memset(p, 0, tlbmiss_handler_setup_pgd_end - (char *)p); 1588 memset(labels, 0, sizeof(labels)); 1589 memset(relocs, 0, sizeof(relocs)); 1590 pgd_reg = allocate_kscratch(); 1591 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 1592 if (pgd_reg == -1) { 1593 struct uasm_label *l = labels; 1594 struct uasm_reloc *r = relocs; 1595 1596 /* PGD << 11 in c0_Context */ 1597 /* 1598 * If it is a ckseg0 address, convert to a physical 1599 * address. Shifting right by 29 and adding 4 will 1600 * result in zero for these addresses. 1601 * 1602 */ 1603 UASM_i_SRA(&p, a1, a0, 29); 1604 UASM_i_ADDIU(&p, a1, a1, 4); 1605 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); 1606 uasm_i_nop(&p); 1607 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); 1608 uasm_l_tlbl_goaround1(&l, p); 1609 UASM_i_SLL(&p, a0, a0, 11); 1610 UASM_i_MTC0(&p, a0, C0_CONTEXT); 1611 uasm_i_jr(&p, 31); 1612 uasm_i_ehb(&p); 1613 } else { 1614 /* PGD in c0_KScratch */ 1615 if (cpu_has_ldpte) 1616 UASM_i_MTC0(&p, a0, C0_PWBASE); 1617 else 1618 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1619 uasm_i_jr(&p, 31); 1620 uasm_i_ehb(&p); 1621 } 1622 #else 1623 #ifdef CONFIG_SMP 1624 /* Save PGD to pgd_current[smp_processor_id()] */ 1625 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); 1626 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); 1627 UASM_i_LA_mostly(&p, a2, pgdc); 1628 UASM_i_ADDU(&p, a2, a2, a1); 1629 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1630 #else 1631 UASM_i_LA_mostly(&p, a2, pgdc); 1632 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1633 #endif /* SMP */ 1634 1635 /* if pgd_reg is allocated, save PGD also to scratch register */ 1636 if (pgd_reg != -1) { 1637 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1638 uasm_i_jr(&p, 31); 1639 uasm_i_ehb(&p); 1640 } else { 1641 uasm_i_jr(&p, 31); 1642 uasm_i_nop(&p); 1643 } 1644 #endif 1645 if (p >= (u32 *)tlbmiss_handler_setup_pgd_end) 1646 panic("tlbmiss_handler_setup_pgd space exceeded"); 1647 1648 uasm_resolve_relocs(relocs, labels); 1649 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", 1650 (unsigned int)(p - (u32 *)tlbmiss_handler_setup_pgd)); 1651 1652 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, 1653 tlbmiss_handler_setup_pgd_end); 1654 } 1655 1656 static void 1657 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) 1658 { 1659 #ifdef CONFIG_SMP 1660 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 1661 uasm_i_sync(p, 0); 1662 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1663 if (cpu_has_64bits) 1664 uasm_i_lld(p, pte, 0, ptr); 1665 else 1666 # endif 1667 UASM_i_LL(p, pte, 0, ptr); 1668 #else 1669 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1670 if (cpu_has_64bits) 1671 uasm_i_ld(p, pte, 0, ptr); 1672 else 1673 # endif 1674 UASM_i_LW(p, pte, 0, ptr); 1675 #endif 1676 } 1677 1678 static void 1679 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, 1680 unsigned int mode, unsigned int scratch) 1681 { 1682 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1683 unsigned int swmode = mode & ~hwmode; 1684 1685 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) { 1686 uasm_i_lui(p, scratch, swmode >> 16); 1687 uasm_i_or(p, pte, pte, scratch); 1688 BUG_ON(swmode & 0xffff); 1689 } else { 1690 uasm_i_ori(p, pte, pte, mode); 1691 } 1692 1693 #ifdef CONFIG_SMP 1694 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1695 if (cpu_has_64bits) 1696 uasm_i_scd(p, pte, 0, ptr); 1697 else 1698 # endif 1699 UASM_i_SC(p, pte, 0, ptr); 1700 1701 if (r10000_llsc_war()) 1702 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); 1703 else 1704 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1705 1706 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1707 if (!cpu_has_64bits) { 1708 /* no uasm_i_nop needed */ 1709 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1710 uasm_i_ori(p, pte, pte, hwmode); 1711 BUG_ON(hwmode & ~0xffff); 1712 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1713 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1714 /* no uasm_i_nop needed */ 1715 uasm_i_lw(p, pte, 0, ptr); 1716 } else 1717 uasm_i_nop(p); 1718 # else 1719 uasm_i_nop(p); 1720 # endif 1721 #else 1722 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1723 if (cpu_has_64bits) 1724 uasm_i_sd(p, pte, 0, ptr); 1725 else 1726 # endif 1727 UASM_i_SW(p, pte, 0, ptr); 1728 1729 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1730 if (!cpu_has_64bits) { 1731 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1732 uasm_i_ori(p, pte, pte, hwmode); 1733 BUG_ON(hwmode & ~0xffff); 1734 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1735 uasm_i_lw(p, pte, 0, ptr); 1736 } 1737 # endif 1738 #endif 1739 } 1740 1741 /* 1742 * Check if PTE is present, if not then jump to LABEL. PTR points to 1743 * the page table where this PTE is located, PTE will be re-loaded 1744 * with it's original value. 1745 */ 1746 static void 1747 build_pte_present(u32 **p, struct uasm_reloc **r, 1748 int pte, int ptr, int scratch, enum label_id lid) 1749 { 1750 int t = scratch >= 0 ? scratch : pte; 1751 int cur = pte; 1752 1753 if (cpu_has_rixi) { 1754 if (use_bbit_insns()) { 1755 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); 1756 uasm_i_nop(p); 1757 } else { 1758 if (_PAGE_PRESENT_SHIFT) { 1759 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1760 cur = t; 1761 } 1762 uasm_i_andi(p, t, cur, 1); 1763 uasm_il_beqz(p, r, t, lid); 1764 if (pte == t) 1765 /* You lose the SMP race :-(*/ 1766 iPTE_LW(p, pte, ptr); 1767 } 1768 } else { 1769 if (_PAGE_PRESENT_SHIFT) { 1770 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1771 cur = t; 1772 } 1773 uasm_i_andi(p, t, cur, 1774 (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT); 1775 uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT); 1776 uasm_il_bnez(p, r, t, lid); 1777 if (pte == t) 1778 /* You lose the SMP race :-(*/ 1779 iPTE_LW(p, pte, ptr); 1780 } 1781 } 1782 1783 /* Make PTE valid, store result in PTR. */ 1784 static void 1785 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, 1786 unsigned int ptr, unsigned int scratch) 1787 { 1788 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 1789 1790 iPTE_SW(p, r, pte, ptr, mode, scratch); 1791 } 1792 1793 /* 1794 * Check if PTE can be written to, if not branch to LABEL. Regardless 1795 * restore PTE with value from PTR when done. 1796 */ 1797 static void 1798 build_pte_writable(u32 **p, struct uasm_reloc **r, 1799 unsigned int pte, unsigned int ptr, int scratch, 1800 enum label_id lid) 1801 { 1802 int t = scratch >= 0 ? scratch : pte; 1803 int cur = pte; 1804 1805 if (_PAGE_PRESENT_SHIFT) { 1806 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1807 cur = t; 1808 } 1809 uasm_i_andi(p, t, cur, 1810 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1811 uasm_i_xori(p, t, t, 1812 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1813 uasm_il_bnez(p, r, t, lid); 1814 if (pte == t) 1815 /* You lose the SMP race :-(*/ 1816 iPTE_LW(p, pte, ptr); 1817 else 1818 uasm_i_nop(p); 1819 } 1820 1821 /* Make PTE writable, update software status bits as well, then store 1822 * at PTR. 1823 */ 1824 static void 1825 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, 1826 unsigned int ptr, unsigned int scratch) 1827 { 1828 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 1829 | _PAGE_DIRTY); 1830 1831 iPTE_SW(p, r, pte, ptr, mode, scratch); 1832 } 1833 1834 /* 1835 * Check if PTE can be modified, if not branch to LABEL. Regardless 1836 * restore PTE with value from PTR when done. 1837 */ 1838 static void 1839 build_pte_modifiable(u32 **p, struct uasm_reloc **r, 1840 unsigned int pte, unsigned int ptr, int scratch, 1841 enum label_id lid) 1842 { 1843 if (use_bbit_insns()) { 1844 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); 1845 uasm_i_nop(p); 1846 } else { 1847 int t = scratch >= 0 ? scratch : pte; 1848 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT); 1849 uasm_i_andi(p, t, t, 1); 1850 uasm_il_beqz(p, r, t, lid); 1851 if (pte == t) 1852 /* You lose the SMP race :-(*/ 1853 iPTE_LW(p, pte, ptr); 1854 } 1855 } 1856 1857 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1858 1859 1860 /* 1861 * R3000 style TLB load/store/modify handlers. 1862 */ 1863 1864 /* 1865 * This places the pte into ENTRYLO0 and writes it with tlbwi. 1866 * Then it returns. 1867 */ 1868 static void 1869 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 1870 { 1871 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1872 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 1873 uasm_i_tlbwi(p); 1874 uasm_i_jr(p, tmp); 1875 uasm_i_rfe(p); /* branch delay */ 1876 } 1877 1878 /* 1879 * This places the pte into ENTRYLO0 and writes it with tlbwi 1880 * or tlbwr as appropriate. This is because the index register 1881 * may have the probe fail bit set as a result of a trap on a 1882 * kseg2 access, i.e. without refill. Then it returns. 1883 */ 1884 static void 1885 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, 1886 struct uasm_reloc **r, unsigned int pte, 1887 unsigned int tmp) 1888 { 1889 uasm_i_mfc0(p, tmp, C0_INDEX); 1890 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1891 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 1892 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ 1893 uasm_i_tlbwi(p); /* cp0 delay */ 1894 uasm_i_jr(p, tmp); 1895 uasm_i_rfe(p); /* branch delay */ 1896 uasm_l_r3000_write_probe_fail(l, *p); 1897 uasm_i_tlbwr(p); /* cp0 delay */ 1898 uasm_i_jr(p, tmp); 1899 uasm_i_rfe(p); /* branch delay */ 1900 } 1901 1902 static void 1903 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1904 unsigned int ptr) 1905 { 1906 long pgdc = (long)pgd_current; 1907 1908 uasm_i_mfc0(p, pte, C0_BADVADDR); 1909 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ 1910 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 1911 uasm_i_srl(p, pte, pte, 22); /* load delay */ 1912 uasm_i_sll(p, pte, pte, 2); 1913 uasm_i_addu(p, ptr, ptr, pte); 1914 uasm_i_mfc0(p, pte, C0_CONTEXT); 1915 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ 1916 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ 1917 uasm_i_addu(p, ptr, ptr, pte); 1918 uasm_i_lw(p, pte, 0, ptr); 1919 uasm_i_tlbp(p); /* load delay */ 1920 } 1921 1922 static void build_r3000_tlb_load_handler(void) 1923 { 1924 u32 *p = (u32 *)handle_tlbl; 1925 struct uasm_label *l = labels; 1926 struct uasm_reloc *r = relocs; 1927 1928 memset(p, 0, handle_tlbl_end - (char *)p); 1929 memset(labels, 0, sizeof(labels)); 1930 memset(relocs, 0, sizeof(relocs)); 1931 1932 build_r3000_tlbchange_handler_head(&p, K0, K1); 1933 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); 1934 uasm_i_nop(&p); /* load delay */ 1935 build_make_valid(&p, &r, K0, K1, -1); 1936 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1937 1938 uasm_l_nopage_tlbl(&l, p); 1939 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1940 uasm_i_nop(&p); 1941 1942 if (p >= (u32 *)handle_tlbl_end) 1943 panic("TLB load handler fastpath space exceeded"); 1944 1945 uasm_resolve_relocs(relocs, labels); 1946 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1947 (unsigned int)(p - (u32 *)handle_tlbl)); 1948 1949 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_end); 1950 } 1951 1952 static void build_r3000_tlb_store_handler(void) 1953 { 1954 u32 *p = (u32 *)handle_tlbs; 1955 struct uasm_label *l = labels; 1956 struct uasm_reloc *r = relocs; 1957 1958 memset(p, 0, handle_tlbs_end - (char *)p); 1959 memset(labels, 0, sizeof(labels)); 1960 memset(relocs, 0, sizeof(relocs)); 1961 1962 build_r3000_tlbchange_handler_head(&p, K0, K1); 1963 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); 1964 uasm_i_nop(&p); /* load delay */ 1965 build_make_write(&p, &r, K0, K1, -1); 1966 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1967 1968 uasm_l_nopage_tlbs(&l, p); 1969 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1970 uasm_i_nop(&p); 1971 1972 if (p >= (u32 *)handle_tlbs_end) 1973 panic("TLB store handler fastpath space exceeded"); 1974 1975 uasm_resolve_relocs(relocs, labels); 1976 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1977 (unsigned int)(p - (u32 *)handle_tlbs)); 1978 1979 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_end); 1980 } 1981 1982 static void build_r3000_tlb_modify_handler(void) 1983 { 1984 u32 *p = (u32 *)handle_tlbm; 1985 struct uasm_label *l = labels; 1986 struct uasm_reloc *r = relocs; 1987 1988 memset(p, 0, handle_tlbm_end - (char *)p); 1989 memset(labels, 0, sizeof(labels)); 1990 memset(relocs, 0, sizeof(relocs)); 1991 1992 build_r3000_tlbchange_handler_head(&p, K0, K1); 1993 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); 1994 uasm_i_nop(&p); /* load delay */ 1995 build_make_write(&p, &r, K0, K1, -1); 1996 build_r3000_pte_reload_tlbwi(&p, K0, K1); 1997 1998 uasm_l_nopage_tlbm(&l, p); 1999 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2000 uasm_i_nop(&p); 2001 2002 if (p >= (u32 *)handle_tlbm_end) 2003 panic("TLB modify handler fastpath space exceeded"); 2004 2005 uasm_resolve_relocs(relocs, labels); 2006 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2007 (unsigned int)(p - (u32 *)handle_tlbm)); 2008 2009 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_end); 2010 } 2011 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 2012 2013 static bool cpu_has_tlbex_tlbp_race(void) 2014 { 2015 /* 2016 * When a Hardware Table Walker is running it can replace TLB entries 2017 * at any time, leading to a race between it & the CPU. 2018 */ 2019 if (cpu_has_htw) 2020 return true; 2021 2022 /* 2023 * If the CPU shares FTLB RAM with its siblings then our entry may be 2024 * replaced at any time by a sibling performing a write to the FTLB. 2025 */ 2026 if (cpu_has_shared_ftlb_ram) 2027 return true; 2028 2029 /* In all other cases there ought to be no race condition to handle */ 2030 return false; 2031 } 2032 2033 /* 2034 * R4000 style TLB load/store/modify handlers. 2035 */ 2036 static struct work_registers 2037 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, 2038 struct uasm_reloc **r) 2039 { 2040 struct work_registers wr = build_get_work_registers(p); 2041 2042 #ifdef CONFIG_64BIT 2043 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ 2044 #else 2045 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ 2046 #endif 2047 2048 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2049 /* 2050 * For huge tlb entries, pmd doesn't contain an address but 2051 * instead contains the tlb pte. Check the PAGE_HUGE bit and 2052 * see if we need to jump to huge tlb processing. 2053 */ 2054 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); 2055 #endif 2056 2057 UASM_i_MFC0(p, wr.r1, C0_BADVADDR); 2058 UASM_i_LW(p, wr.r2, 0, wr.r2); 2059 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 2060 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 2061 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); 2062 2063 #ifdef CONFIG_SMP 2064 uasm_l_smp_pgtable_change(l, *p); 2065 #endif 2066 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ 2067 if (!m4kc_tlbp_war()) { 2068 build_tlb_probe_entry(p); 2069 if (cpu_has_tlbex_tlbp_race()) { 2070 /* race condition happens, leaving */ 2071 uasm_i_ehb(p); 2072 uasm_i_mfc0(p, wr.r3, C0_INDEX); 2073 uasm_il_bltz(p, r, wr.r3, label_leave); 2074 uasm_i_nop(p); 2075 } 2076 } 2077 return wr; 2078 } 2079 2080 static void 2081 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, 2082 struct uasm_reloc **r, unsigned int tmp, 2083 unsigned int ptr) 2084 { 2085 uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); 2086 uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); 2087 build_update_entries(p, tmp, ptr); 2088 build_tlb_write_entry(p, l, r, tlb_indexed); 2089 uasm_l_leave(l, *p); 2090 build_restore_work_registers(p); 2091 uasm_i_eret(p); /* return from trap */ 2092 2093 #ifdef CONFIG_64BIT 2094 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); 2095 #endif 2096 } 2097 2098 static void build_r4000_tlb_load_handler(void) 2099 { 2100 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl); 2101 struct uasm_label *l = labels; 2102 struct uasm_reloc *r = relocs; 2103 struct work_registers wr; 2104 2105 memset(p, 0, handle_tlbl_end - (char *)p); 2106 memset(labels, 0, sizeof(labels)); 2107 memset(relocs, 0, sizeof(relocs)); 2108 2109 if (bcm1250_m3_war()) { 2110 unsigned int segbits = 44; 2111 2112 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 2113 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 2114 uasm_i_xor(&p, K0, K0, K1); 2115 uasm_i_dsrl_safe(&p, K1, K0, 62); 2116 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 2117 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 2118 uasm_i_or(&p, K0, K0, K1); 2119 uasm_il_bnez(&p, &r, K0, label_leave); 2120 /* No need for uasm_i_nop */ 2121 } 2122 2123 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2124 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2125 if (m4kc_tlbp_war()) 2126 build_tlb_probe_entry(&p); 2127 2128 if (cpu_has_rixi && !cpu_has_rixiex) { 2129 /* 2130 * If the page is not _PAGE_VALID, RI or XI could not 2131 * have triggered it. Skip the expensive test.. 2132 */ 2133 if (use_bbit_insns()) { 2134 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2135 label_tlbl_goaround1); 2136 } else { 2137 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2138 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); 2139 } 2140 uasm_i_nop(&p); 2141 2142 /* 2143 * Warn if something may race with us & replace the TLB entry 2144 * before we read it here. Everything with such races should 2145 * also have dedicated RiXi exception handlers, so this 2146 * shouldn't be hit. 2147 */ 2148 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path"); 2149 2150 uasm_i_tlbr(&p); 2151 2152 switch (current_cpu_type()) { 2153 default: 2154 if (cpu_has_mips_r2_exec_hazard) { 2155 uasm_i_ehb(&p); 2156 2157 case CPU_CAVIUM_OCTEON: 2158 case CPU_CAVIUM_OCTEON_PLUS: 2159 case CPU_CAVIUM_OCTEON2: 2160 break; 2161 } 2162 } 2163 2164 /* Examine entrylo 0 or 1 based on ptr. */ 2165 if (use_bbit_insns()) { 2166 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2167 } else { 2168 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2169 uasm_i_beqz(&p, wr.r3, 8); 2170 } 2171 /* load it in the delay slot*/ 2172 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2173 /* load it if ptr is odd */ 2174 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2175 /* 2176 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2177 * XI must have triggered it. 2178 */ 2179 if (use_bbit_insns()) { 2180 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); 2181 uasm_i_nop(&p); 2182 uasm_l_tlbl_goaround1(&l, p); 2183 } else { 2184 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2185 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); 2186 uasm_i_nop(&p); 2187 } 2188 uasm_l_tlbl_goaround1(&l, p); 2189 } 2190 build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3); 2191 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2192 2193 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2194 /* 2195 * This is the entry point when build_r4000_tlbchange_handler_head 2196 * spots a huge page. 2197 */ 2198 uasm_l_tlb_huge_update(&l, p); 2199 iPTE_LW(&p, wr.r1, wr.r2); 2200 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2201 build_tlb_probe_entry(&p); 2202 2203 if (cpu_has_rixi && !cpu_has_rixiex) { 2204 /* 2205 * If the page is not _PAGE_VALID, RI or XI could not 2206 * have triggered it. Skip the expensive test.. 2207 */ 2208 if (use_bbit_insns()) { 2209 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2210 label_tlbl_goaround2); 2211 } else { 2212 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2213 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2214 } 2215 uasm_i_nop(&p); 2216 2217 /* 2218 * Warn if something may race with us & replace the TLB entry 2219 * before we read it here. Everything with such races should 2220 * also have dedicated RiXi exception handlers, so this 2221 * shouldn't be hit. 2222 */ 2223 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path"); 2224 2225 uasm_i_tlbr(&p); 2226 2227 switch (current_cpu_type()) { 2228 default: 2229 if (cpu_has_mips_r2_exec_hazard) { 2230 uasm_i_ehb(&p); 2231 2232 case CPU_CAVIUM_OCTEON: 2233 case CPU_CAVIUM_OCTEON_PLUS: 2234 case CPU_CAVIUM_OCTEON2: 2235 break; 2236 } 2237 } 2238 2239 /* Examine entrylo 0 or 1 based on ptr. */ 2240 if (use_bbit_insns()) { 2241 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2242 } else { 2243 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2244 uasm_i_beqz(&p, wr.r3, 8); 2245 } 2246 /* load it in the delay slot*/ 2247 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2248 /* load it if ptr is odd */ 2249 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2250 /* 2251 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2252 * XI must have triggered it. 2253 */ 2254 if (use_bbit_insns()) { 2255 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); 2256 } else { 2257 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2258 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2259 } 2260 if (PM_DEFAULT_MASK == 0) 2261 uasm_i_nop(&p); 2262 /* 2263 * We clobbered C0_PAGEMASK, restore it. On the other branch 2264 * it is restored in build_huge_tlb_write_entry. 2265 */ 2266 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); 2267 2268 uasm_l_tlbl_goaround2(&l, p); 2269 } 2270 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); 2271 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); 2272 #endif 2273 2274 uasm_l_nopage_tlbl(&l, p); 2275 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2276 uasm_i_sync(&p, 0); 2277 build_restore_work_registers(&p); 2278 #ifdef CONFIG_CPU_MICROMIPS 2279 if ((unsigned long)tlb_do_page_fault_0 & 1) { 2280 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); 2281 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); 2282 uasm_i_jr(&p, K0); 2283 } else 2284 #endif 2285 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 2286 uasm_i_nop(&p); 2287 2288 if (p >= (u32 *)handle_tlbl_end) 2289 panic("TLB load handler fastpath space exceeded"); 2290 2291 uasm_resolve_relocs(relocs, labels); 2292 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 2293 (unsigned int)(p - (u32 *)handle_tlbl)); 2294 2295 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_end); 2296 } 2297 2298 static void build_r4000_tlb_store_handler(void) 2299 { 2300 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs); 2301 struct uasm_label *l = labels; 2302 struct uasm_reloc *r = relocs; 2303 struct work_registers wr; 2304 2305 memset(p, 0, handle_tlbs_end - (char *)p); 2306 memset(labels, 0, sizeof(labels)); 2307 memset(relocs, 0, sizeof(relocs)); 2308 2309 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2310 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2311 if (m4kc_tlbp_war()) 2312 build_tlb_probe_entry(&p); 2313 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); 2314 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2315 2316 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2317 /* 2318 * This is the entry point when 2319 * build_r4000_tlbchange_handler_head spots a huge page. 2320 */ 2321 uasm_l_tlb_huge_update(&l, p); 2322 iPTE_LW(&p, wr.r1, wr.r2); 2323 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2324 build_tlb_probe_entry(&p); 2325 uasm_i_ori(&p, wr.r1, wr.r1, 2326 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2327 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); 2328 #endif 2329 2330 uasm_l_nopage_tlbs(&l, p); 2331 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2332 uasm_i_sync(&p, 0); 2333 build_restore_work_registers(&p); 2334 #ifdef CONFIG_CPU_MICROMIPS 2335 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2336 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2337 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2338 uasm_i_jr(&p, K0); 2339 } else 2340 #endif 2341 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2342 uasm_i_nop(&p); 2343 2344 if (p >= (u32 *)handle_tlbs_end) 2345 panic("TLB store handler fastpath space exceeded"); 2346 2347 uasm_resolve_relocs(relocs, labels); 2348 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 2349 (unsigned int)(p - (u32 *)handle_tlbs)); 2350 2351 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_end); 2352 } 2353 2354 static void build_r4000_tlb_modify_handler(void) 2355 { 2356 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm); 2357 struct uasm_label *l = labels; 2358 struct uasm_reloc *r = relocs; 2359 struct work_registers wr; 2360 2361 memset(p, 0, handle_tlbm_end - (char *)p); 2362 memset(labels, 0, sizeof(labels)); 2363 memset(relocs, 0, sizeof(relocs)); 2364 2365 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2366 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2367 if (m4kc_tlbp_war()) 2368 build_tlb_probe_entry(&p); 2369 /* Present and writable bits set, set accessed and dirty bits. */ 2370 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); 2371 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2372 2373 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2374 /* 2375 * This is the entry point when 2376 * build_r4000_tlbchange_handler_head spots a huge page. 2377 */ 2378 uasm_l_tlb_huge_update(&l, p); 2379 iPTE_LW(&p, wr.r1, wr.r2); 2380 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2381 build_tlb_probe_entry(&p); 2382 uasm_i_ori(&p, wr.r1, wr.r1, 2383 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2384 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0); 2385 #endif 2386 2387 uasm_l_nopage_tlbm(&l, p); 2388 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2389 uasm_i_sync(&p, 0); 2390 build_restore_work_registers(&p); 2391 #ifdef CONFIG_CPU_MICROMIPS 2392 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2393 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2394 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2395 uasm_i_jr(&p, K0); 2396 } else 2397 #endif 2398 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2399 uasm_i_nop(&p); 2400 2401 if (p >= (u32 *)handle_tlbm_end) 2402 panic("TLB modify handler fastpath space exceeded"); 2403 2404 uasm_resolve_relocs(relocs, labels); 2405 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2406 (unsigned int)(p - (u32 *)handle_tlbm)); 2407 2408 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_end); 2409 } 2410 2411 static void flush_tlb_handlers(void) 2412 { 2413 local_flush_icache_range((unsigned long)handle_tlbl, 2414 (unsigned long)handle_tlbl_end); 2415 local_flush_icache_range((unsigned long)handle_tlbs, 2416 (unsigned long)handle_tlbs_end); 2417 local_flush_icache_range((unsigned long)handle_tlbm, 2418 (unsigned long)handle_tlbm_end); 2419 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, 2420 (unsigned long)tlbmiss_handler_setup_pgd_end); 2421 } 2422 2423 static void print_htw_config(void) 2424 { 2425 unsigned long config; 2426 unsigned int pwctl; 2427 const int field = 2 * sizeof(unsigned long); 2428 2429 config = read_c0_pwfield(); 2430 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n", 2431 field, config, 2432 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT, 2433 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT, 2434 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT, 2435 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT, 2436 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); 2437 2438 config = read_c0_pwsize(); 2439 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", 2440 field, config, 2441 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT, 2442 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, 2443 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, 2444 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, 2445 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT, 2446 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); 2447 2448 pwctl = read_c0_pwctl(); 2449 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", 2450 pwctl, 2451 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, 2452 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT, 2453 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT, 2454 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT, 2455 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, 2456 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, 2457 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); 2458 } 2459 2460 static void config_htw_params(void) 2461 { 2462 unsigned long pwfield, pwsize, ptei; 2463 unsigned int config; 2464 2465 /* 2466 * We are using 2-level page tables, so we only need to 2467 * setup GDW and PTW appropriately. UDW and MDW will remain 0. 2468 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to 2469 * write values less than 0xc in these fields because the entire 2470 * write will be dropped. As a result of which, we must preserve 2471 * the original reset values and overwrite only what we really want. 2472 */ 2473 2474 pwfield = read_c0_pwfield(); 2475 /* re-initialize the GDI field */ 2476 pwfield &= ~MIPS_PWFIELD_GDI_MASK; 2477 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT; 2478 /* re-initialize the PTI field including the even/odd bit */ 2479 pwfield &= ~MIPS_PWFIELD_PTI_MASK; 2480 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT; 2481 if (CONFIG_PGTABLE_LEVELS >= 3) { 2482 pwfield &= ~MIPS_PWFIELD_MDI_MASK; 2483 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT; 2484 } 2485 /* Set the PTEI right shift */ 2486 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT; 2487 pwfield |= ptei; 2488 write_c0_pwfield(pwfield); 2489 /* Check whether the PTEI value is supported */ 2490 back_to_back_c0_hazard(); 2491 pwfield = read_c0_pwfield(); 2492 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT) 2493 != ptei) { 2494 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled", 2495 ptei); 2496 /* 2497 * Drop option to avoid HTW being enabled via another path 2498 * (eg htw_reset()) 2499 */ 2500 current_cpu_data.options &= ~MIPS_CPU_HTW; 2501 return; 2502 } 2503 2504 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; 2505 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; 2506 if (CONFIG_PGTABLE_LEVELS >= 3) 2507 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; 2508 2509 /* Set pointer size to size of directory pointers */ 2510 if (IS_ENABLED(CONFIG_64BIT)) 2511 pwsize |= MIPS_PWSIZE_PS_MASK; 2512 /* PTEs may be multiple pointers long (e.g. with XPA) */ 2513 pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT) 2514 & MIPS_PWSIZE_PTEW_MASK; 2515 2516 write_c0_pwsize(pwsize); 2517 2518 /* Make sure everything is set before we enable the HTW */ 2519 back_to_back_c0_hazard(); 2520 2521 /* 2522 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of 2523 * the pwctl fields. 2524 */ 2525 config = 1 << MIPS_PWCTL_PWEN_SHIFT; 2526 if (IS_ENABLED(CONFIG_64BIT)) 2527 config |= MIPS_PWCTL_XU_MASK; 2528 write_c0_pwctl(config); 2529 pr_info("Hardware Page Table Walker enabled\n"); 2530 2531 print_htw_config(); 2532 } 2533 2534 static void config_xpa_params(void) 2535 { 2536 #ifdef CONFIG_XPA 2537 unsigned int pagegrain; 2538 2539 if (mips_xpa_disabled) { 2540 pr_info("Extended Physical Addressing (XPA) disabled\n"); 2541 return; 2542 } 2543 2544 pagegrain = read_c0_pagegrain(); 2545 write_c0_pagegrain(pagegrain | PG_ELPA); 2546 back_to_back_c0_hazard(); 2547 pagegrain = read_c0_pagegrain(); 2548 2549 if (pagegrain & PG_ELPA) 2550 pr_info("Extended Physical Addressing (XPA) enabled\n"); 2551 else 2552 panic("Extended Physical Addressing (XPA) disabled"); 2553 #endif 2554 } 2555 2556 static void check_pabits(void) 2557 { 2558 unsigned long entry; 2559 unsigned pabits, fillbits; 2560 2561 if (!cpu_has_rixi || !_PAGE_NO_EXEC) { 2562 /* 2563 * We'll only be making use of the fact that we can rotate bits 2564 * into the fill if the CPU supports RIXI, so don't bother 2565 * probing this for CPUs which don't. 2566 */ 2567 return; 2568 } 2569 2570 write_c0_entrylo0(~0ul); 2571 back_to_back_c0_hazard(); 2572 entry = read_c0_entrylo0(); 2573 2574 /* clear all non-PFN bits */ 2575 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1); 2576 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); 2577 2578 /* find a lower bound on PABITS, and upper bound on fill bits */ 2579 pabits = fls_long(entry) + 6; 2580 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0); 2581 2582 /* minus the RI & XI bits */ 2583 fillbits -= min_t(unsigned, fillbits, 2); 2584 2585 if (fillbits >= ilog2(_PAGE_NO_EXEC)) 2586 fill_includes_sw_bits = true; 2587 2588 pr_debug("Entry* registers contain %u fill bits\n", fillbits); 2589 } 2590 2591 void build_tlb_refill_handler(void) 2592 { 2593 /* 2594 * The refill handler is generated per-CPU, multi-node systems 2595 * may have local storage for it. The other handlers are only 2596 * needed once. 2597 */ 2598 static int run_once = 0; 2599 2600 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi) 2601 panic("Kernels supporting XPA currently require CPUs with RIXI"); 2602 2603 output_pgtable_bits_defines(); 2604 check_pabits(); 2605 2606 #ifdef CONFIG_64BIT 2607 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 2608 #endif 2609 2610 if (cpu_has_3kex) { 2611 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 2612 if (!run_once) { 2613 build_setup_pgd(); 2614 build_r3000_tlb_refill_handler(); 2615 build_r3000_tlb_load_handler(); 2616 build_r3000_tlb_store_handler(); 2617 build_r3000_tlb_modify_handler(); 2618 flush_tlb_handlers(); 2619 run_once++; 2620 } 2621 #else 2622 panic("No R3000 TLB refill handler"); 2623 #endif 2624 return; 2625 } 2626 2627 if (cpu_has_ldpte) 2628 setup_pw(); 2629 2630 if (!run_once) { 2631 scratch_reg = allocate_kscratch(); 2632 build_setup_pgd(); 2633 build_r4000_tlb_load_handler(); 2634 build_r4000_tlb_store_handler(); 2635 build_r4000_tlb_modify_handler(); 2636 if (cpu_has_ldpte) 2637 build_loongson3_tlb_refill_handler(); 2638 else 2639 build_r4000_tlb_refill_handler(); 2640 flush_tlb_handlers(); 2641 run_once++; 2642 } 2643 if (cpu_has_xpa) 2644 config_xpa_params(); 2645 if (cpu_has_htw) 2646 config_htw_params(); 2647 } 2648