1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 9 * Copyright (C) 2005, 2007 Maciej W. Rozycki 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 * 12 * ... and the days got worse and worse and now you see 13 * I've gone completly out of my mind. 14 * 15 * They're coming to take me a away haha 16 * they're coming to take me a away hoho hihi haha 17 * to the funny farm where code is beautiful all the time ... 18 * 19 * (Condolences to Napoleon XIV) 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/types.h> 24 #include <linux/string.h> 25 #include <linux/init.h> 26 27 #include <asm/mmu_context.h> 28 #include <asm/war.h> 29 30 #include "uasm.h" 31 32 static inline int r45k_bvahwbug(void) 33 { 34 /* XXX: We should probe for the presence of this bug, but we don't. */ 35 return 0; 36 } 37 38 static inline int r4k_250MHZhwbug(void) 39 { 40 /* XXX: We should probe for the presence of this bug, but we don't. */ 41 return 0; 42 } 43 44 static inline int __maybe_unused bcm1250_m3_war(void) 45 { 46 return BCM1250_M3_WAR; 47 } 48 49 static inline int __maybe_unused r10000_llsc_war(void) 50 { 51 return R10000_LLSC_WAR; 52 } 53 54 /* 55 * Found by experiment: At least some revisions of the 4kc throw under 56 * some circumstances a machine check exception, triggered by invalid 57 * values in the index register. Delaying the tlbp instruction until 58 * after the next branch, plus adding an additional nop in front of 59 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows 60 * why; it's not an issue caused by the core RTL. 61 * 62 */ 63 static int __cpuinit m4kc_tlbp_war(void) 64 { 65 return (current_cpu_data.processor_id & 0xffff00) == 66 (PRID_COMP_MIPS | PRID_IMP_4KC); 67 } 68 69 /* Handle labels (which must be positive integers). */ 70 enum label_id { 71 label_second_part = 1, 72 label_leave, 73 #ifdef MODULE_START 74 label_module_alloc, 75 #endif 76 label_vmalloc, 77 label_vmalloc_done, 78 label_tlbw_hazard, 79 label_split, 80 label_nopage_tlbl, 81 label_nopage_tlbs, 82 label_nopage_tlbm, 83 label_smp_pgtable_change, 84 label_r3000_write_probe_fail, 85 }; 86 87 UASM_L_LA(_second_part) 88 UASM_L_LA(_leave) 89 #ifdef MODULE_START 90 UASM_L_LA(_module_alloc) 91 #endif 92 UASM_L_LA(_vmalloc) 93 UASM_L_LA(_vmalloc_done) 94 UASM_L_LA(_tlbw_hazard) 95 UASM_L_LA(_split) 96 UASM_L_LA(_nopage_tlbl) 97 UASM_L_LA(_nopage_tlbs) 98 UASM_L_LA(_nopage_tlbm) 99 UASM_L_LA(_smp_pgtable_change) 100 UASM_L_LA(_r3000_write_probe_fail) 101 102 /* 103 * For debug purposes. 104 */ 105 static inline void dump_handler(const u32 *handler, int count) 106 { 107 int i; 108 109 pr_debug("\t.set push\n"); 110 pr_debug("\t.set noreorder\n"); 111 112 for (i = 0; i < count; i++) 113 pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]); 114 115 pr_debug("\t.set pop\n"); 116 } 117 118 /* The only general purpose registers allowed in TLB handlers. */ 119 #define K0 26 120 #define K1 27 121 122 /* Some CP0 registers */ 123 #define C0_INDEX 0, 0 124 #define C0_ENTRYLO0 2, 0 125 #define C0_TCBIND 2, 2 126 #define C0_ENTRYLO1 3, 0 127 #define C0_CONTEXT 4, 0 128 #define C0_BADVADDR 8, 0 129 #define C0_ENTRYHI 10, 0 130 #define C0_EPC 14, 0 131 #define C0_XCONTEXT 20, 0 132 133 #ifdef CONFIG_64BIT 134 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) 135 #else 136 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) 137 #endif 138 139 /* The worst case length of the handler is around 18 instructions for 140 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 141 * Maximum space available is 32 instructions for R3000 and 64 142 * instructions for R4000. 143 * 144 * We deliberately chose a buffer size of 128, so we won't scribble 145 * over anything important on overflow before we panic. 146 */ 147 static u32 tlb_handler[128] __cpuinitdata; 148 149 /* simply assume worst case size for labels and relocs */ 150 static struct uasm_label labels[128] __cpuinitdata; 151 static struct uasm_reloc relocs[128] __cpuinitdata; 152 153 /* 154 * The R3000 TLB handler is simple. 155 */ 156 static void __cpuinit build_r3000_tlb_refill_handler(void) 157 { 158 long pgdc = (long)pgd_current; 159 u32 *p; 160 161 memset(tlb_handler, 0, sizeof(tlb_handler)); 162 p = tlb_handler; 163 164 uasm_i_mfc0(&p, K0, C0_BADVADDR); 165 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ 166 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); 167 uasm_i_srl(&p, K0, K0, 22); /* load delay */ 168 uasm_i_sll(&p, K0, K0, 2); 169 uasm_i_addu(&p, K1, K1, K0); 170 uasm_i_mfc0(&p, K0, C0_CONTEXT); 171 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ 172 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ 173 uasm_i_addu(&p, K1, K1, K0); 174 uasm_i_lw(&p, K0, 0, K1); 175 uasm_i_nop(&p); /* load delay */ 176 uasm_i_mtc0(&p, K0, C0_ENTRYLO0); 177 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 178 uasm_i_tlbwr(&p); /* cp0 delay */ 179 uasm_i_jr(&p, K1); 180 uasm_i_rfe(&p); /* branch delay */ 181 182 if (p > tlb_handler + 32) 183 panic("TLB refill handler space exceeded"); 184 185 pr_debug("Wrote TLB refill handler (%u instructions).\n", 186 (unsigned int)(p - tlb_handler)); 187 188 memcpy((void *)ebase, tlb_handler, 0x80); 189 190 dump_handler((u32 *)ebase, 32); 191 } 192 193 /* 194 * The R4000 TLB handler is much more complicated. We have two 195 * consecutive handler areas with 32 instructions space each. 196 * Since they aren't used at the same time, we can overflow in the 197 * other one.To keep things simple, we first assume linear space, 198 * then we relocate it to the final handler layout as needed. 199 */ 200 static u32 final_handler[64] __cpuinitdata; 201 202 /* 203 * Hazards 204 * 205 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 206 * 2. A timing hazard exists for the TLBP instruction. 207 * 208 * stalling_instruction 209 * TLBP 210 * 211 * The JTLB is being read for the TLBP throughout the stall generated by the 212 * previous instruction. This is not really correct as the stalling instruction 213 * can modify the address used to access the JTLB. The failure symptom is that 214 * the TLBP instruction will use an address created for the stalling instruction 215 * and not the address held in C0_ENHI and thus report the wrong results. 216 * 217 * The software work-around is to not allow the instruction preceding the TLBP 218 * to stall - make it an NOP or some other instruction guaranteed not to stall. 219 * 220 * Errata 2 will not be fixed. This errata is also on the R5000. 221 * 222 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 223 */ 224 static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p) 225 { 226 switch (current_cpu_type()) { 227 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ 228 case CPU_R4600: 229 case CPU_R4700: 230 case CPU_R5000: 231 case CPU_R5000A: 232 case CPU_NEVADA: 233 uasm_i_nop(p); 234 uasm_i_tlbp(p); 235 break; 236 237 default: 238 uasm_i_tlbp(p); 239 break; 240 } 241 } 242 243 /* 244 * Write random or indexed TLB entry, and care about the hazards from 245 * the preceeding mtc0 and for the following eret. 246 */ 247 enum tlb_write_entry { tlb_random, tlb_indexed }; 248 249 static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, 250 struct uasm_reloc **r, 251 enum tlb_write_entry wmode) 252 { 253 void(*tlbw)(u32 **) = NULL; 254 255 switch (wmode) { 256 case tlb_random: tlbw = uasm_i_tlbwr; break; 257 case tlb_indexed: tlbw = uasm_i_tlbwi; break; 258 } 259 260 if (cpu_has_mips_r2) { 261 uasm_i_ehb(p); 262 tlbw(p); 263 return; 264 } 265 266 switch (current_cpu_type()) { 267 case CPU_R4000PC: 268 case CPU_R4000SC: 269 case CPU_R4000MC: 270 case CPU_R4400PC: 271 case CPU_R4400SC: 272 case CPU_R4400MC: 273 /* 274 * This branch uses up a mtc0 hazard nop slot and saves 275 * two nops after the tlbw instruction. 276 */ 277 uasm_il_bgezl(p, r, 0, label_tlbw_hazard); 278 tlbw(p); 279 uasm_l_tlbw_hazard(l, *p); 280 uasm_i_nop(p); 281 break; 282 283 case CPU_R4600: 284 case CPU_R4700: 285 case CPU_R5000: 286 case CPU_R5000A: 287 uasm_i_nop(p); 288 tlbw(p); 289 uasm_i_nop(p); 290 break; 291 292 case CPU_R4300: 293 case CPU_5KC: 294 case CPU_TX49XX: 295 case CPU_PR4450: 296 uasm_i_nop(p); 297 tlbw(p); 298 break; 299 300 case CPU_R10000: 301 case CPU_R12000: 302 case CPU_R14000: 303 case CPU_4KC: 304 case CPU_4KEC: 305 case CPU_SB1: 306 case CPU_SB1A: 307 case CPU_4KSC: 308 case CPU_20KC: 309 case CPU_25KF: 310 case CPU_BCM3302: 311 case CPU_BCM4710: 312 case CPU_LOONGSON2: 313 case CPU_CAVIUM_OCTEON: 314 case CPU_R5500: 315 if (m4kc_tlbp_war()) 316 uasm_i_nop(p); 317 case CPU_ALCHEMY: 318 tlbw(p); 319 break; 320 321 case CPU_NEVADA: 322 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 323 /* 324 * This branch uses up a mtc0 hazard nop slot and saves 325 * a nop after the tlbw instruction. 326 */ 327 uasm_il_bgezl(p, r, 0, label_tlbw_hazard); 328 tlbw(p); 329 uasm_l_tlbw_hazard(l, *p); 330 break; 331 332 case CPU_RM7000: 333 uasm_i_nop(p); 334 uasm_i_nop(p); 335 uasm_i_nop(p); 336 uasm_i_nop(p); 337 tlbw(p); 338 break; 339 340 case CPU_RM9000: 341 /* 342 * When the JTLB is updated by tlbwi or tlbwr, a subsequent 343 * use of the JTLB for instructions should not occur for 4 344 * cpu cycles and use for data translations should not occur 345 * for 3 cpu cycles. 346 */ 347 uasm_i_ssnop(p); 348 uasm_i_ssnop(p); 349 uasm_i_ssnop(p); 350 uasm_i_ssnop(p); 351 tlbw(p); 352 uasm_i_ssnop(p); 353 uasm_i_ssnop(p); 354 uasm_i_ssnop(p); 355 uasm_i_ssnop(p); 356 break; 357 358 case CPU_VR4111: 359 case CPU_VR4121: 360 case CPU_VR4122: 361 case CPU_VR4181: 362 case CPU_VR4181A: 363 uasm_i_nop(p); 364 uasm_i_nop(p); 365 tlbw(p); 366 uasm_i_nop(p); 367 uasm_i_nop(p); 368 break; 369 370 case CPU_VR4131: 371 case CPU_VR4133: 372 case CPU_R5432: 373 uasm_i_nop(p); 374 uasm_i_nop(p); 375 tlbw(p); 376 break; 377 378 default: 379 panic("No TLB refill handler yet (CPU type: %d)", 380 current_cpu_data.cputype); 381 break; 382 } 383 } 384 385 #ifdef CONFIG_64BIT 386 /* 387 * TMP and PTR are scratch. 388 * TMP will be clobbered, PTR will hold the pmd entry. 389 */ 390 static void __cpuinit 391 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 392 unsigned int tmp, unsigned int ptr) 393 { 394 long pgdc = (long)pgd_current; 395 396 /* 397 * The vmalloc handling is not in the hotpath. 398 */ 399 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 400 #ifdef MODULE_START 401 uasm_il_bltz(p, r, tmp, label_module_alloc); 402 #else 403 uasm_il_bltz(p, r, tmp, label_vmalloc); 404 #endif 405 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 406 407 #ifdef CONFIG_SMP 408 # ifdef CONFIG_MIPS_MT_SMTC 409 /* 410 * SMTC uses TCBind value as "CPU" index 411 */ 412 uasm_i_mfc0(p, ptr, C0_TCBIND); 413 uasm_i_dsrl(p, ptr, ptr, 19); 414 # else 415 /* 416 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 417 * stored in CONTEXT. 418 */ 419 uasm_i_dmfc0(p, ptr, C0_CONTEXT); 420 uasm_i_dsrl(p, ptr, ptr, 23); 421 #endif 422 UASM_i_LA_mostly(p, tmp, pgdc); 423 uasm_i_daddu(p, ptr, ptr, tmp); 424 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 425 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 426 #else 427 UASM_i_LA_mostly(p, ptr, pgdc); 428 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 429 #endif 430 431 uasm_l_vmalloc_done(l, *p); 432 433 if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */ 434 uasm_i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); 435 else 436 uasm_i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32); 437 438 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 439 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 440 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 441 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 442 uasm_i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 443 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 444 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 445 } 446 447 /* 448 * BVADDR is the faulting address, PTR is scratch. 449 * PTR will hold the pgd for vmalloc. 450 */ 451 static void __cpuinit 452 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 453 unsigned int bvaddr, unsigned int ptr) 454 { 455 long swpd = (long)swapper_pg_dir; 456 457 #ifdef MODULE_START 458 long modd = (long)module_pg_dir; 459 460 uasm_l_module_alloc(l, *p); 461 /* 462 * Assumption: 463 * VMALLOC_START >= 0xc000000000000000UL 464 * MODULE_START >= 0xe000000000000000UL 465 */ 466 UASM_i_SLL(p, ptr, bvaddr, 2); 467 uasm_il_bgez(p, r, ptr, label_vmalloc); 468 469 if (uasm_in_compat_space_p(MODULE_START) && 470 !uasm_rel_lo(MODULE_START)) { 471 uasm_i_lui(p, ptr, uasm_rel_hi(MODULE_START)); /* delay slot */ 472 } else { 473 /* unlikely configuration */ 474 uasm_i_nop(p); /* delay slot */ 475 UASM_i_LA(p, ptr, MODULE_START); 476 } 477 uasm_i_dsubu(p, bvaddr, bvaddr, ptr); 478 479 if (uasm_in_compat_space_p(modd) && !uasm_rel_lo(modd)) { 480 uasm_il_b(p, r, label_vmalloc_done); 481 uasm_i_lui(p, ptr, uasm_rel_hi(modd)); 482 } else { 483 UASM_i_LA_mostly(p, ptr, modd); 484 uasm_il_b(p, r, label_vmalloc_done); 485 if (uasm_in_compat_space_p(modd)) 486 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(modd)); 487 else 488 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(modd)); 489 } 490 491 uasm_l_vmalloc(l, *p); 492 if (uasm_in_compat_space_p(MODULE_START) && 493 !uasm_rel_lo(MODULE_START) && 494 MODULE_START << 32 == VMALLOC_START) 495 uasm_i_dsll32(p, ptr, ptr, 0); /* typical case */ 496 else 497 UASM_i_LA(p, ptr, VMALLOC_START); 498 #else 499 uasm_l_vmalloc(l, *p); 500 UASM_i_LA(p, ptr, VMALLOC_START); 501 #endif 502 uasm_i_dsubu(p, bvaddr, bvaddr, ptr); 503 504 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { 505 uasm_il_b(p, r, label_vmalloc_done); 506 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 507 } else { 508 UASM_i_LA_mostly(p, ptr, swpd); 509 uasm_il_b(p, r, label_vmalloc_done); 510 if (uasm_in_compat_space_p(swpd)) 511 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); 512 else 513 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); 514 } 515 } 516 517 #else /* !CONFIG_64BIT */ 518 519 /* 520 * TMP and PTR are scratch. 521 * TMP will be clobbered, PTR will hold the pgd entry. 522 */ 523 static void __cpuinit __maybe_unused 524 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 525 { 526 long pgdc = (long)pgd_current; 527 528 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 529 #ifdef CONFIG_SMP 530 #ifdef CONFIG_MIPS_MT_SMTC 531 /* 532 * SMTC uses TCBind value as "CPU" index 533 */ 534 uasm_i_mfc0(p, ptr, C0_TCBIND); 535 UASM_i_LA_mostly(p, tmp, pgdc); 536 uasm_i_srl(p, ptr, ptr, 19); 537 #else 538 /* 539 * smp_processor_id() << 3 is stored in CONTEXT. 540 */ 541 uasm_i_mfc0(p, ptr, C0_CONTEXT); 542 UASM_i_LA_mostly(p, tmp, pgdc); 543 uasm_i_srl(p, ptr, ptr, 23); 544 #endif 545 uasm_i_addu(p, ptr, tmp, ptr); 546 #else 547 UASM_i_LA_mostly(p, ptr, pgdc); 548 #endif 549 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 550 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 551 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 552 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); 553 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 554 } 555 556 #endif /* !CONFIG_64BIT */ 557 558 static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) 559 { 560 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 561 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 562 563 switch (current_cpu_type()) { 564 case CPU_VR41XX: 565 case CPU_VR4111: 566 case CPU_VR4121: 567 case CPU_VR4122: 568 case CPU_VR4131: 569 case CPU_VR4181: 570 case CPU_VR4181A: 571 case CPU_VR4133: 572 shift += 2; 573 break; 574 575 default: 576 break; 577 } 578 579 if (shift) 580 UASM_i_SRL(p, ctx, ctx, shift); 581 uasm_i_andi(p, ctx, ctx, mask); 582 } 583 584 static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 585 { 586 /* 587 * Bug workaround for the Nevada. It seems as if under certain 588 * circumstances the move from cp0_context might produce a 589 * bogus result when the mfc0 instruction and its consumer are 590 * in a different cacheline or a load instruction, probably any 591 * memory reference, is between them. 592 */ 593 switch (current_cpu_type()) { 594 case CPU_NEVADA: 595 UASM_i_LW(p, ptr, 0, ptr); 596 GET_CONTEXT(p, tmp); /* get context reg */ 597 break; 598 599 default: 600 GET_CONTEXT(p, tmp); /* get context reg */ 601 UASM_i_LW(p, ptr, 0, ptr); 602 break; 603 } 604 605 build_adjust_context(p, tmp); 606 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 607 } 608 609 static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, 610 unsigned int ptep) 611 { 612 /* 613 * 64bit address support (36bit on a 32bit CPU) in a 32bit 614 * Kernel is a special case. Only a few CPUs use it. 615 */ 616 #ifdef CONFIG_64BIT_PHYS_ADDR 617 if (cpu_has_64bits) { 618 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ 619 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 620 uasm_i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ 621 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 622 uasm_i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ 623 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 624 } else { 625 int pte_off_even = sizeof(pte_t) / 2; 626 int pte_off_odd = pte_off_even + sizeof(pte_t); 627 628 /* The pte entries are pre-shifted */ 629 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ 630 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 631 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ 632 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 633 } 634 #else 635 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ 636 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 637 if (r45k_bvahwbug()) 638 build_tlb_probe_entry(p); 639 UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ 640 if (r4k_250MHZhwbug()) 641 uasm_i_mtc0(p, 0, C0_ENTRYLO0); 642 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 643 UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ 644 if (r45k_bvahwbug()) 645 uasm_i_mfc0(p, tmp, C0_INDEX); 646 if (r4k_250MHZhwbug()) 647 uasm_i_mtc0(p, 0, C0_ENTRYLO1); 648 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 649 #endif 650 } 651 652 static void __cpuinit build_r4000_tlb_refill_handler(void) 653 { 654 u32 *p = tlb_handler; 655 struct uasm_label *l = labels; 656 struct uasm_reloc *r = relocs; 657 u32 *f; 658 unsigned int final_len; 659 660 memset(tlb_handler, 0, sizeof(tlb_handler)); 661 memset(labels, 0, sizeof(labels)); 662 memset(relocs, 0, sizeof(relocs)); 663 memset(final_handler, 0, sizeof(final_handler)); 664 665 /* 666 * create the plain linear handler 667 */ 668 if (bcm1250_m3_war()) { 669 UASM_i_MFC0(&p, K0, C0_BADVADDR); 670 UASM_i_MFC0(&p, K1, C0_ENTRYHI); 671 uasm_i_xor(&p, K0, K0, K1); 672 UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); 673 uasm_il_bnez(&p, &r, K0, label_leave); 674 /* No need for uasm_i_nop */ 675 } 676 677 #ifdef CONFIG_64BIT 678 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 679 #else 680 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 681 #endif 682 683 build_get_ptep(&p, K0, K1); 684 build_update_entries(&p, K0, K1); 685 build_tlb_write_entry(&p, &l, &r, tlb_random); 686 uasm_l_leave(&l, p); 687 uasm_i_eret(&p); /* return from trap */ 688 689 #ifdef CONFIG_64BIT 690 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); 691 #endif 692 693 /* 694 * Overflow check: For the 64bit handler, we need at least one 695 * free instruction slot for the wrap-around branch. In worst 696 * case, if the intended insertion point is a delay slot, we 697 * need three, with the second nop'ed and the third being 698 * unused. 699 */ 700 /* Loongson2 ebase is different than r4k, we have more space */ 701 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) 702 if ((p - tlb_handler) > 64) 703 panic("TLB refill handler space exceeded"); 704 #else 705 if (((p - tlb_handler) > 63) 706 || (((p - tlb_handler) > 61) 707 && uasm_insn_has_bdelay(relocs, tlb_handler + 29))) 708 panic("TLB refill handler space exceeded"); 709 #endif 710 711 /* 712 * Now fold the handler in the TLB refill handler space. 713 */ 714 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) 715 f = final_handler; 716 /* Simplest case, just copy the handler. */ 717 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 718 final_len = p - tlb_handler; 719 #else /* CONFIG_64BIT */ 720 f = final_handler + 32; 721 if ((p - tlb_handler) <= 32) { 722 /* Just copy the handler. */ 723 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 724 final_len = p - tlb_handler; 725 } else { 726 u32 *split = tlb_handler + 30; 727 728 /* 729 * Find the split point. 730 */ 731 if (uasm_insn_has_bdelay(relocs, split - 1)) 732 split--; 733 734 /* Copy first part of the handler. */ 735 uasm_copy_handler(relocs, labels, tlb_handler, split, f); 736 f += split - tlb_handler; 737 738 /* Insert branch. */ 739 uasm_l_split(&l, final_handler); 740 uasm_il_b(&f, &r, label_split); 741 if (uasm_insn_has_bdelay(relocs, split)) 742 uasm_i_nop(&f); 743 else { 744 uasm_copy_handler(relocs, labels, split, split + 1, f); 745 uasm_move_labels(labels, f, f + 1, -1); 746 f++; 747 split++; 748 } 749 750 /* Copy the rest of the handler. */ 751 uasm_copy_handler(relocs, labels, split, p, final_handler); 752 final_len = (f - (final_handler + 32)) + (p - split); 753 } 754 #endif /* CONFIG_64BIT */ 755 756 uasm_resolve_relocs(relocs, labels); 757 pr_debug("Wrote TLB refill handler (%u instructions).\n", 758 final_len); 759 760 memcpy((void *)ebase, final_handler, 0x100); 761 762 dump_handler((u32 *)ebase, 64); 763 } 764 765 /* 766 * TLB load/store/modify handlers. 767 * 768 * Only the fastpath gets synthesized at runtime, the slowpath for 769 * do_page_fault remains normal asm. 770 */ 771 extern void tlb_do_page_fault_0(void); 772 extern void tlb_do_page_fault_1(void); 773 774 /* 775 * 128 instructions for the fastpath handler is generous and should 776 * never be exceeded. 777 */ 778 #define FASTPATH_SIZE 128 779 780 u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; 781 u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; 782 u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; 783 784 static void __cpuinit 785 iPTE_LW(u32 **p, struct uasm_label **l, unsigned int pte, unsigned int ptr) 786 { 787 #ifdef CONFIG_SMP 788 # ifdef CONFIG_64BIT_PHYS_ADDR 789 if (cpu_has_64bits) 790 uasm_i_lld(p, pte, 0, ptr); 791 else 792 # endif 793 UASM_i_LL(p, pte, 0, ptr); 794 #else 795 # ifdef CONFIG_64BIT_PHYS_ADDR 796 if (cpu_has_64bits) 797 uasm_i_ld(p, pte, 0, ptr); 798 else 799 # endif 800 UASM_i_LW(p, pte, 0, ptr); 801 #endif 802 } 803 804 static void __cpuinit 805 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, 806 unsigned int mode) 807 { 808 #ifdef CONFIG_64BIT_PHYS_ADDR 809 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 810 #endif 811 812 uasm_i_ori(p, pte, pte, mode); 813 #ifdef CONFIG_SMP 814 # ifdef CONFIG_64BIT_PHYS_ADDR 815 if (cpu_has_64bits) 816 uasm_i_scd(p, pte, 0, ptr); 817 else 818 # endif 819 UASM_i_SC(p, pte, 0, ptr); 820 821 if (r10000_llsc_war()) 822 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); 823 else 824 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 825 826 # ifdef CONFIG_64BIT_PHYS_ADDR 827 if (!cpu_has_64bits) { 828 /* no uasm_i_nop needed */ 829 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); 830 uasm_i_ori(p, pte, pte, hwmode); 831 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); 832 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 833 /* no uasm_i_nop needed */ 834 uasm_i_lw(p, pte, 0, ptr); 835 } else 836 uasm_i_nop(p); 837 # else 838 uasm_i_nop(p); 839 # endif 840 #else 841 # ifdef CONFIG_64BIT_PHYS_ADDR 842 if (cpu_has_64bits) 843 uasm_i_sd(p, pte, 0, ptr); 844 else 845 # endif 846 UASM_i_SW(p, pte, 0, ptr); 847 848 # ifdef CONFIG_64BIT_PHYS_ADDR 849 if (!cpu_has_64bits) { 850 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); 851 uasm_i_ori(p, pte, pte, hwmode); 852 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); 853 uasm_i_lw(p, pte, 0, ptr); 854 } 855 # endif 856 #endif 857 } 858 859 /* 860 * Check if PTE is present, if not then jump to LABEL. PTR points to 861 * the page table where this PTE is located, PTE will be re-loaded 862 * with it's original value. 863 */ 864 static void __cpuinit 865 build_pte_present(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 866 unsigned int pte, unsigned int ptr, enum label_id lid) 867 { 868 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 869 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 870 uasm_il_bnez(p, r, pte, lid); 871 iPTE_LW(p, l, pte, ptr); 872 } 873 874 /* Make PTE valid, store result in PTR. */ 875 static void __cpuinit 876 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, 877 unsigned int ptr) 878 { 879 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 880 881 iPTE_SW(p, r, pte, ptr, mode); 882 } 883 884 /* 885 * Check if PTE can be written to, if not branch to LABEL. Regardless 886 * restore PTE with value from PTR when done. 887 */ 888 static void __cpuinit 889 build_pte_writable(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 890 unsigned int pte, unsigned int ptr, enum label_id lid) 891 { 892 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 893 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 894 uasm_il_bnez(p, r, pte, lid); 895 iPTE_LW(p, l, pte, ptr); 896 } 897 898 /* Make PTE writable, update software status bits as well, then store 899 * at PTR. 900 */ 901 static void __cpuinit 902 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, 903 unsigned int ptr) 904 { 905 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 906 | _PAGE_DIRTY); 907 908 iPTE_SW(p, r, pte, ptr, mode); 909 } 910 911 /* 912 * Check if PTE can be modified, if not branch to LABEL. Regardless 913 * restore PTE with value from PTR when done. 914 */ 915 static void __cpuinit 916 build_pte_modifiable(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 917 unsigned int pte, unsigned int ptr, enum label_id lid) 918 { 919 uasm_i_andi(p, pte, pte, _PAGE_WRITE); 920 uasm_il_beqz(p, r, pte, lid); 921 iPTE_LW(p, l, pte, ptr); 922 } 923 924 /* 925 * R3000 style TLB load/store/modify handlers. 926 */ 927 928 /* 929 * This places the pte into ENTRYLO0 and writes it with tlbwi. 930 * Then it returns. 931 */ 932 static void __cpuinit 933 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 934 { 935 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 936 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 937 uasm_i_tlbwi(p); 938 uasm_i_jr(p, tmp); 939 uasm_i_rfe(p); /* branch delay */ 940 } 941 942 /* 943 * This places the pte into ENTRYLO0 and writes it with tlbwi 944 * or tlbwr as appropriate. This is because the index register 945 * may have the probe fail bit set as a result of a trap on a 946 * kseg2 access, i.e. without refill. Then it returns. 947 */ 948 static void __cpuinit 949 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, 950 struct uasm_reloc **r, unsigned int pte, 951 unsigned int tmp) 952 { 953 uasm_i_mfc0(p, tmp, C0_INDEX); 954 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 955 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 956 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ 957 uasm_i_tlbwi(p); /* cp0 delay */ 958 uasm_i_jr(p, tmp); 959 uasm_i_rfe(p); /* branch delay */ 960 uasm_l_r3000_write_probe_fail(l, *p); 961 uasm_i_tlbwr(p); /* cp0 delay */ 962 uasm_i_jr(p, tmp); 963 uasm_i_rfe(p); /* branch delay */ 964 } 965 966 static void __cpuinit 967 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 968 unsigned int ptr) 969 { 970 long pgdc = (long)pgd_current; 971 972 uasm_i_mfc0(p, pte, C0_BADVADDR); 973 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ 974 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 975 uasm_i_srl(p, pte, pte, 22); /* load delay */ 976 uasm_i_sll(p, pte, pte, 2); 977 uasm_i_addu(p, ptr, ptr, pte); 978 uasm_i_mfc0(p, pte, C0_CONTEXT); 979 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ 980 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ 981 uasm_i_addu(p, ptr, ptr, pte); 982 uasm_i_lw(p, pte, 0, ptr); 983 uasm_i_tlbp(p); /* load delay */ 984 } 985 986 static void __cpuinit build_r3000_tlb_load_handler(void) 987 { 988 u32 *p = handle_tlbl; 989 struct uasm_label *l = labels; 990 struct uasm_reloc *r = relocs; 991 992 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 993 memset(labels, 0, sizeof(labels)); 994 memset(relocs, 0, sizeof(relocs)); 995 996 build_r3000_tlbchange_handler_head(&p, K0, K1); 997 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 998 uasm_i_nop(&p); /* load delay */ 999 build_make_valid(&p, &r, K0, K1); 1000 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1001 1002 uasm_l_nopage_tlbl(&l, p); 1003 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1004 uasm_i_nop(&p); 1005 1006 if ((p - handle_tlbl) > FASTPATH_SIZE) 1007 panic("TLB load handler fastpath space exceeded"); 1008 1009 uasm_resolve_relocs(relocs, labels); 1010 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1011 (unsigned int)(p - handle_tlbl)); 1012 1013 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); 1014 } 1015 1016 static void __cpuinit build_r3000_tlb_store_handler(void) 1017 { 1018 u32 *p = handle_tlbs; 1019 struct uasm_label *l = labels; 1020 struct uasm_reloc *r = relocs; 1021 1022 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1023 memset(labels, 0, sizeof(labels)); 1024 memset(relocs, 0, sizeof(relocs)); 1025 1026 build_r3000_tlbchange_handler_head(&p, K0, K1); 1027 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1028 uasm_i_nop(&p); /* load delay */ 1029 build_make_write(&p, &r, K0, K1); 1030 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1031 1032 uasm_l_nopage_tlbs(&l, p); 1033 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1034 uasm_i_nop(&p); 1035 1036 if ((p - handle_tlbs) > FASTPATH_SIZE) 1037 panic("TLB store handler fastpath space exceeded"); 1038 1039 uasm_resolve_relocs(relocs, labels); 1040 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1041 (unsigned int)(p - handle_tlbs)); 1042 1043 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); 1044 } 1045 1046 static void __cpuinit build_r3000_tlb_modify_handler(void) 1047 { 1048 u32 *p = handle_tlbm; 1049 struct uasm_label *l = labels; 1050 struct uasm_reloc *r = relocs; 1051 1052 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1053 memset(labels, 0, sizeof(labels)); 1054 memset(relocs, 0, sizeof(relocs)); 1055 1056 build_r3000_tlbchange_handler_head(&p, K0, K1); 1057 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1058 uasm_i_nop(&p); /* load delay */ 1059 build_make_write(&p, &r, K0, K1); 1060 build_r3000_pte_reload_tlbwi(&p, K0, K1); 1061 1062 uasm_l_nopage_tlbm(&l, p); 1063 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1064 uasm_i_nop(&p); 1065 1066 if ((p - handle_tlbm) > FASTPATH_SIZE) 1067 panic("TLB modify handler fastpath space exceeded"); 1068 1069 uasm_resolve_relocs(relocs, labels); 1070 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 1071 (unsigned int)(p - handle_tlbm)); 1072 1073 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); 1074 } 1075 1076 /* 1077 * R4000 style TLB load/store/modify handlers. 1078 */ 1079 static void __cpuinit 1080 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, 1081 struct uasm_reloc **r, unsigned int pte, 1082 unsigned int ptr) 1083 { 1084 #ifdef CONFIG_64BIT 1085 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ 1086 #else 1087 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ 1088 #endif 1089 1090 UASM_i_MFC0(p, pte, C0_BADVADDR); 1091 UASM_i_LW(p, ptr, 0, ptr); 1092 UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 1093 uasm_i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 1094 UASM_i_ADDU(p, ptr, ptr, pte); 1095 1096 #ifdef CONFIG_SMP 1097 uasm_l_smp_pgtable_change(l, *p); 1098 #endif 1099 iPTE_LW(p, l, pte, ptr); /* get even pte */ 1100 if (!m4kc_tlbp_war()) 1101 build_tlb_probe_entry(p); 1102 } 1103 1104 static void __cpuinit 1105 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, 1106 struct uasm_reloc **r, unsigned int tmp, 1107 unsigned int ptr) 1108 { 1109 uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); 1110 uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); 1111 build_update_entries(p, tmp, ptr); 1112 build_tlb_write_entry(p, l, r, tlb_indexed); 1113 uasm_l_leave(l, *p); 1114 uasm_i_eret(p); /* return from trap */ 1115 1116 #ifdef CONFIG_64BIT 1117 build_get_pgd_vmalloc64(p, l, r, tmp, ptr); 1118 #endif 1119 } 1120 1121 static void __cpuinit build_r4000_tlb_load_handler(void) 1122 { 1123 u32 *p = handle_tlbl; 1124 struct uasm_label *l = labels; 1125 struct uasm_reloc *r = relocs; 1126 1127 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1128 memset(labels, 0, sizeof(labels)); 1129 memset(relocs, 0, sizeof(relocs)); 1130 1131 if (bcm1250_m3_war()) { 1132 UASM_i_MFC0(&p, K0, C0_BADVADDR); 1133 UASM_i_MFC0(&p, K1, C0_ENTRYHI); 1134 uasm_i_xor(&p, K0, K0, K1); 1135 UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); 1136 uasm_il_bnez(&p, &r, K0, label_leave); 1137 /* No need for uasm_i_nop */ 1138 } 1139 1140 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1141 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1142 if (m4kc_tlbp_war()) 1143 build_tlb_probe_entry(&p); 1144 build_make_valid(&p, &r, K0, K1); 1145 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1146 1147 uasm_l_nopage_tlbl(&l, p); 1148 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1149 uasm_i_nop(&p); 1150 1151 if ((p - handle_tlbl) > FASTPATH_SIZE) 1152 panic("TLB load handler fastpath space exceeded"); 1153 1154 uasm_resolve_relocs(relocs, labels); 1155 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1156 (unsigned int)(p - handle_tlbl)); 1157 1158 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); 1159 } 1160 1161 static void __cpuinit build_r4000_tlb_store_handler(void) 1162 { 1163 u32 *p = handle_tlbs; 1164 struct uasm_label *l = labels; 1165 struct uasm_reloc *r = relocs; 1166 1167 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1168 memset(labels, 0, sizeof(labels)); 1169 memset(relocs, 0, sizeof(relocs)); 1170 1171 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1172 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1173 if (m4kc_tlbp_war()) 1174 build_tlb_probe_entry(&p); 1175 build_make_write(&p, &r, K0, K1); 1176 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1177 1178 uasm_l_nopage_tlbs(&l, p); 1179 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1180 uasm_i_nop(&p); 1181 1182 if ((p - handle_tlbs) > FASTPATH_SIZE) 1183 panic("TLB store handler fastpath space exceeded"); 1184 1185 uasm_resolve_relocs(relocs, labels); 1186 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1187 (unsigned int)(p - handle_tlbs)); 1188 1189 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); 1190 } 1191 1192 static void __cpuinit build_r4000_tlb_modify_handler(void) 1193 { 1194 u32 *p = handle_tlbm; 1195 struct uasm_label *l = labels; 1196 struct uasm_reloc *r = relocs; 1197 1198 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1199 memset(labels, 0, sizeof(labels)); 1200 memset(relocs, 0, sizeof(relocs)); 1201 1202 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1203 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1204 if (m4kc_tlbp_war()) 1205 build_tlb_probe_entry(&p); 1206 /* Present and writable bits set, set accessed and dirty bits. */ 1207 build_make_write(&p, &r, K0, K1); 1208 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1209 1210 uasm_l_nopage_tlbm(&l, p); 1211 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1212 uasm_i_nop(&p); 1213 1214 if ((p - handle_tlbm) > FASTPATH_SIZE) 1215 panic("TLB modify handler fastpath space exceeded"); 1216 1217 uasm_resolve_relocs(relocs, labels); 1218 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 1219 (unsigned int)(p - handle_tlbm)); 1220 1221 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); 1222 } 1223 1224 void __cpuinit build_tlb_refill_handler(void) 1225 { 1226 /* 1227 * The refill handler is generated per-CPU, multi-node systems 1228 * may have local storage for it. The other handlers are only 1229 * needed once. 1230 */ 1231 static int run_once = 0; 1232 1233 switch (current_cpu_type()) { 1234 case CPU_R2000: 1235 case CPU_R3000: 1236 case CPU_R3000A: 1237 case CPU_R3081E: 1238 case CPU_TX3912: 1239 case CPU_TX3922: 1240 case CPU_TX3927: 1241 build_r3000_tlb_refill_handler(); 1242 if (!run_once) { 1243 build_r3000_tlb_load_handler(); 1244 build_r3000_tlb_store_handler(); 1245 build_r3000_tlb_modify_handler(); 1246 run_once++; 1247 } 1248 break; 1249 1250 case CPU_R6000: 1251 case CPU_R6000A: 1252 panic("No R6000 TLB refill handler yet"); 1253 break; 1254 1255 case CPU_R8000: 1256 panic("No R8000 TLB refill handler yet"); 1257 break; 1258 1259 default: 1260 build_r4000_tlb_refill_handler(); 1261 if (!run_once) { 1262 build_r4000_tlb_load_handler(); 1263 build_r4000_tlb_store_handler(); 1264 build_r4000_tlb_modify_handler(); 1265 run_once++; 1266 } 1267 } 1268 } 1269 1270 void __cpuinit flush_tlb_handlers(void) 1271 { 1272 local_flush_icache_range((unsigned long)handle_tlbl, 1273 (unsigned long)handle_tlbl + sizeof(handle_tlbl)); 1274 local_flush_icache_range((unsigned long)handle_tlbs, 1275 (unsigned long)handle_tlbs + sizeof(handle_tlbs)); 1276 local_flush_icache_range((unsigned long)handle_tlbm, 1277 (unsigned long)handle_tlbm + sizeof(handle_tlbm)); 1278 } 1279