1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 * Copyright (C) 2008, 2009 Cavium Networks, Inc. 12 * Copyright (C) 2011 MIPS Technologies, Inc. 13 * 14 * ... and the days got worse and worse and now you see 15 * I've gone completely out of my mind. 16 * 17 * They're coming to take me a away haha 18 * they're coming to take me a away hoho hihi haha 19 * to the funny farm where code is beautiful all the time ... 20 * 21 * (Condolences to Napoleon XIV) 22 */ 23 24 #include <linux/bug.h> 25 #include <linux/export.h> 26 #include <linux/kernel.h> 27 #include <linux/types.h> 28 #include <linux/smp.h> 29 #include <linux/string.h> 30 #include <linux/cache.h> 31 32 #include <asm/cacheflush.h> 33 #include <asm/cpu-type.h> 34 #include <asm/mmu_context.h> 35 #include <asm/pgtable.h> 36 #include <asm/war.h> 37 #include <asm/uasm.h> 38 #include <asm/setup.h> 39 #include <asm/tlbex.h> 40 41 static int mips_xpa_disabled; 42 43 static int __init xpa_disable(char *s) 44 { 45 mips_xpa_disabled = 1; 46 47 return 1; 48 } 49 50 __setup("noxpa", xpa_disable); 51 52 /* 53 * TLB load/store/modify handlers. 54 * 55 * Only the fastpath gets synthesized at runtime, the slowpath for 56 * do_page_fault remains normal asm. 57 */ 58 extern void tlb_do_page_fault_0(void); 59 extern void tlb_do_page_fault_1(void); 60 61 struct work_registers { 62 int r1; 63 int r2; 64 int r3; 65 }; 66 67 struct tlb_reg_save { 68 unsigned long a; 69 unsigned long b; 70 } ____cacheline_aligned_in_smp; 71 72 static struct tlb_reg_save handler_reg_save[NR_CPUS]; 73 74 static inline int r45k_bvahwbug(void) 75 { 76 /* XXX: We should probe for the presence of this bug, but we don't. */ 77 return 0; 78 } 79 80 static inline int r4k_250MHZhwbug(void) 81 { 82 /* XXX: We should probe for the presence of this bug, but we don't. */ 83 return 0; 84 } 85 86 static inline int __maybe_unused bcm1250_m3_war(void) 87 { 88 return BCM1250_M3_WAR; 89 } 90 91 static inline int __maybe_unused r10000_llsc_war(void) 92 { 93 return R10000_LLSC_WAR; 94 } 95 96 static int use_bbit_insns(void) 97 { 98 switch (current_cpu_type()) { 99 case CPU_CAVIUM_OCTEON: 100 case CPU_CAVIUM_OCTEON_PLUS: 101 case CPU_CAVIUM_OCTEON2: 102 case CPU_CAVIUM_OCTEON3: 103 return 1; 104 default: 105 return 0; 106 } 107 } 108 109 static int use_lwx_insns(void) 110 { 111 switch (current_cpu_type()) { 112 case CPU_CAVIUM_OCTEON2: 113 case CPU_CAVIUM_OCTEON3: 114 return 1; 115 default: 116 return 0; 117 } 118 } 119 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ 120 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 121 static bool scratchpad_available(void) 122 { 123 return true; 124 } 125 static int scratchpad_offset(int i) 126 { 127 /* 128 * CVMSEG starts at address -32768 and extends for 129 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. 130 */ 131 i += 1; /* Kernel use starts at the top and works down. */ 132 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; 133 } 134 #else 135 static bool scratchpad_available(void) 136 { 137 return false; 138 } 139 static int scratchpad_offset(int i) 140 { 141 BUG(); 142 /* Really unreachable, but evidently some GCC want this. */ 143 return 0; 144 } 145 #endif 146 /* 147 * Found by experiment: At least some revisions of the 4kc throw under 148 * some circumstances a machine check exception, triggered by invalid 149 * values in the index register. Delaying the tlbp instruction until 150 * after the next branch, plus adding an additional nop in front of 151 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows 152 * why; it's not an issue caused by the core RTL. 153 * 154 */ 155 static int m4kc_tlbp_war(void) 156 { 157 return current_cpu_type() == CPU_4KC; 158 } 159 160 /* Handle labels (which must be positive integers). */ 161 enum label_id { 162 label_second_part = 1, 163 label_leave, 164 label_vmalloc, 165 label_vmalloc_done, 166 label_tlbw_hazard_0, 167 label_split = label_tlbw_hazard_0 + 8, 168 label_tlbl_goaround1, 169 label_tlbl_goaround2, 170 label_nopage_tlbl, 171 label_nopage_tlbs, 172 label_nopage_tlbm, 173 label_smp_pgtable_change, 174 label_r3000_write_probe_fail, 175 label_large_segbits_fault, 176 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 177 label_tlb_huge_update, 178 #endif 179 }; 180 181 UASM_L_LA(_second_part) 182 UASM_L_LA(_leave) 183 UASM_L_LA(_vmalloc) 184 UASM_L_LA(_vmalloc_done) 185 /* _tlbw_hazard_x is handled differently. */ 186 UASM_L_LA(_split) 187 UASM_L_LA(_tlbl_goaround1) 188 UASM_L_LA(_tlbl_goaround2) 189 UASM_L_LA(_nopage_tlbl) 190 UASM_L_LA(_nopage_tlbs) 191 UASM_L_LA(_nopage_tlbm) 192 UASM_L_LA(_smp_pgtable_change) 193 UASM_L_LA(_r3000_write_probe_fail) 194 UASM_L_LA(_large_segbits_fault) 195 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 196 UASM_L_LA(_tlb_huge_update) 197 #endif 198 199 static int hazard_instance; 200 201 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) 202 { 203 switch (instance) { 204 case 0 ... 7: 205 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); 206 return; 207 default: 208 BUG(); 209 } 210 } 211 212 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) 213 { 214 switch (instance) { 215 case 0 ... 7: 216 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); 217 break; 218 default: 219 BUG(); 220 } 221 } 222 223 /* 224 * pgtable bits are assigned dynamically depending on processor feature 225 * and statically based on kernel configuration. This spits out the actual 226 * values the kernel is using. Required to make sense from disassembled 227 * TLB exception handlers. 228 */ 229 static void output_pgtable_bits_defines(void) 230 { 231 #define pr_define(fmt, ...) \ 232 pr_debug("#define " fmt, ##__VA_ARGS__) 233 234 pr_debug("#include <asm/asm.h>\n"); 235 pr_debug("#include <asm/regdef.h>\n"); 236 pr_debug("\n"); 237 238 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); 239 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); 240 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); 241 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); 242 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); 243 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 244 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); 245 #endif 246 #ifdef _PAGE_NO_EXEC_SHIFT 247 if (cpu_has_rixi) 248 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); 249 #endif 250 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); 251 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); 252 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); 253 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); 254 pr_debug("\n"); 255 } 256 257 static inline void dump_handler(const char *symbol, const void *start, const void *end) 258 { 259 unsigned int count = (end - start) / sizeof(u32); 260 const u32 *handler = start; 261 int i; 262 263 pr_debug("LEAF(%s)\n", symbol); 264 265 pr_debug("\t.set push\n"); 266 pr_debug("\t.set noreorder\n"); 267 268 for (i = 0; i < count; i++) 269 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); 270 271 pr_debug("\t.set\tpop\n"); 272 273 pr_debug("\tEND(%s)\n", symbol); 274 } 275 276 /* The only general purpose registers allowed in TLB handlers. */ 277 #define K0 26 278 #define K1 27 279 280 /* Some CP0 registers */ 281 #define C0_INDEX 0, 0 282 #define C0_ENTRYLO0 2, 0 283 #define C0_TCBIND 2, 2 284 #define C0_ENTRYLO1 3, 0 285 #define C0_CONTEXT 4, 0 286 #define C0_PAGEMASK 5, 0 287 #define C0_PWBASE 5, 5 288 #define C0_PWFIELD 5, 6 289 #define C0_PWSIZE 5, 7 290 #define C0_PWCTL 6, 6 291 #define C0_BADVADDR 8, 0 292 #define C0_PGD 9, 7 293 #define C0_ENTRYHI 10, 0 294 #define C0_EPC 14, 0 295 #define C0_XCONTEXT 20, 0 296 297 #ifdef CONFIG_64BIT 298 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) 299 #else 300 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) 301 #endif 302 303 /* The worst case length of the handler is around 18 instructions for 304 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 305 * Maximum space available is 32 instructions for R3000 and 64 306 * instructions for R4000. 307 * 308 * We deliberately chose a buffer size of 128, so we won't scribble 309 * over anything important on overflow before we panic. 310 */ 311 static u32 tlb_handler[128]; 312 313 /* simply assume worst case size for labels and relocs */ 314 static struct uasm_label labels[128]; 315 static struct uasm_reloc relocs[128]; 316 317 static int check_for_high_segbits; 318 static bool fill_includes_sw_bits; 319 320 static unsigned int kscratch_used_mask; 321 322 static inline int __maybe_unused c0_kscratch(void) 323 { 324 switch (current_cpu_type()) { 325 case CPU_XLP: 326 case CPU_XLR: 327 return 22; 328 default: 329 return 31; 330 } 331 } 332 333 static int allocate_kscratch(void) 334 { 335 int r; 336 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; 337 338 r = ffs(a); 339 340 if (r == 0) 341 return -1; 342 343 r--; /* make it zero based */ 344 345 kscratch_used_mask |= (1 << r); 346 347 return r; 348 } 349 350 static int scratch_reg; 351 int pgd_reg; 352 EXPORT_SYMBOL_GPL(pgd_reg); 353 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; 354 355 static struct work_registers build_get_work_registers(u32 **p) 356 { 357 struct work_registers r; 358 359 if (scratch_reg >= 0) { 360 /* Save in CPU local C0_KScratch? */ 361 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); 362 r.r1 = K0; 363 r.r2 = K1; 364 r.r3 = 1; 365 return r; 366 } 367 368 if (num_possible_cpus() > 1) { 369 /* Get smp_processor_id */ 370 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); 371 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); 372 373 /* handler_reg_save index in K0 */ 374 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); 375 376 UASM_i_LA(p, K1, (long)&handler_reg_save); 377 UASM_i_ADDU(p, K0, K0, K1); 378 } else { 379 UASM_i_LA(p, K0, (long)&handler_reg_save); 380 } 381 /* K0 now points to save area, save $1 and $2 */ 382 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); 383 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); 384 385 r.r1 = K1; 386 r.r2 = 1; 387 r.r3 = 2; 388 return r; 389 } 390 391 static void build_restore_work_registers(u32 **p) 392 { 393 if (scratch_reg >= 0) { 394 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 395 return; 396 } 397 /* K0 already points to save area, restore $1 and $2 */ 398 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); 399 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); 400 } 401 402 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 403 404 /* 405 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, 406 * we cannot do r3000 under these circumstances. 407 * 408 * The R3000 TLB handler is simple. 409 */ 410 static void build_r3000_tlb_refill_handler(void) 411 { 412 long pgdc = (long)pgd_current; 413 u32 *p; 414 415 memset(tlb_handler, 0, sizeof(tlb_handler)); 416 p = tlb_handler; 417 418 uasm_i_mfc0(&p, K0, C0_BADVADDR); 419 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ 420 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); 421 uasm_i_srl(&p, K0, K0, 22); /* load delay */ 422 uasm_i_sll(&p, K0, K0, 2); 423 uasm_i_addu(&p, K1, K1, K0); 424 uasm_i_mfc0(&p, K0, C0_CONTEXT); 425 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ 426 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ 427 uasm_i_addu(&p, K1, K1, K0); 428 uasm_i_lw(&p, K0, 0, K1); 429 uasm_i_nop(&p); /* load delay */ 430 uasm_i_mtc0(&p, K0, C0_ENTRYLO0); 431 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 432 uasm_i_tlbwr(&p); /* cp0 delay */ 433 uasm_i_jr(&p, K1); 434 uasm_i_rfe(&p); /* branch delay */ 435 436 if (p > tlb_handler + 32) 437 panic("TLB refill handler space exceeded"); 438 439 pr_debug("Wrote TLB refill handler (%u instructions).\n", 440 (unsigned int)(p - tlb_handler)); 441 442 memcpy((void *)ebase, tlb_handler, 0x80); 443 local_flush_icache_range(ebase, ebase + 0x80); 444 dump_handler("r3000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x80)); 445 } 446 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 447 448 /* 449 * The R4000 TLB handler is much more complicated. We have two 450 * consecutive handler areas with 32 instructions space each. 451 * Since they aren't used at the same time, we can overflow in the 452 * other one.To keep things simple, we first assume linear space, 453 * then we relocate it to the final handler layout as needed. 454 */ 455 static u32 final_handler[64]; 456 457 /* 458 * Hazards 459 * 460 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 461 * 2. A timing hazard exists for the TLBP instruction. 462 * 463 * stalling_instruction 464 * TLBP 465 * 466 * The JTLB is being read for the TLBP throughout the stall generated by the 467 * previous instruction. This is not really correct as the stalling instruction 468 * can modify the address used to access the JTLB. The failure symptom is that 469 * the TLBP instruction will use an address created for the stalling instruction 470 * and not the address held in C0_ENHI and thus report the wrong results. 471 * 472 * The software work-around is to not allow the instruction preceding the TLBP 473 * to stall - make it an NOP or some other instruction guaranteed not to stall. 474 * 475 * Errata 2 will not be fixed. This errata is also on the R5000. 476 * 477 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 478 */ 479 static void __maybe_unused build_tlb_probe_entry(u32 **p) 480 { 481 switch (current_cpu_type()) { 482 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ 483 case CPU_R4600: 484 case CPU_R4700: 485 case CPU_R5000: 486 case CPU_NEVADA: 487 uasm_i_nop(p); 488 uasm_i_tlbp(p); 489 break; 490 491 default: 492 uasm_i_tlbp(p); 493 break; 494 } 495 } 496 497 void build_tlb_write_entry(u32 **p, struct uasm_label **l, 498 struct uasm_reloc **r, 499 enum tlb_write_entry wmode) 500 { 501 void(*tlbw)(u32 **) = NULL; 502 503 switch (wmode) { 504 case tlb_random: tlbw = uasm_i_tlbwr; break; 505 case tlb_indexed: tlbw = uasm_i_tlbwi; break; 506 } 507 508 if (cpu_has_mips_r2_r6) { 509 if (cpu_has_mips_r2_exec_hazard) 510 uasm_i_ehb(p); 511 tlbw(p); 512 return; 513 } 514 515 switch (current_cpu_type()) { 516 case CPU_R4000PC: 517 case CPU_R4000SC: 518 case CPU_R4000MC: 519 case CPU_R4400PC: 520 case CPU_R4400SC: 521 case CPU_R4400MC: 522 /* 523 * This branch uses up a mtc0 hazard nop slot and saves 524 * two nops after the tlbw instruction. 525 */ 526 uasm_bgezl_hazard(p, r, hazard_instance); 527 tlbw(p); 528 uasm_bgezl_label(l, p, hazard_instance); 529 hazard_instance++; 530 uasm_i_nop(p); 531 break; 532 533 case CPU_R4600: 534 case CPU_R4700: 535 uasm_i_nop(p); 536 tlbw(p); 537 uasm_i_nop(p); 538 break; 539 540 case CPU_R5000: 541 case CPU_NEVADA: 542 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 543 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 544 tlbw(p); 545 break; 546 547 case CPU_R4300: 548 case CPU_5KC: 549 case CPU_TX49XX: 550 case CPU_PR4450: 551 case CPU_XLR: 552 uasm_i_nop(p); 553 tlbw(p); 554 break; 555 556 case CPU_R10000: 557 case CPU_R12000: 558 case CPU_R14000: 559 case CPU_R16000: 560 case CPU_4KC: 561 case CPU_4KEC: 562 case CPU_M14KC: 563 case CPU_M14KEC: 564 case CPU_SB1: 565 case CPU_SB1A: 566 case CPU_4KSC: 567 case CPU_20KC: 568 case CPU_25KF: 569 case CPU_BMIPS32: 570 case CPU_BMIPS3300: 571 case CPU_BMIPS4350: 572 case CPU_BMIPS4380: 573 case CPU_BMIPS5000: 574 case CPU_LOONGSON2: 575 case CPU_LOONGSON3: 576 case CPU_R5500: 577 if (m4kc_tlbp_war()) 578 uasm_i_nop(p); 579 /* fall through */ 580 case CPU_ALCHEMY: 581 tlbw(p); 582 break; 583 584 case CPU_RM7000: 585 uasm_i_nop(p); 586 uasm_i_nop(p); 587 uasm_i_nop(p); 588 uasm_i_nop(p); 589 tlbw(p); 590 break; 591 592 case CPU_VR4111: 593 case CPU_VR4121: 594 case CPU_VR4122: 595 case CPU_VR4181: 596 case CPU_VR4181A: 597 uasm_i_nop(p); 598 uasm_i_nop(p); 599 tlbw(p); 600 uasm_i_nop(p); 601 uasm_i_nop(p); 602 break; 603 604 case CPU_VR4131: 605 case CPU_VR4133: 606 case CPU_R5432: 607 uasm_i_nop(p); 608 uasm_i_nop(p); 609 tlbw(p); 610 break; 611 612 case CPU_JZRISC: 613 tlbw(p); 614 uasm_i_nop(p); 615 break; 616 617 default: 618 panic("No TLB refill handler yet (CPU type: %d)", 619 current_cpu_type()); 620 break; 621 } 622 } 623 EXPORT_SYMBOL_GPL(build_tlb_write_entry); 624 625 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, 626 unsigned int reg) 627 { 628 if (_PAGE_GLOBAL_SHIFT == 0) { 629 /* pte_t is already in EntryLo format */ 630 return; 631 } 632 633 if (cpu_has_rixi && _PAGE_NO_EXEC) { 634 if (fill_includes_sw_bits) { 635 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); 636 } else { 637 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); 638 UASM_i_ROTR(p, reg, reg, 639 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); 640 } 641 } else { 642 #ifdef CONFIG_PHYS_ADDR_T_64BIT 643 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); 644 #else 645 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); 646 #endif 647 } 648 } 649 650 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 651 652 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, 653 unsigned int tmp, enum label_id lid, 654 int restore_scratch) 655 { 656 if (restore_scratch) { 657 /* Reset default page size */ 658 if (PM_DEFAULT_MASK >> 16) { 659 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 660 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 661 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 662 uasm_il_b(p, r, lid); 663 } else if (PM_DEFAULT_MASK) { 664 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 665 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 666 uasm_il_b(p, r, lid); 667 } else { 668 uasm_i_mtc0(p, 0, C0_PAGEMASK); 669 uasm_il_b(p, r, lid); 670 } 671 if (scratch_reg >= 0) 672 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 673 else 674 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 675 } else { 676 /* Reset default page size */ 677 if (PM_DEFAULT_MASK >> 16) { 678 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 679 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 680 uasm_il_b(p, r, lid); 681 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 682 } else if (PM_DEFAULT_MASK) { 683 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 684 uasm_il_b(p, r, lid); 685 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 686 } else { 687 uasm_il_b(p, r, lid); 688 uasm_i_mtc0(p, 0, C0_PAGEMASK); 689 } 690 } 691 } 692 693 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, 694 struct uasm_reloc **r, 695 unsigned int tmp, 696 enum tlb_write_entry wmode, 697 int restore_scratch) 698 { 699 /* Set huge page tlb entry size */ 700 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); 701 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); 702 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 703 704 build_tlb_write_entry(p, l, r, wmode); 705 706 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); 707 } 708 709 /* 710 * Check if Huge PTE is present, if so then jump to LABEL. 711 */ 712 static void 713 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, 714 unsigned int pmd, int lid) 715 { 716 UASM_i_LW(p, tmp, 0, pmd); 717 if (use_bbit_insns()) { 718 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); 719 } else { 720 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); 721 uasm_il_bnez(p, r, tmp, lid); 722 } 723 } 724 725 static void build_huge_update_entries(u32 **p, unsigned int pte, 726 unsigned int tmp) 727 { 728 int small_sequence; 729 730 /* 731 * A huge PTE describes an area the size of the 732 * configured huge page size. This is twice the 733 * of the large TLB entry size we intend to use. 734 * A TLB entry half the size of the configured 735 * huge page size is configured into entrylo0 736 * and entrylo1 to cover the contiguous huge PTE 737 * address space. 738 */ 739 small_sequence = (HPAGE_SIZE >> 7) < 0x10000; 740 741 /* We can clobber tmp. It isn't used after this.*/ 742 if (!small_sequence) 743 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); 744 745 build_convert_pte_to_entrylo(p, pte); 746 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ 747 /* convert to entrylo1 */ 748 if (small_sequence) 749 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); 750 else 751 UASM_i_ADDU(p, pte, pte, tmp); 752 753 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ 754 } 755 756 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, 757 struct uasm_label **l, 758 unsigned int pte, 759 unsigned int ptr, 760 unsigned int flush) 761 { 762 #ifdef CONFIG_SMP 763 UASM_i_SC(p, pte, 0, ptr); 764 uasm_il_beqz(p, r, pte, label_tlb_huge_update); 765 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ 766 #else 767 UASM_i_SW(p, pte, 0, ptr); 768 #endif 769 if (cpu_has_ftlb && flush) { 770 BUG_ON(!cpu_has_tlbinv); 771 772 UASM_i_MFC0(p, ptr, C0_ENTRYHI); 773 uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); 774 UASM_i_MTC0(p, ptr, C0_ENTRYHI); 775 build_tlb_write_entry(p, l, r, tlb_indexed); 776 777 uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); 778 UASM_i_MTC0(p, ptr, C0_ENTRYHI); 779 build_huge_update_entries(p, pte, ptr); 780 build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0); 781 782 return; 783 } 784 785 build_huge_update_entries(p, pte, ptr); 786 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); 787 } 788 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 789 790 #ifdef CONFIG_64BIT 791 /* 792 * TMP and PTR are scratch. 793 * TMP will be clobbered, PTR will hold the pmd entry. 794 */ 795 void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 796 unsigned int tmp, unsigned int ptr) 797 { 798 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 799 long pgdc = (long)pgd_current; 800 #endif 801 /* 802 * The vmalloc handling is not in the hotpath. 803 */ 804 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 805 806 if (check_for_high_segbits) { 807 /* 808 * The kernel currently implicitely assumes that the 809 * MIPS SEGBITS parameter for the processor is 810 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never 811 * allocate virtual addresses outside the maximum 812 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But 813 * that doesn't prevent user code from accessing the 814 * higher xuseg addresses. Here, we make sure that 815 * everything but the lower xuseg addresses goes down 816 * the module_alloc/vmalloc path. 817 */ 818 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 819 uasm_il_bnez(p, r, ptr, label_vmalloc); 820 } else { 821 uasm_il_bltz(p, r, tmp, label_vmalloc); 822 } 823 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 824 825 if (pgd_reg != -1) { 826 /* pgd is in pgd_reg */ 827 if (cpu_has_ldpte) 828 UASM_i_MFC0(p, ptr, C0_PWBASE); 829 else 830 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 831 } else { 832 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT) 833 /* 834 * &pgd << 11 stored in CONTEXT [23..63]. 835 */ 836 UASM_i_MFC0(p, ptr, C0_CONTEXT); 837 838 /* Clear lower 23 bits of context. */ 839 uasm_i_dins(p, ptr, 0, 0, 23); 840 841 /* 1 0 1 0 1 << 6 xkphys cached */ 842 uasm_i_ori(p, ptr, ptr, 0x540); 843 uasm_i_drotr(p, ptr, ptr, 11); 844 #elif defined(CONFIG_SMP) 845 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); 846 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 847 UASM_i_LA_mostly(p, tmp, pgdc); 848 uasm_i_daddu(p, ptr, ptr, tmp); 849 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 850 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 851 #else 852 UASM_i_LA_mostly(p, ptr, pgdc); 853 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 854 #endif 855 } 856 857 uasm_l_vmalloc_done(l, *p); 858 859 /* get pgd offset in bytes */ 860 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); 861 862 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 863 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 864 #ifndef __PAGETABLE_PUD_FOLDED 865 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 866 uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */ 867 uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */ 868 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3); 869 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */ 870 #endif 871 #ifndef __PAGETABLE_PMD_FOLDED 872 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 873 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 874 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 875 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 876 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 877 #endif 878 } 879 EXPORT_SYMBOL_GPL(build_get_pmde64); 880 881 /* 882 * BVADDR is the faulting address, PTR is scratch. 883 * PTR will hold the pgd for vmalloc. 884 */ 885 static void 886 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 887 unsigned int bvaddr, unsigned int ptr, 888 enum vmalloc64_mode mode) 889 { 890 long swpd = (long)swapper_pg_dir; 891 int single_insn_swpd; 892 int did_vmalloc_branch = 0; 893 894 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); 895 896 uasm_l_vmalloc(l, *p); 897 898 if (mode != not_refill && check_for_high_segbits) { 899 if (single_insn_swpd) { 900 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); 901 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 902 did_vmalloc_branch = 1; 903 /* fall through */ 904 } else { 905 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); 906 } 907 } 908 if (!did_vmalloc_branch) { 909 if (single_insn_swpd) { 910 uasm_il_b(p, r, label_vmalloc_done); 911 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 912 } else { 913 UASM_i_LA_mostly(p, ptr, swpd); 914 uasm_il_b(p, r, label_vmalloc_done); 915 if (uasm_in_compat_space_p(swpd)) 916 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); 917 else 918 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); 919 } 920 } 921 if (mode != not_refill && check_for_high_segbits) { 922 uasm_l_large_segbits_fault(l, *p); 923 /* 924 * We get here if we are an xsseg address, or if we are 925 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. 926 * 927 * Ignoring xsseg (assume disabled so would generate 928 * (address errors?), the only remaining possibility 929 * is the upper xuseg addresses. On processors with 930 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these 931 * addresses would have taken an address error. We try 932 * to mimic that here by taking a load/istream page 933 * fault. 934 */ 935 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); 936 uasm_i_jr(p, ptr); 937 938 if (mode == refill_scratch) { 939 if (scratch_reg >= 0) 940 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 941 else 942 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 943 } else { 944 uasm_i_nop(p); 945 } 946 } 947 } 948 949 #else /* !CONFIG_64BIT */ 950 951 /* 952 * TMP and PTR are scratch. 953 * TMP will be clobbered, PTR will hold the pgd entry. 954 */ 955 void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 956 { 957 if (pgd_reg != -1) { 958 /* pgd is in pgd_reg */ 959 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); 960 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 961 } else { 962 long pgdc = (long)pgd_current; 963 964 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 965 #ifdef CONFIG_SMP 966 uasm_i_mfc0(p, ptr, SMP_CPUID_REG); 967 UASM_i_LA_mostly(p, tmp, pgdc); 968 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 969 uasm_i_addu(p, ptr, tmp, ptr); 970 #else 971 UASM_i_LA_mostly(p, ptr, pgdc); 972 #endif 973 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 974 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 975 } 976 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 977 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); 978 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 979 } 980 EXPORT_SYMBOL_GPL(build_get_pgde32); 981 982 #endif /* !CONFIG_64BIT */ 983 984 static void build_adjust_context(u32 **p, unsigned int ctx) 985 { 986 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 987 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 988 989 switch (current_cpu_type()) { 990 case CPU_VR41XX: 991 case CPU_VR4111: 992 case CPU_VR4121: 993 case CPU_VR4122: 994 case CPU_VR4131: 995 case CPU_VR4181: 996 case CPU_VR4181A: 997 case CPU_VR4133: 998 shift += 2; 999 break; 1000 1001 default: 1002 break; 1003 } 1004 1005 if (shift) 1006 UASM_i_SRL(p, ctx, ctx, shift); 1007 uasm_i_andi(p, ctx, ctx, mask); 1008 } 1009 1010 void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1011 { 1012 /* 1013 * Bug workaround for the Nevada. It seems as if under certain 1014 * circumstances the move from cp0_context might produce a 1015 * bogus result when the mfc0 instruction and its consumer are 1016 * in a different cacheline or a load instruction, probably any 1017 * memory reference, is between them. 1018 */ 1019 switch (current_cpu_type()) { 1020 case CPU_NEVADA: 1021 UASM_i_LW(p, ptr, 0, ptr); 1022 GET_CONTEXT(p, tmp); /* get context reg */ 1023 break; 1024 1025 default: 1026 GET_CONTEXT(p, tmp); /* get context reg */ 1027 UASM_i_LW(p, ptr, 0, ptr); 1028 break; 1029 } 1030 1031 build_adjust_context(p, tmp); 1032 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1033 } 1034 EXPORT_SYMBOL_GPL(build_get_ptep); 1035 1036 void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) 1037 { 1038 int pte_off_even = 0; 1039 int pte_off_odd = sizeof(pte_t); 1040 1041 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT) 1042 /* The low 32 bits of EntryLo is stored in pte_high */ 1043 pte_off_even += offsetof(pte_t, pte_high); 1044 pte_off_odd += offsetof(pte_t, pte_high); 1045 #endif 1046 1047 if (IS_ENABLED(CONFIG_XPA)) { 1048 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */ 1049 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1050 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); 1051 1052 if (cpu_has_xpa && !mips_xpa_disabled) { 1053 uasm_i_lw(p, tmp, 0, ptep); 1054 uasm_i_ext(p, tmp, tmp, 0, 24); 1055 uasm_i_mthc0(p, tmp, C0_ENTRYLO0); 1056 } 1057 1058 uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */ 1059 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1060 UASM_i_MTC0(p, tmp, C0_ENTRYLO1); 1061 1062 if (cpu_has_xpa && !mips_xpa_disabled) { 1063 uasm_i_lw(p, tmp, sizeof(pte_t), ptep); 1064 uasm_i_ext(p, tmp, tmp, 0, 24); 1065 uasm_i_mthc0(p, tmp, C0_ENTRYLO1); 1066 } 1067 return; 1068 } 1069 1070 UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */ 1071 UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */ 1072 if (r45k_bvahwbug()) 1073 build_tlb_probe_entry(p); 1074 build_convert_pte_to_entrylo(p, tmp); 1075 if (r4k_250MHZhwbug()) 1076 UASM_i_MTC0(p, 0, C0_ENTRYLO0); 1077 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ 1078 build_convert_pte_to_entrylo(p, ptep); 1079 if (r45k_bvahwbug()) 1080 uasm_i_mfc0(p, tmp, C0_INDEX); 1081 if (r4k_250MHZhwbug()) 1082 UASM_i_MTC0(p, 0, C0_ENTRYLO1); 1083 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ 1084 } 1085 EXPORT_SYMBOL_GPL(build_update_entries); 1086 1087 struct mips_huge_tlb_info { 1088 int huge_pte; 1089 int restore_scratch; 1090 bool need_reload_pte; 1091 }; 1092 1093 static struct mips_huge_tlb_info 1094 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, 1095 struct uasm_reloc **r, unsigned int tmp, 1096 unsigned int ptr, int c0_scratch_reg) 1097 { 1098 struct mips_huge_tlb_info rv; 1099 unsigned int even, odd; 1100 int vmalloc_branch_delay_filled = 0; 1101 const int scratch = 1; /* Our extra working register */ 1102 1103 rv.huge_pte = scratch; 1104 rv.restore_scratch = 0; 1105 rv.need_reload_pte = false; 1106 1107 if (check_for_high_segbits) { 1108 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1109 1110 if (pgd_reg != -1) 1111 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1112 else 1113 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1114 1115 if (c0_scratch_reg >= 0) 1116 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1117 else 1118 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1119 1120 uasm_i_dsrl_safe(p, scratch, tmp, 1121 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1122 uasm_il_bnez(p, r, scratch, label_vmalloc); 1123 1124 if (pgd_reg == -1) { 1125 vmalloc_branch_delay_filled = 1; 1126 /* Clear lower 23 bits of context. */ 1127 uasm_i_dins(p, ptr, 0, 0, 23); 1128 } 1129 } else { 1130 if (pgd_reg != -1) 1131 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1132 else 1133 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1134 1135 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1136 1137 if (c0_scratch_reg >= 0) 1138 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1139 else 1140 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1141 1142 if (pgd_reg == -1) 1143 /* Clear lower 23 bits of context. */ 1144 uasm_i_dins(p, ptr, 0, 0, 23); 1145 1146 uasm_il_bltz(p, r, tmp, label_vmalloc); 1147 } 1148 1149 if (pgd_reg == -1) { 1150 vmalloc_branch_delay_filled = 1; 1151 /* 1 0 1 0 1 << 6 xkphys cached */ 1152 uasm_i_ori(p, ptr, ptr, 0x540); 1153 uasm_i_drotr(p, ptr, ptr, 11); 1154 } 1155 1156 #ifdef __PAGETABLE_PMD_FOLDED 1157 #define LOC_PTEP scratch 1158 #else 1159 #define LOC_PTEP ptr 1160 #endif 1161 1162 if (!vmalloc_branch_delay_filled) 1163 /* get pgd offset in bytes */ 1164 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1165 1166 uasm_l_vmalloc_done(l, *p); 1167 1168 /* 1169 * tmp ptr 1170 * fall-through case = badvaddr *pgd_current 1171 * vmalloc case = badvaddr swapper_pg_dir 1172 */ 1173 1174 if (vmalloc_branch_delay_filled) 1175 /* get pgd offset in bytes */ 1176 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1177 1178 #ifdef __PAGETABLE_PMD_FOLDED 1179 GET_CONTEXT(p, tmp); /* get context reg */ 1180 #endif 1181 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); 1182 1183 if (use_lwx_insns()) { 1184 UASM_i_LWX(p, LOC_PTEP, scratch, ptr); 1185 } else { 1186 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ 1187 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ 1188 } 1189 1190 #ifndef __PAGETABLE_PUD_FOLDED 1191 /* get pud offset in bytes */ 1192 uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3); 1193 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3); 1194 1195 if (use_lwx_insns()) { 1196 UASM_i_LWX(p, ptr, scratch, ptr); 1197 } else { 1198 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1199 UASM_i_LW(p, ptr, 0, ptr); 1200 } 1201 /* ptr contains a pointer to PMD entry */ 1202 /* tmp contains the address */ 1203 #endif 1204 1205 #ifndef __PAGETABLE_PMD_FOLDED 1206 /* get pmd offset in bytes */ 1207 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); 1208 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); 1209 GET_CONTEXT(p, tmp); /* get context reg */ 1210 1211 if (use_lwx_insns()) { 1212 UASM_i_LWX(p, scratch, scratch, ptr); 1213 } else { 1214 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1215 UASM_i_LW(p, scratch, 0, ptr); 1216 } 1217 #endif 1218 /* Adjust the context during the load latency. */ 1219 build_adjust_context(p, tmp); 1220 1221 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1222 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); 1223 /* 1224 * The in the LWX case we don't want to do the load in the 1225 * delay slot. It cannot issue in the same cycle and may be 1226 * speculative and unneeded. 1227 */ 1228 if (use_lwx_insns()) 1229 uasm_i_nop(p); 1230 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 1231 1232 1233 /* build_update_entries */ 1234 if (use_lwx_insns()) { 1235 even = ptr; 1236 odd = tmp; 1237 UASM_i_LWX(p, even, scratch, tmp); 1238 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); 1239 UASM_i_LWX(p, odd, scratch, tmp); 1240 } else { 1241 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ 1242 even = tmp; 1243 odd = ptr; 1244 UASM_i_LW(p, even, 0, ptr); /* get even pte */ 1245 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ 1246 } 1247 if (cpu_has_rixi) { 1248 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); 1249 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1250 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1251 } else { 1252 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); 1253 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1254 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1255 } 1256 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ 1257 1258 if (c0_scratch_reg >= 0) { 1259 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1260 build_tlb_write_entry(p, l, r, tlb_random); 1261 uasm_l_leave(l, *p); 1262 rv.restore_scratch = 1; 1263 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { 1264 build_tlb_write_entry(p, l, r, tlb_random); 1265 uasm_l_leave(l, *p); 1266 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1267 } else { 1268 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1269 build_tlb_write_entry(p, l, r, tlb_random); 1270 uasm_l_leave(l, *p); 1271 rv.restore_scratch = 1; 1272 } 1273 1274 uasm_i_eret(p); /* return from trap */ 1275 1276 return rv; 1277 } 1278 1279 /* 1280 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception 1281 * because EXL == 0. If we wrap, we can also use the 32 instruction 1282 * slots before the XTLB refill exception handler which belong to the 1283 * unused TLB refill exception. 1284 */ 1285 #define MIPS64_REFILL_INSNS 32 1286 1287 static void build_r4000_tlb_refill_handler(void) 1288 { 1289 u32 *p = tlb_handler; 1290 struct uasm_label *l = labels; 1291 struct uasm_reloc *r = relocs; 1292 u32 *f; 1293 unsigned int final_len; 1294 struct mips_huge_tlb_info htlb_info __maybe_unused; 1295 enum vmalloc64_mode vmalloc_mode __maybe_unused; 1296 1297 memset(tlb_handler, 0, sizeof(tlb_handler)); 1298 memset(labels, 0, sizeof(labels)); 1299 memset(relocs, 0, sizeof(relocs)); 1300 memset(final_handler, 0, sizeof(final_handler)); 1301 1302 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { 1303 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, 1304 scratch_reg); 1305 vmalloc_mode = refill_scratch; 1306 } else { 1307 htlb_info.huge_pte = K0; 1308 htlb_info.restore_scratch = 0; 1309 htlb_info.need_reload_pte = true; 1310 vmalloc_mode = refill_noscratch; 1311 /* 1312 * create the plain linear handler 1313 */ 1314 if (bcm1250_m3_war()) { 1315 unsigned int segbits = 44; 1316 1317 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1318 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 1319 uasm_i_xor(&p, K0, K0, K1); 1320 uasm_i_dsrl_safe(&p, K1, K0, 62); 1321 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 1322 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 1323 uasm_i_or(&p, K0, K0, K1); 1324 uasm_il_bnez(&p, &r, K0, label_leave); 1325 /* No need for uasm_i_nop */ 1326 } 1327 1328 #ifdef CONFIG_64BIT 1329 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1330 #else 1331 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1332 #endif 1333 1334 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1335 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); 1336 #endif 1337 1338 build_get_ptep(&p, K0, K1); 1339 build_update_entries(&p, K0, K1); 1340 build_tlb_write_entry(&p, &l, &r, tlb_random); 1341 uasm_l_leave(&l, p); 1342 uasm_i_eret(&p); /* return from trap */ 1343 } 1344 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1345 uasm_l_tlb_huge_update(&l, p); 1346 if (htlb_info.need_reload_pte) 1347 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1); 1348 build_huge_update_entries(&p, htlb_info.huge_pte, K1); 1349 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, 1350 htlb_info.restore_scratch); 1351 #endif 1352 1353 #ifdef CONFIG_64BIT 1354 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); 1355 #endif 1356 1357 /* 1358 * Overflow check: For the 64bit handler, we need at least one 1359 * free instruction slot for the wrap-around branch. In worst 1360 * case, if the intended insertion point is a delay slot, we 1361 * need three, with the second nop'ed and the third being 1362 * unused. 1363 */ 1364 switch (boot_cpu_type()) { 1365 default: 1366 if (sizeof(long) == 4) { 1367 case CPU_LOONGSON2: 1368 /* Loongson2 ebase is different than r4k, we have more space */ 1369 if ((p - tlb_handler) > 64) 1370 panic("TLB refill handler space exceeded"); 1371 /* 1372 * Now fold the handler in the TLB refill handler space. 1373 */ 1374 f = final_handler; 1375 /* Simplest case, just copy the handler. */ 1376 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1377 final_len = p - tlb_handler; 1378 break; 1379 } else { 1380 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) 1381 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) 1382 && uasm_insn_has_bdelay(relocs, 1383 tlb_handler + MIPS64_REFILL_INSNS - 3))) 1384 panic("TLB refill handler space exceeded"); 1385 /* 1386 * Now fold the handler in the TLB refill handler space. 1387 */ 1388 f = final_handler + MIPS64_REFILL_INSNS; 1389 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { 1390 /* Just copy the handler. */ 1391 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1392 final_len = p - tlb_handler; 1393 } else { 1394 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1395 const enum label_id ls = label_tlb_huge_update; 1396 #else 1397 const enum label_id ls = label_vmalloc; 1398 #endif 1399 u32 *split; 1400 int ov = 0; 1401 int i; 1402 1403 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) 1404 ; 1405 BUG_ON(i == ARRAY_SIZE(labels)); 1406 split = labels[i].addr; 1407 1408 /* 1409 * See if we have overflown one way or the other. 1410 */ 1411 if (split > tlb_handler + MIPS64_REFILL_INSNS || 1412 split < p - MIPS64_REFILL_INSNS) 1413 ov = 1; 1414 1415 if (ov) { 1416 /* 1417 * Split two instructions before the end. One 1418 * for the branch and one for the instruction 1419 * in the delay slot. 1420 */ 1421 split = tlb_handler + MIPS64_REFILL_INSNS - 2; 1422 1423 /* 1424 * If the branch would fall in a delay slot, 1425 * we must back up an additional instruction 1426 * so that it is no longer in a delay slot. 1427 */ 1428 if (uasm_insn_has_bdelay(relocs, split - 1)) 1429 split--; 1430 } 1431 /* Copy first part of the handler. */ 1432 uasm_copy_handler(relocs, labels, tlb_handler, split, f); 1433 f += split - tlb_handler; 1434 1435 if (ov) { 1436 /* Insert branch. */ 1437 uasm_l_split(&l, final_handler); 1438 uasm_il_b(&f, &r, label_split); 1439 if (uasm_insn_has_bdelay(relocs, split)) 1440 uasm_i_nop(&f); 1441 else { 1442 uasm_copy_handler(relocs, labels, 1443 split, split + 1, f); 1444 uasm_move_labels(labels, f, f + 1, -1); 1445 f++; 1446 split++; 1447 } 1448 } 1449 1450 /* Copy the rest of the handler. */ 1451 uasm_copy_handler(relocs, labels, split, p, final_handler); 1452 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + 1453 (p - split); 1454 } 1455 } 1456 break; 1457 } 1458 1459 uasm_resolve_relocs(relocs, labels); 1460 pr_debug("Wrote TLB refill handler (%u instructions).\n", 1461 final_len); 1462 1463 memcpy((void *)ebase, final_handler, 0x100); 1464 local_flush_icache_range(ebase, ebase + 0x100); 1465 dump_handler("r4000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x100)); 1466 } 1467 1468 static void setup_pw(void) 1469 { 1470 unsigned long pgd_i, pgd_w; 1471 #ifndef __PAGETABLE_PMD_FOLDED 1472 unsigned long pmd_i, pmd_w; 1473 #endif 1474 unsigned long pt_i, pt_w; 1475 unsigned long pte_i, pte_w; 1476 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1477 unsigned long psn; 1478 1479 psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */ 1480 #endif 1481 pgd_i = PGDIR_SHIFT; /* 1st level PGD */ 1482 #ifndef __PAGETABLE_PMD_FOLDED 1483 pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER; 1484 1485 pmd_i = PMD_SHIFT; /* 2nd level PMD */ 1486 pmd_w = PMD_SHIFT - PAGE_SHIFT; 1487 #else 1488 pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER; 1489 #endif 1490 1491 pt_i = PAGE_SHIFT; /* 3rd level PTE */ 1492 pt_w = PAGE_SHIFT - 3; 1493 1494 pte_i = ilog2(_PAGE_GLOBAL); 1495 pte_w = 0; 1496 1497 #ifndef __PAGETABLE_PMD_FOLDED 1498 write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i); 1499 write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w); 1500 #else 1501 write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i); 1502 write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w); 1503 #endif 1504 1505 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1506 write_c0_pwctl(1 << 6 | psn); 1507 #endif 1508 write_c0_kpgd((long)swapper_pg_dir); 1509 kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */ 1510 } 1511 1512 static void build_loongson3_tlb_refill_handler(void) 1513 { 1514 u32 *p = tlb_handler; 1515 struct uasm_label *l = labels; 1516 struct uasm_reloc *r = relocs; 1517 1518 memset(labels, 0, sizeof(labels)); 1519 memset(relocs, 0, sizeof(relocs)); 1520 memset(tlb_handler, 0, sizeof(tlb_handler)); 1521 1522 if (check_for_high_segbits) { 1523 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1524 uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1525 uasm_il_beqz(&p, &r, K1, label_vmalloc); 1526 uasm_i_nop(&p); 1527 1528 uasm_il_bgez(&p, &r, K0, label_large_segbits_fault); 1529 uasm_i_nop(&p); 1530 uasm_l_vmalloc(&l, p); 1531 } 1532 1533 uasm_i_dmfc0(&p, K1, C0_PGD); 1534 1535 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */ 1536 #ifndef __PAGETABLE_PMD_FOLDED 1537 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */ 1538 #endif 1539 uasm_i_ldpte(&p, K1, 0); /* even */ 1540 uasm_i_ldpte(&p, K1, 1); /* odd */ 1541 uasm_i_tlbwr(&p); 1542 1543 /* restore page mask */ 1544 if (PM_DEFAULT_MASK >> 16) { 1545 uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16); 1546 uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff); 1547 uasm_i_mtc0(&p, K0, C0_PAGEMASK); 1548 } else if (PM_DEFAULT_MASK) { 1549 uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK); 1550 uasm_i_mtc0(&p, K0, C0_PAGEMASK); 1551 } else { 1552 uasm_i_mtc0(&p, 0, C0_PAGEMASK); 1553 } 1554 1555 uasm_i_eret(&p); 1556 1557 if (check_for_high_segbits) { 1558 uasm_l_large_segbits_fault(&l, p); 1559 UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0); 1560 uasm_i_jr(&p, K1); 1561 uasm_i_nop(&p); 1562 } 1563 1564 uasm_resolve_relocs(relocs, labels); 1565 memcpy((void *)(ebase + 0x80), tlb_handler, 0x80); 1566 local_flush_icache_range(ebase + 0x80, ebase + 0x100); 1567 dump_handler("loongson3_tlb_refill", 1568 (u32 *)(ebase + 0x80), (u32 *)(ebase + 0x100)); 1569 } 1570 1571 static void build_setup_pgd(void) 1572 { 1573 const int a0 = 4; 1574 const int __maybe_unused a1 = 5; 1575 const int __maybe_unused a2 = 6; 1576 u32 *p = (u32 *)msk_isa16_mode((ulong)tlbmiss_handler_setup_pgd); 1577 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1578 long pgdc = (long)pgd_current; 1579 #endif 1580 1581 memset(p, 0, tlbmiss_handler_setup_pgd_end - (char *)p); 1582 memset(labels, 0, sizeof(labels)); 1583 memset(relocs, 0, sizeof(relocs)); 1584 pgd_reg = allocate_kscratch(); 1585 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 1586 if (pgd_reg == -1) { 1587 struct uasm_label *l = labels; 1588 struct uasm_reloc *r = relocs; 1589 1590 /* PGD << 11 in c0_Context */ 1591 /* 1592 * If it is a ckseg0 address, convert to a physical 1593 * address. Shifting right by 29 and adding 4 will 1594 * result in zero for these addresses. 1595 * 1596 */ 1597 UASM_i_SRA(&p, a1, a0, 29); 1598 UASM_i_ADDIU(&p, a1, a1, 4); 1599 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); 1600 uasm_i_nop(&p); 1601 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); 1602 uasm_l_tlbl_goaround1(&l, p); 1603 UASM_i_SLL(&p, a0, a0, 11); 1604 uasm_i_jr(&p, 31); 1605 UASM_i_MTC0(&p, a0, C0_CONTEXT); 1606 } else { 1607 /* PGD in c0_KScratch */ 1608 uasm_i_jr(&p, 31); 1609 if (cpu_has_ldpte) 1610 UASM_i_MTC0(&p, a0, C0_PWBASE); 1611 else 1612 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1613 } 1614 #else 1615 #ifdef CONFIG_SMP 1616 /* Save PGD to pgd_current[smp_processor_id()] */ 1617 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); 1618 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); 1619 UASM_i_LA_mostly(&p, a2, pgdc); 1620 UASM_i_ADDU(&p, a2, a2, a1); 1621 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1622 #else 1623 UASM_i_LA_mostly(&p, a2, pgdc); 1624 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1625 #endif /* SMP */ 1626 uasm_i_jr(&p, 31); 1627 1628 /* if pgd_reg is allocated, save PGD also to scratch register */ 1629 if (pgd_reg != -1) 1630 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1631 else 1632 uasm_i_nop(&p); 1633 #endif 1634 if (p >= (u32 *)tlbmiss_handler_setup_pgd_end) 1635 panic("tlbmiss_handler_setup_pgd space exceeded"); 1636 1637 uasm_resolve_relocs(relocs, labels); 1638 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", 1639 (unsigned int)(p - (u32 *)tlbmiss_handler_setup_pgd)); 1640 1641 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, 1642 tlbmiss_handler_setup_pgd_end); 1643 } 1644 1645 static void 1646 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) 1647 { 1648 #ifdef CONFIG_SMP 1649 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1650 if (cpu_has_64bits) 1651 uasm_i_lld(p, pte, 0, ptr); 1652 else 1653 # endif 1654 UASM_i_LL(p, pte, 0, ptr); 1655 #else 1656 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1657 if (cpu_has_64bits) 1658 uasm_i_ld(p, pte, 0, ptr); 1659 else 1660 # endif 1661 UASM_i_LW(p, pte, 0, ptr); 1662 #endif 1663 } 1664 1665 static void 1666 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, 1667 unsigned int mode, unsigned int scratch) 1668 { 1669 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1670 unsigned int swmode = mode & ~hwmode; 1671 1672 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) { 1673 uasm_i_lui(p, scratch, swmode >> 16); 1674 uasm_i_or(p, pte, pte, scratch); 1675 BUG_ON(swmode & 0xffff); 1676 } else { 1677 uasm_i_ori(p, pte, pte, mode); 1678 } 1679 1680 #ifdef CONFIG_SMP 1681 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1682 if (cpu_has_64bits) 1683 uasm_i_scd(p, pte, 0, ptr); 1684 else 1685 # endif 1686 UASM_i_SC(p, pte, 0, ptr); 1687 1688 if (r10000_llsc_war()) 1689 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); 1690 else 1691 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1692 1693 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1694 if (!cpu_has_64bits) { 1695 /* no uasm_i_nop needed */ 1696 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1697 uasm_i_ori(p, pte, pte, hwmode); 1698 BUG_ON(hwmode & ~0xffff); 1699 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1700 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1701 /* no uasm_i_nop needed */ 1702 uasm_i_lw(p, pte, 0, ptr); 1703 } else 1704 uasm_i_nop(p); 1705 # else 1706 uasm_i_nop(p); 1707 # endif 1708 #else 1709 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1710 if (cpu_has_64bits) 1711 uasm_i_sd(p, pte, 0, ptr); 1712 else 1713 # endif 1714 UASM_i_SW(p, pte, 0, ptr); 1715 1716 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1717 if (!cpu_has_64bits) { 1718 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1719 uasm_i_ori(p, pte, pte, hwmode); 1720 BUG_ON(hwmode & ~0xffff); 1721 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1722 uasm_i_lw(p, pte, 0, ptr); 1723 } 1724 # endif 1725 #endif 1726 } 1727 1728 /* 1729 * Check if PTE is present, if not then jump to LABEL. PTR points to 1730 * the page table where this PTE is located, PTE will be re-loaded 1731 * with it's original value. 1732 */ 1733 static void 1734 build_pte_present(u32 **p, struct uasm_reloc **r, 1735 int pte, int ptr, int scratch, enum label_id lid) 1736 { 1737 int t = scratch >= 0 ? scratch : pte; 1738 int cur = pte; 1739 1740 if (cpu_has_rixi) { 1741 if (use_bbit_insns()) { 1742 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); 1743 uasm_i_nop(p); 1744 } else { 1745 if (_PAGE_PRESENT_SHIFT) { 1746 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1747 cur = t; 1748 } 1749 uasm_i_andi(p, t, cur, 1); 1750 uasm_il_beqz(p, r, t, lid); 1751 if (pte == t) 1752 /* You lose the SMP race :-(*/ 1753 iPTE_LW(p, pte, ptr); 1754 } 1755 } else { 1756 if (_PAGE_PRESENT_SHIFT) { 1757 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1758 cur = t; 1759 } 1760 uasm_i_andi(p, t, cur, 1761 (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT); 1762 uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT); 1763 uasm_il_bnez(p, r, t, lid); 1764 if (pte == t) 1765 /* You lose the SMP race :-(*/ 1766 iPTE_LW(p, pte, ptr); 1767 } 1768 } 1769 1770 /* Make PTE valid, store result in PTR. */ 1771 static void 1772 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, 1773 unsigned int ptr, unsigned int scratch) 1774 { 1775 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 1776 1777 iPTE_SW(p, r, pte, ptr, mode, scratch); 1778 } 1779 1780 /* 1781 * Check if PTE can be written to, if not branch to LABEL. Regardless 1782 * restore PTE with value from PTR when done. 1783 */ 1784 static void 1785 build_pte_writable(u32 **p, struct uasm_reloc **r, 1786 unsigned int pte, unsigned int ptr, int scratch, 1787 enum label_id lid) 1788 { 1789 int t = scratch >= 0 ? scratch : pte; 1790 int cur = pte; 1791 1792 if (_PAGE_PRESENT_SHIFT) { 1793 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1794 cur = t; 1795 } 1796 uasm_i_andi(p, t, cur, 1797 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1798 uasm_i_xori(p, t, t, 1799 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1800 uasm_il_bnez(p, r, t, lid); 1801 if (pte == t) 1802 /* You lose the SMP race :-(*/ 1803 iPTE_LW(p, pte, ptr); 1804 else 1805 uasm_i_nop(p); 1806 } 1807 1808 /* Make PTE writable, update software status bits as well, then store 1809 * at PTR. 1810 */ 1811 static void 1812 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, 1813 unsigned int ptr, unsigned int scratch) 1814 { 1815 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 1816 | _PAGE_DIRTY); 1817 1818 iPTE_SW(p, r, pte, ptr, mode, scratch); 1819 } 1820 1821 /* 1822 * Check if PTE can be modified, if not branch to LABEL. Regardless 1823 * restore PTE with value from PTR when done. 1824 */ 1825 static void 1826 build_pte_modifiable(u32 **p, struct uasm_reloc **r, 1827 unsigned int pte, unsigned int ptr, int scratch, 1828 enum label_id lid) 1829 { 1830 if (use_bbit_insns()) { 1831 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); 1832 uasm_i_nop(p); 1833 } else { 1834 int t = scratch >= 0 ? scratch : pte; 1835 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT); 1836 uasm_i_andi(p, t, t, 1); 1837 uasm_il_beqz(p, r, t, lid); 1838 if (pte == t) 1839 /* You lose the SMP race :-(*/ 1840 iPTE_LW(p, pte, ptr); 1841 } 1842 } 1843 1844 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1845 1846 1847 /* 1848 * R3000 style TLB load/store/modify handlers. 1849 */ 1850 1851 /* 1852 * This places the pte into ENTRYLO0 and writes it with tlbwi. 1853 * Then it returns. 1854 */ 1855 static void 1856 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 1857 { 1858 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1859 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 1860 uasm_i_tlbwi(p); 1861 uasm_i_jr(p, tmp); 1862 uasm_i_rfe(p); /* branch delay */ 1863 } 1864 1865 /* 1866 * This places the pte into ENTRYLO0 and writes it with tlbwi 1867 * or tlbwr as appropriate. This is because the index register 1868 * may have the probe fail bit set as a result of a trap on a 1869 * kseg2 access, i.e. without refill. Then it returns. 1870 */ 1871 static void 1872 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, 1873 struct uasm_reloc **r, unsigned int pte, 1874 unsigned int tmp) 1875 { 1876 uasm_i_mfc0(p, tmp, C0_INDEX); 1877 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1878 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 1879 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ 1880 uasm_i_tlbwi(p); /* cp0 delay */ 1881 uasm_i_jr(p, tmp); 1882 uasm_i_rfe(p); /* branch delay */ 1883 uasm_l_r3000_write_probe_fail(l, *p); 1884 uasm_i_tlbwr(p); /* cp0 delay */ 1885 uasm_i_jr(p, tmp); 1886 uasm_i_rfe(p); /* branch delay */ 1887 } 1888 1889 static void 1890 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1891 unsigned int ptr) 1892 { 1893 long pgdc = (long)pgd_current; 1894 1895 uasm_i_mfc0(p, pte, C0_BADVADDR); 1896 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ 1897 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 1898 uasm_i_srl(p, pte, pte, 22); /* load delay */ 1899 uasm_i_sll(p, pte, pte, 2); 1900 uasm_i_addu(p, ptr, ptr, pte); 1901 uasm_i_mfc0(p, pte, C0_CONTEXT); 1902 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ 1903 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ 1904 uasm_i_addu(p, ptr, ptr, pte); 1905 uasm_i_lw(p, pte, 0, ptr); 1906 uasm_i_tlbp(p); /* load delay */ 1907 } 1908 1909 static void build_r3000_tlb_load_handler(void) 1910 { 1911 u32 *p = (u32 *)handle_tlbl; 1912 struct uasm_label *l = labels; 1913 struct uasm_reloc *r = relocs; 1914 1915 memset(p, 0, handle_tlbl_end - (char *)p); 1916 memset(labels, 0, sizeof(labels)); 1917 memset(relocs, 0, sizeof(relocs)); 1918 1919 build_r3000_tlbchange_handler_head(&p, K0, K1); 1920 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); 1921 uasm_i_nop(&p); /* load delay */ 1922 build_make_valid(&p, &r, K0, K1, -1); 1923 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1924 1925 uasm_l_nopage_tlbl(&l, p); 1926 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1927 uasm_i_nop(&p); 1928 1929 if (p >= (u32 *)handle_tlbl_end) 1930 panic("TLB load handler fastpath space exceeded"); 1931 1932 uasm_resolve_relocs(relocs, labels); 1933 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1934 (unsigned int)(p - (u32 *)handle_tlbl)); 1935 1936 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_end); 1937 } 1938 1939 static void build_r3000_tlb_store_handler(void) 1940 { 1941 u32 *p = (u32 *)handle_tlbs; 1942 struct uasm_label *l = labels; 1943 struct uasm_reloc *r = relocs; 1944 1945 memset(p, 0, handle_tlbs_end - (char *)p); 1946 memset(labels, 0, sizeof(labels)); 1947 memset(relocs, 0, sizeof(relocs)); 1948 1949 build_r3000_tlbchange_handler_head(&p, K0, K1); 1950 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); 1951 uasm_i_nop(&p); /* load delay */ 1952 build_make_write(&p, &r, K0, K1, -1); 1953 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1954 1955 uasm_l_nopage_tlbs(&l, p); 1956 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1957 uasm_i_nop(&p); 1958 1959 if (p >= (u32 *)handle_tlbs_end) 1960 panic("TLB store handler fastpath space exceeded"); 1961 1962 uasm_resolve_relocs(relocs, labels); 1963 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1964 (unsigned int)(p - (u32 *)handle_tlbs)); 1965 1966 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_end); 1967 } 1968 1969 static void build_r3000_tlb_modify_handler(void) 1970 { 1971 u32 *p = (u32 *)handle_tlbm; 1972 struct uasm_label *l = labels; 1973 struct uasm_reloc *r = relocs; 1974 1975 memset(p, 0, handle_tlbm_end - (char *)p); 1976 memset(labels, 0, sizeof(labels)); 1977 memset(relocs, 0, sizeof(relocs)); 1978 1979 build_r3000_tlbchange_handler_head(&p, K0, K1); 1980 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); 1981 uasm_i_nop(&p); /* load delay */ 1982 build_make_write(&p, &r, K0, K1, -1); 1983 build_r3000_pte_reload_tlbwi(&p, K0, K1); 1984 1985 uasm_l_nopage_tlbm(&l, p); 1986 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1987 uasm_i_nop(&p); 1988 1989 if (p >= (u32 *)handle_tlbm_end) 1990 panic("TLB modify handler fastpath space exceeded"); 1991 1992 uasm_resolve_relocs(relocs, labels); 1993 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 1994 (unsigned int)(p - (u32 *)handle_tlbm)); 1995 1996 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_end); 1997 } 1998 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 1999 2000 static bool cpu_has_tlbex_tlbp_race(void) 2001 { 2002 /* 2003 * When a Hardware Table Walker is running it can replace TLB entries 2004 * at any time, leading to a race between it & the CPU. 2005 */ 2006 if (cpu_has_htw) 2007 return true; 2008 2009 /* 2010 * If the CPU shares FTLB RAM with its siblings then our entry may be 2011 * replaced at any time by a sibling performing a write to the FTLB. 2012 */ 2013 if (cpu_has_shared_ftlb_ram) 2014 return true; 2015 2016 /* In all other cases there ought to be no race condition to handle */ 2017 return false; 2018 } 2019 2020 /* 2021 * R4000 style TLB load/store/modify handlers. 2022 */ 2023 static struct work_registers 2024 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, 2025 struct uasm_reloc **r) 2026 { 2027 struct work_registers wr = build_get_work_registers(p); 2028 2029 #ifdef CONFIG_64BIT 2030 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ 2031 #else 2032 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ 2033 #endif 2034 2035 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2036 /* 2037 * For huge tlb entries, pmd doesn't contain an address but 2038 * instead contains the tlb pte. Check the PAGE_HUGE bit and 2039 * see if we need to jump to huge tlb processing. 2040 */ 2041 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); 2042 #endif 2043 2044 UASM_i_MFC0(p, wr.r1, C0_BADVADDR); 2045 UASM_i_LW(p, wr.r2, 0, wr.r2); 2046 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 2047 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 2048 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); 2049 2050 #ifdef CONFIG_SMP 2051 uasm_l_smp_pgtable_change(l, *p); 2052 #endif 2053 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ 2054 if (!m4kc_tlbp_war()) { 2055 build_tlb_probe_entry(p); 2056 if (cpu_has_tlbex_tlbp_race()) { 2057 /* race condition happens, leaving */ 2058 uasm_i_ehb(p); 2059 uasm_i_mfc0(p, wr.r3, C0_INDEX); 2060 uasm_il_bltz(p, r, wr.r3, label_leave); 2061 uasm_i_nop(p); 2062 } 2063 } 2064 return wr; 2065 } 2066 2067 static void 2068 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, 2069 struct uasm_reloc **r, unsigned int tmp, 2070 unsigned int ptr) 2071 { 2072 uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); 2073 uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); 2074 build_update_entries(p, tmp, ptr); 2075 build_tlb_write_entry(p, l, r, tlb_indexed); 2076 uasm_l_leave(l, *p); 2077 build_restore_work_registers(p); 2078 uasm_i_eret(p); /* return from trap */ 2079 2080 #ifdef CONFIG_64BIT 2081 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); 2082 #endif 2083 } 2084 2085 static void build_r4000_tlb_load_handler(void) 2086 { 2087 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl); 2088 struct uasm_label *l = labels; 2089 struct uasm_reloc *r = relocs; 2090 struct work_registers wr; 2091 2092 memset(p, 0, handle_tlbl_end - (char *)p); 2093 memset(labels, 0, sizeof(labels)); 2094 memset(relocs, 0, sizeof(relocs)); 2095 2096 if (bcm1250_m3_war()) { 2097 unsigned int segbits = 44; 2098 2099 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 2100 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 2101 uasm_i_xor(&p, K0, K0, K1); 2102 uasm_i_dsrl_safe(&p, K1, K0, 62); 2103 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 2104 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 2105 uasm_i_or(&p, K0, K0, K1); 2106 uasm_il_bnez(&p, &r, K0, label_leave); 2107 /* No need for uasm_i_nop */ 2108 } 2109 2110 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2111 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2112 if (m4kc_tlbp_war()) 2113 build_tlb_probe_entry(&p); 2114 2115 if (cpu_has_rixi && !cpu_has_rixiex) { 2116 /* 2117 * If the page is not _PAGE_VALID, RI or XI could not 2118 * have triggered it. Skip the expensive test.. 2119 */ 2120 if (use_bbit_insns()) { 2121 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2122 label_tlbl_goaround1); 2123 } else { 2124 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2125 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); 2126 } 2127 uasm_i_nop(&p); 2128 2129 /* 2130 * Warn if something may race with us & replace the TLB entry 2131 * before we read it here. Everything with such races should 2132 * also have dedicated RiXi exception handlers, so this 2133 * shouldn't be hit. 2134 */ 2135 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path"); 2136 2137 uasm_i_tlbr(&p); 2138 2139 switch (current_cpu_type()) { 2140 default: 2141 if (cpu_has_mips_r2_exec_hazard) { 2142 uasm_i_ehb(&p); 2143 2144 case CPU_CAVIUM_OCTEON: 2145 case CPU_CAVIUM_OCTEON_PLUS: 2146 case CPU_CAVIUM_OCTEON2: 2147 break; 2148 } 2149 } 2150 2151 /* Examine entrylo 0 or 1 based on ptr. */ 2152 if (use_bbit_insns()) { 2153 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2154 } else { 2155 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2156 uasm_i_beqz(&p, wr.r3, 8); 2157 } 2158 /* load it in the delay slot*/ 2159 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2160 /* load it if ptr is odd */ 2161 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2162 /* 2163 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2164 * XI must have triggered it. 2165 */ 2166 if (use_bbit_insns()) { 2167 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); 2168 uasm_i_nop(&p); 2169 uasm_l_tlbl_goaround1(&l, p); 2170 } else { 2171 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2172 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); 2173 uasm_i_nop(&p); 2174 } 2175 uasm_l_tlbl_goaround1(&l, p); 2176 } 2177 build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3); 2178 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2179 2180 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2181 /* 2182 * This is the entry point when build_r4000_tlbchange_handler_head 2183 * spots a huge page. 2184 */ 2185 uasm_l_tlb_huge_update(&l, p); 2186 iPTE_LW(&p, wr.r1, wr.r2); 2187 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2188 build_tlb_probe_entry(&p); 2189 2190 if (cpu_has_rixi && !cpu_has_rixiex) { 2191 /* 2192 * If the page is not _PAGE_VALID, RI or XI could not 2193 * have triggered it. Skip the expensive test.. 2194 */ 2195 if (use_bbit_insns()) { 2196 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2197 label_tlbl_goaround2); 2198 } else { 2199 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2200 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2201 } 2202 uasm_i_nop(&p); 2203 2204 /* 2205 * Warn if something may race with us & replace the TLB entry 2206 * before we read it here. Everything with such races should 2207 * also have dedicated RiXi exception handlers, so this 2208 * shouldn't be hit. 2209 */ 2210 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path"); 2211 2212 uasm_i_tlbr(&p); 2213 2214 switch (current_cpu_type()) { 2215 default: 2216 if (cpu_has_mips_r2_exec_hazard) { 2217 uasm_i_ehb(&p); 2218 2219 case CPU_CAVIUM_OCTEON: 2220 case CPU_CAVIUM_OCTEON_PLUS: 2221 case CPU_CAVIUM_OCTEON2: 2222 break; 2223 } 2224 } 2225 2226 /* Examine entrylo 0 or 1 based on ptr. */ 2227 if (use_bbit_insns()) { 2228 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2229 } else { 2230 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2231 uasm_i_beqz(&p, wr.r3, 8); 2232 } 2233 /* load it in the delay slot*/ 2234 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2235 /* load it if ptr is odd */ 2236 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2237 /* 2238 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2239 * XI must have triggered it. 2240 */ 2241 if (use_bbit_insns()) { 2242 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); 2243 } else { 2244 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2245 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2246 } 2247 if (PM_DEFAULT_MASK == 0) 2248 uasm_i_nop(&p); 2249 /* 2250 * We clobbered C0_PAGEMASK, restore it. On the other branch 2251 * it is restored in build_huge_tlb_write_entry. 2252 */ 2253 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); 2254 2255 uasm_l_tlbl_goaround2(&l, p); 2256 } 2257 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); 2258 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); 2259 #endif 2260 2261 uasm_l_nopage_tlbl(&l, p); 2262 build_restore_work_registers(&p); 2263 #ifdef CONFIG_CPU_MICROMIPS 2264 if ((unsigned long)tlb_do_page_fault_0 & 1) { 2265 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); 2266 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); 2267 uasm_i_jr(&p, K0); 2268 } else 2269 #endif 2270 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 2271 uasm_i_nop(&p); 2272 2273 if (p >= (u32 *)handle_tlbl_end) 2274 panic("TLB load handler fastpath space exceeded"); 2275 2276 uasm_resolve_relocs(relocs, labels); 2277 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 2278 (unsigned int)(p - (u32 *)handle_tlbl)); 2279 2280 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_end); 2281 } 2282 2283 static void build_r4000_tlb_store_handler(void) 2284 { 2285 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs); 2286 struct uasm_label *l = labels; 2287 struct uasm_reloc *r = relocs; 2288 struct work_registers wr; 2289 2290 memset(p, 0, handle_tlbs_end - (char *)p); 2291 memset(labels, 0, sizeof(labels)); 2292 memset(relocs, 0, sizeof(relocs)); 2293 2294 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2295 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2296 if (m4kc_tlbp_war()) 2297 build_tlb_probe_entry(&p); 2298 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); 2299 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2300 2301 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2302 /* 2303 * This is the entry point when 2304 * build_r4000_tlbchange_handler_head spots a huge page. 2305 */ 2306 uasm_l_tlb_huge_update(&l, p); 2307 iPTE_LW(&p, wr.r1, wr.r2); 2308 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2309 build_tlb_probe_entry(&p); 2310 uasm_i_ori(&p, wr.r1, wr.r1, 2311 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2312 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); 2313 #endif 2314 2315 uasm_l_nopage_tlbs(&l, p); 2316 build_restore_work_registers(&p); 2317 #ifdef CONFIG_CPU_MICROMIPS 2318 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2319 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2320 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2321 uasm_i_jr(&p, K0); 2322 } else 2323 #endif 2324 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2325 uasm_i_nop(&p); 2326 2327 if (p >= (u32 *)handle_tlbs_end) 2328 panic("TLB store handler fastpath space exceeded"); 2329 2330 uasm_resolve_relocs(relocs, labels); 2331 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 2332 (unsigned int)(p - (u32 *)handle_tlbs)); 2333 2334 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_end); 2335 } 2336 2337 static void build_r4000_tlb_modify_handler(void) 2338 { 2339 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm); 2340 struct uasm_label *l = labels; 2341 struct uasm_reloc *r = relocs; 2342 struct work_registers wr; 2343 2344 memset(p, 0, handle_tlbm_end - (char *)p); 2345 memset(labels, 0, sizeof(labels)); 2346 memset(relocs, 0, sizeof(relocs)); 2347 2348 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2349 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2350 if (m4kc_tlbp_war()) 2351 build_tlb_probe_entry(&p); 2352 /* Present and writable bits set, set accessed and dirty bits. */ 2353 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); 2354 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2355 2356 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2357 /* 2358 * This is the entry point when 2359 * build_r4000_tlbchange_handler_head spots a huge page. 2360 */ 2361 uasm_l_tlb_huge_update(&l, p); 2362 iPTE_LW(&p, wr.r1, wr.r2); 2363 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2364 build_tlb_probe_entry(&p); 2365 uasm_i_ori(&p, wr.r1, wr.r1, 2366 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2367 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0); 2368 #endif 2369 2370 uasm_l_nopage_tlbm(&l, p); 2371 build_restore_work_registers(&p); 2372 #ifdef CONFIG_CPU_MICROMIPS 2373 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2374 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2375 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2376 uasm_i_jr(&p, K0); 2377 } else 2378 #endif 2379 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2380 uasm_i_nop(&p); 2381 2382 if (p >= (u32 *)handle_tlbm_end) 2383 panic("TLB modify handler fastpath space exceeded"); 2384 2385 uasm_resolve_relocs(relocs, labels); 2386 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2387 (unsigned int)(p - (u32 *)handle_tlbm)); 2388 2389 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_end); 2390 } 2391 2392 static void flush_tlb_handlers(void) 2393 { 2394 local_flush_icache_range((unsigned long)handle_tlbl, 2395 (unsigned long)handle_tlbl_end); 2396 local_flush_icache_range((unsigned long)handle_tlbs, 2397 (unsigned long)handle_tlbs_end); 2398 local_flush_icache_range((unsigned long)handle_tlbm, 2399 (unsigned long)handle_tlbm_end); 2400 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, 2401 (unsigned long)tlbmiss_handler_setup_pgd_end); 2402 } 2403 2404 static void print_htw_config(void) 2405 { 2406 unsigned long config; 2407 unsigned int pwctl; 2408 const int field = 2 * sizeof(unsigned long); 2409 2410 config = read_c0_pwfield(); 2411 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n", 2412 field, config, 2413 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT, 2414 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT, 2415 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT, 2416 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT, 2417 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); 2418 2419 config = read_c0_pwsize(); 2420 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", 2421 field, config, 2422 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT, 2423 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, 2424 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, 2425 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, 2426 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT, 2427 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); 2428 2429 pwctl = read_c0_pwctl(); 2430 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", 2431 pwctl, 2432 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, 2433 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT, 2434 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT, 2435 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT, 2436 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, 2437 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, 2438 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); 2439 } 2440 2441 static void config_htw_params(void) 2442 { 2443 unsigned long pwfield, pwsize, ptei; 2444 unsigned int config; 2445 2446 /* 2447 * We are using 2-level page tables, so we only need to 2448 * setup GDW and PTW appropriately. UDW and MDW will remain 0. 2449 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to 2450 * write values less than 0xc in these fields because the entire 2451 * write will be dropped. As a result of which, we must preserve 2452 * the original reset values and overwrite only what we really want. 2453 */ 2454 2455 pwfield = read_c0_pwfield(); 2456 /* re-initialize the GDI field */ 2457 pwfield &= ~MIPS_PWFIELD_GDI_MASK; 2458 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT; 2459 /* re-initialize the PTI field including the even/odd bit */ 2460 pwfield &= ~MIPS_PWFIELD_PTI_MASK; 2461 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT; 2462 if (CONFIG_PGTABLE_LEVELS >= 3) { 2463 pwfield &= ~MIPS_PWFIELD_MDI_MASK; 2464 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT; 2465 } 2466 /* Set the PTEI right shift */ 2467 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT; 2468 pwfield |= ptei; 2469 write_c0_pwfield(pwfield); 2470 /* Check whether the PTEI value is supported */ 2471 back_to_back_c0_hazard(); 2472 pwfield = read_c0_pwfield(); 2473 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT) 2474 != ptei) { 2475 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled", 2476 ptei); 2477 /* 2478 * Drop option to avoid HTW being enabled via another path 2479 * (eg htw_reset()) 2480 */ 2481 current_cpu_data.options &= ~MIPS_CPU_HTW; 2482 return; 2483 } 2484 2485 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; 2486 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; 2487 if (CONFIG_PGTABLE_LEVELS >= 3) 2488 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; 2489 2490 /* Set pointer size to size of directory pointers */ 2491 if (IS_ENABLED(CONFIG_64BIT)) 2492 pwsize |= MIPS_PWSIZE_PS_MASK; 2493 /* PTEs may be multiple pointers long (e.g. with XPA) */ 2494 pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT) 2495 & MIPS_PWSIZE_PTEW_MASK; 2496 2497 write_c0_pwsize(pwsize); 2498 2499 /* Make sure everything is set before we enable the HTW */ 2500 back_to_back_c0_hazard(); 2501 2502 /* 2503 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of 2504 * the pwctl fields. 2505 */ 2506 config = 1 << MIPS_PWCTL_PWEN_SHIFT; 2507 if (IS_ENABLED(CONFIG_64BIT)) 2508 config |= MIPS_PWCTL_XU_MASK; 2509 write_c0_pwctl(config); 2510 pr_info("Hardware Page Table Walker enabled\n"); 2511 2512 print_htw_config(); 2513 } 2514 2515 static void config_xpa_params(void) 2516 { 2517 #ifdef CONFIG_XPA 2518 unsigned int pagegrain; 2519 2520 if (mips_xpa_disabled) { 2521 pr_info("Extended Physical Addressing (XPA) disabled\n"); 2522 return; 2523 } 2524 2525 pagegrain = read_c0_pagegrain(); 2526 write_c0_pagegrain(pagegrain | PG_ELPA); 2527 back_to_back_c0_hazard(); 2528 pagegrain = read_c0_pagegrain(); 2529 2530 if (pagegrain & PG_ELPA) 2531 pr_info("Extended Physical Addressing (XPA) enabled\n"); 2532 else 2533 panic("Extended Physical Addressing (XPA) disabled"); 2534 #endif 2535 } 2536 2537 static void check_pabits(void) 2538 { 2539 unsigned long entry; 2540 unsigned pabits, fillbits; 2541 2542 if (!cpu_has_rixi || !_PAGE_NO_EXEC) { 2543 /* 2544 * We'll only be making use of the fact that we can rotate bits 2545 * into the fill if the CPU supports RIXI, so don't bother 2546 * probing this for CPUs which don't. 2547 */ 2548 return; 2549 } 2550 2551 write_c0_entrylo0(~0ul); 2552 back_to_back_c0_hazard(); 2553 entry = read_c0_entrylo0(); 2554 2555 /* clear all non-PFN bits */ 2556 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1); 2557 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); 2558 2559 /* find a lower bound on PABITS, and upper bound on fill bits */ 2560 pabits = fls_long(entry) + 6; 2561 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0); 2562 2563 /* minus the RI & XI bits */ 2564 fillbits -= min_t(unsigned, fillbits, 2); 2565 2566 if (fillbits >= ilog2(_PAGE_NO_EXEC)) 2567 fill_includes_sw_bits = true; 2568 2569 pr_debug("Entry* registers contain %u fill bits\n", fillbits); 2570 } 2571 2572 void build_tlb_refill_handler(void) 2573 { 2574 /* 2575 * The refill handler is generated per-CPU, multi-node systems 2576 * may have local storage for it. The other handlers are only 2577 * needed once. 2578 */ 2579 static int run_once = 0; 2580 2581 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi) 2582 panic("Kernels supporting XPA currently require CPUs with RIXI"); 2583 2584 output_pgtable_bits_defines(); 2585 check_pabits(); 2586 2587 #ifdef CONFIG_64BIT 2588 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 2589 #endif 2590 2591 switch (current_cpu_type()) { 2592 case CPU_R2000: 2593 case CPU_R3000: 2594 case CPU_R3000A: 2595 case CPU_R3081E: 2596 case CPU_TX3912: 2597 case CPU_TX3922: 2598 case CPU_TX3927: 2599 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 2600 if (cpu_has_local_ebase) 2601 build_r3000_tlb_refill_handler(); 2602 if (!run_once) { 2603 if (!cpu_has_local_ebase) 2604 build_r3000_tlb_refill_handler(); 2605 build_setup_pgd(); 2606 build_r3000_tlb_load_handler(); 2607 build_r3000_tlb_store_handler(); 2608 build_r3000_tlb_modify_handler(); 2609 flush_tlb_handlers(); 2610 run_once++; 2611 } 2612 #else 2613 panic("No R3000 TLB refill handler"); 2614 #endif 2615 break; 2616 2617 case CPU_R8000: 2618 panic("No R8000 TLB refill handler yet"); 2619 break; 2620 2621 default: 2622 if (cpu_has_ldpte) 2623 setup_pw(); 2624 2625 if (!run_once) { 2626 scratch_reg = allocate_kscratch(); 2627 build_setup_pgd(); 2628 build_r4000_tlb_load_handler(); 2629 build_r4000_tlb_store_handler(); 2630 build_r4000_tlb_modify_handler(); 2631 if (cpu_has_ldpte) 2632 build_loongson3_tlb_refill_handler(); 2633 else if (!cpu_has_local_ebase) 2634 build_r4000_tlb_refill_handler(); 2635 flush_tlb_handlers(); 2636 run_once++; 2637 } 2638 if (cpu_has_local_ebase) 2639 build_r4000_tlb_refill_handler(); 2640 if (cpu_has_xpa) 2641 config_xpa_params(); 2642 if (cpu_has_htw) 2643 config_htw_params(); 2644 } 2645 } 2646