1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004,2005 by Thiemo Seufer 9 * Copyright (C) 2005 Maciej W. Rozycki 10 */ 11 12 #include <stdarg.h> 13 14 #include <linux/config.h> 15 #include <linux/mm.h> 16 #include <linux/kernel.h> 17 #include <linux/types.h> 18 #include <linux/string.h> 19 #include <linux/init.h> 20 21 #include <asm/pgtable.h> 22 #include <asm/cacheflush.h> 23 #include <asm/mmu_context.h> 24 #include <asm/inst.h> 25 #include <asm/elf.h> 26 #include <asm/smp.h> 27 #include <asm/war.h> 28 29 /* #define DEBUG_TLB */ 30 31 static __init int __attribute__((unused)) r45k_bvahwbug(void) 32 { 33 /* XXX: We should probe for the presence of this bug, but we don't. */ 34 return 0; 35 } 36 37 static __init int __attribute__((unused)) r4k_250MHZhwbug(void) 38 { 39 /* XXX: We should probe for the presence of this bug, but we don't. */ 40 return 0; 41 } 42 43 static __init int __attribute__((unused)) bcm1250_m3_war(void) 44 { 45 return BCM1250_M3_WAR; 46 } 47 48 static __init int __attribute__((unused)) r10000_llsc_war(void) 49 { 50 return R10000_LLSC_WAR; 51 } 52 53 /* 54 * A little micro-assembler, intended for TLB refill handler 55 * synthesizing. It is intentionally kept simple, does only support 56 * a subset of instructions, and does not try to hide pipeline effects 57 * like branch delay slots. 58 */ 59 60 enum fields 61 { 62 RS = 0x001, 63 RT = 0x002, 64 RD = 0x004, 65 RE = 0x008, 66 SIMM = 0x010, 67 UIMM = 0x020, 68 BIMM = 0x040, 69 JIMM = 0x080, 70 FUNC = 0x100, 71 }; 72 73 #define OP_MASK 0x2f 74 #define OP_SH 26 75 #define RS_MASK 0x1f 76 #define RS_SH 21 77 #define RT_MASK 0x1f 78 #define RT_SH 16 79 #define RD_MASK 0x1f 80 #define RD_SH 11 81 #define RE_MASK 0x1f 82 #define RE_SH 6 83 #define IMM_MASK 0xffff 84 #define IMM_SH 0 85 #define JIMM_MASK 0x3ffffff 86 #define JIMM_SH 0 87 #define FUNC_MASK 0x2f 88 #define FUNC_SH 0 89 90 enum opcode { 91 insn_invalid, 92 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, 93 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 94 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, 95 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, 96 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, 97 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, 98 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, 99 insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi, 100 insn_tlbwr, insn_xor, insn_xori 101 }; 102 103 struct insn { 104 enum opcode opcode; 105 u32 match; 106 enum fields fields; 107 }; 108 109 /* This macro sets the non-variable bits of an instruction. */ 110 #define M(a, b, c, d, e, f) \ 111 ((a) << OP_SH \ 112 | (b) << RS_SH \ 113 | (c) << RT_SH \ 114 | (d) << RD_SH \ 115 | (e) << RE_SH \ 116 | (f) << FUNC_SH) 117 118 static __initdata struct insn insn_table[] = { 119 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM }, 120 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD }, 121 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD }, 122 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM }, 123 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM }, 124 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM }, 125 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM }, 126 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM }, 127 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM }, 128 { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM }, 129 { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM }, 130 { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM }, 131 { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD }, 132 { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD }, 133 { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD }, 134 { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE }, 135 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, 136 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, 137 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, 138 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, 139 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, 140 { insn_j, M(j_op,0,0,0,0,0), JIMM }, 141 { insn_jal, M(jal_op,0,0,0,0,0), JIMM }, 142 { insn_jr, M(spec_op,0,0,0,0,jr_op), RS }, 143 { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM }, 144 { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM }, 145 { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM }, 146 { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM }, 147 { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM }, 148 { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD }, 149 { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD }, 150 { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM }, 151 { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 }, 152 { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM }, 153 { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM }, 154 { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM }, 155 { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE }, 156 { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE }, 157 { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE }, 158 { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD }, 159 { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM }, 160 { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 }, 161 { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 }, 162 { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 }, 163 { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD }, 164 { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM }, 165 { insn_invalid, 0, 0 } 166 }; 167 168 #undef M 169 170 static __init u32 build_rs(u32 arg) 171 { 172 if (arg & ~RS_MASK) 173 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 174 175 return (arg & RS_MASK) << RS_SH; 176 } 177 178 static __init u32 build_rt(u32 arg) 179 { 180 if (arg & ~RT_MASK) 181 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 182 183 return (arg & RT_MASK) << RT_SH; 184 } 185 186 static __init u32 build_rd(u32 arg) 187 { 188 if (arg & ~RD_MASK) 189 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 190 191 return (arg & RD_MASK) << RD_SH; 192 } 193 194 static __init u32 build_re(u32 arg) 195 { 196 if (arg & ~RE_MASK) 197 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 198 199 return (arg & RE_MASK) << RE_SH; 200 } 201 202 static __init u32 build_simm(s32 arg) 203 { 204 if (arg > 0x7fff || arg < -0x8000) 205 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 206 207 return arg & 0xffff; 208 } 209 210 static __init u32 build_uimm(u32 arg) 211 { 212 if (arg & ~IMM_MASK) 213 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 214 215 return arg & IMM_MASK; 216 } 217 218 static __init u32 build_bimm(s32 arg) 219 { 220 if (arg > 0x1ffff || arg < -0x20000) 221 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 222 223 if (arg & 0x3) 224 printk(KERN_WARNING "Invalid TLB synthesizer branch target\n"); 225 226 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); 227 } 228 229 static __init u32 build_jimm(u32 arg) 230 { 231 if (arg & ~((JIMM_MASK) << 2)) 232 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 233 234 return (arg >> 2) & JIMM_MASK; 235 } 236 237 static __init u32 build_func(u32 arg) 238 { 239 if (arg & ~FUNC_MASK) 240 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 241 242 return arg & FUNC_MASK; 243 } 244 245 /* 246 * The order of opcode arguments is implicitly left to right, 247 * starting with RS and ending with FUNC or IMM. 248 */ 249 static void __init build_insn(u32 **buf, enum opcode opc, ...) 250 { 251 struct insn *ip = NULL; 252 unsigned int i; 253 va_list ap; 254 u32 op; 255 256 for (i = 0; insn_table[i].opcode != insn_invalid; i++) 257 if (insn_table[i].opcode == opc) { 258 ip = &insn_table[i]; 259 break; 260 } 261 262 if (!ip) 263 panic("Unsupported TLB synthesizer instruction %d", opc); 264 265 op = ip->match; 266 va_start(ap, opc); 267 if (ip->fields & RS) op |= build_rs(va_arg(ap, u32)); 268 if (ip->fields & RT) op |= build_rt(va_arg(ap, u32)); 269 if (ip->fields & RD) op |= build_rd(va_arg(ap, u32)); 270 if (ip->fields & RE) op |= build_re(va_arg(ap, u32)); 271 if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32)); 272 if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32)); 273 if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32)); 274 if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32)); 275 if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32)); 276 va_end(ap); 277 278 **buf = op; 279 (*buf)++; 280 } 281 282 #define I_u1u2u3(op) \ 283 static inline void i##op(u32 **buf, unsigned int a, \ 284 unsigned int b, unsigned int c) \ 285 { \ 286 build_insn(buf, insn##op, a, b, c); \ 287 } 288 289 #define I_u2u1u3(op) \ 290 static inline void i##op(u32 **buf, unsigned int a, \ 291 unsigned int b, unsigned int c) \ 292 { \ 293 build_insn(buf, insn##op, b, a, c); \ 294 } 295 296 #define I_u3u1u2(op) \ 297 static inline void i##op(u32 **buf, unsigned int a, \ 298 unsigned int b, unsigned int c) \ 299 { \ 300 build_insn(buf, insn##op, b, c, a); \ 301 } 302 303 #define I_u1u2s3(op) \ 304 static inline void i##op(u32 **buf, unsigned int a, \ 305 unsigned int b, signed int c) \ 306 { \ 307 build_insn(buf, insn##op, a, b, c); \ 308 } 309 310 #define I_u2s3u1(op) \ 311 static inline void i##op(u32 **buf, unsigned int a, \ 312 signed int b, unsigned int c) \ 313 { \ 314 build_insn(buf, insn##op, c, a, b); \ 315 } 316 317 #define I_u2u1s3(op) \ 318 static inline void i##op(u32 **buf, unsigned int a, \ 319 unsigned int b, signed int c) \ 320 { \ 321 build_insn(buf, insn##op, b, a, c); \ 322 } 323 324 #define I_u1u2(op) \ 325 static inline void i##op(u32 **buf, unsigned int a, \ 326 unsigned int b) \ 327 { \ 328 build_insn(buf, insn##op, a, b); \ 329 } 330 331 #define I_u1s2(op) \ 332 static inline void i##op(u32 **buf, unsigned int a, \ 333 signed int b) \ 334 { \ 335 build_insn(buf, insn##op, a, b); \ 336 } 337 338 #define I_u1(op) \ 339 static inline void i##op(u32 **buf, unsigned int a) \ 340 { \ 341 build_insn(buf, insn##op, a); \ 342 } 343 344 #define I_0(op) \ 345 static inline void i##op(u32 **buf) \ 346 { \ 347 build_insn(buf, insn##op); \ 348 } 349 350 I_u2u1s3(_addiu); 351 I_u3u1u2(_addu); 352 I_u2u1u3(_andi); 353 I_u3u1u2(_and); 354 I_u1u2s3(_beq); 355 I_u1u2s3(_beql); 356 I_u1s2(_bgez); 357 I_u1s2(_bgezl); 358 I_u1s2(_bltz); 359 I_u1s2(_bltzl); 360 I_u1u2s3(_bne); 361 I_u1u2(_dmfc0); 362 I_u1u2(_dmtc0); 363 I_u2u1s3(_daddiu); 364 I_u3u1u2(_daddu); 365 I_u2u1u3(_dsll); 366 I_u2u1u3(_dsll32); 367 I_u2u1u3(_dsra); 368 I_u2u1u3(_dsrl); 369 I_u3u1u2(_dsubu); 370 I_0(_eret); 371 I_u1(_j); 372 I_u1(_jal); 373 I_u1(_jr); 374 I_u2s3u1(_ld); 375 I_u2s3u1(_ll); 376 I_u2s3u1(_lld); 377 I_u1s2(_lui); 378 I_u2s3u1(_lw); 379 I_u1u2(_mfc0); 380 I_u1u2(_mtc0); 381 I_u2u1u3(_ori); 382 I_0(_rfe); 383 I_u2s3u1(_sc); 384 I_u2s3u1(_scd); 385 I_u2s3u1(_sd); 386 I_u2u1u3(_sll); 387 I_u2u1u3(_sra); 388 I_u2u1u3(_srl); 389 I_u3u1u2(_subu); 390 I_u2s3u1(_sw); 391 I_0(_tlbp); 392 I_0(_tlbwi); 393 I_0(_tlbwr); 394 I_u3u1u2(_xor) 395 I_u2u1u3(_xori); 396 397 /* 398 * handling labels 399 */ 400 401 enum label_id { 402 label_invalid, 403 label_second_part, 404 label_leave, 405 label_vmalloc, 406 label_vmalloc_done, 407 label_tlbw_hazard, 408 label_split, 409 label_nopage_tlbl, 410 label_nopage_tlbs, 411 label_nopage_tlbm, 412 label_smp_pgtable_change, 413 label_r3000_write_probe_fail, 414 }; 415 416 struct label { 417 u32 *addr; 418 enum label_id lab; 419 }; 420 421 static __init void build_label(struct label **lab, u32 *addr, 422 enum label_id l) 423 { 424 (*lab)->addr = addr; 425 (*lab)->lab = l; 426 (*lab)++; 427 } 428 429 #define L_LA(lb) \ 430 static inline void l##lb(struct label **lab, u32 *addr) \ 431 { \ 432 build_label(lab, addr, label##lb); \ 433 } 434 435 L_LA(_second_part) 436 L_LA(_leave) 437 L_LA(_vmalloc) 438 L_LA(_vmalloc_done) 439 L_LA(_tlbw_hazard) 440 L_LA(_split) 441 L_LA(_nopage_tlbl) 442 L_LA(_nopage_tlbs) 443 L_LA(_nopage_tlbm) 444 L_LA(_smp_pgtable_change) 445 L_LA(_r3000_write_probe_fail) 446 447 /* convenience macros for instructions */ 448 #ifdef CONFIG_64BIT 449 # define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off) 450 # define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off) 451 # define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh) 452 # define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh) 453 # define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh) 454 # define i_MFC0(buf, rt, rd) i_dmfc0(buf, rt, rd) 455 # define i_MTC0(buf, rt, rd) i_dmtc0(buf, rt, rd) 456 # define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val) 457 # define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd) 458 # define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd) 459 # define i_LL(buf, rs, rt, off) i_lld(buf, rs, rt, off) 460 # define i_SC(buf, rs, rt, off) i_scd(buf, rs, rt, off) 461 #else 462 # define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off) 463 # define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off) 464 # define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh) 465 # define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh) 466 # define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh) 467 # define i_MFC0(buf, rt, rd) i_mfc0(buf, rt, rd) 468 # define i_MTC0(buf, rt, rd) i_mtc0(buf, rt, rd) 469 # define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val) 470 # define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd) 471 # define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd) 472 # define i_LL(buf, rs, rt, off) i_ll(buf, rs, rt, off) 473 # define i_SC(buf, rs, rt, off) i_sc(buf, rs, rt, off) 474 #endif 475 476 #define i_b(buf, off) i_beq(buf, 0, 0, off) 477 #define i_beqz(buf, rs, off) i_beq(buf, rs, 0, off) 478 #define i_beqzl(buf, rs, off) i_beql(buf, rs, 0, off) 479 #define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off) 480 #define i_bnezl(buf, rs, off) i_bnel(buf, rs, 0, off) 481 #define i_move(buf, a, b) i_ADDU(buf, a, 0, b) 482 #define i_nop(buf) i_sll(buf, 0, 0, 0) 483 #define i_ssnop(buf) i_sll(buf, 0, 0, 1) 484 #define i_ehb(buf) i_sll(buf, 0, 0, 3) 485 486 #ifdef CONFIG_64BIT 487 static __init int __attribute__((unused)) in_compat_space_p(long addr) 488 { 489 /* Is this address in 32bit compat space? */ 490 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); 491 } 492 493 static __init int __attribute__((unused)) rel_highest(long val) 494 { 495 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 496 } 497 498 static __init int __attribute__((unused)) rel_higher(long val) 499 { 500 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 501 } 502 #endif 503 504 static __init int rel_hi(long val) 505 { 506 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 507 } 508 509 static __init int rel_lo(long val) 510 { 511 return ((val & 0xffff) ^ 0x8000) - 0x8000; 512 } 513 514 static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) 515 { 516 #ifdef CONFIG_64BIT 517 if (!in_compat_space_p(addr)) { 518 i_lui(buf, rs, rel_highest(addr)); 519 if (rel_higher(addr)) 520 i_daddiu(buf, rs, rs, rel_higher(addr)); 521 if (rel_hi(addr)) { 522 i_dsll(buf, rs, rs, 16); 523 i_daddiu(buf, rs, rs, rel_hi(addr)); 524 i_dsll(buf, rs, rs, 16); 525 } else 526 i_dsll32(buf, rs, rs, 0); 527 } else 528 #endif 529 i_lui(buf, rs, rel_hi(addr)); 530 } 531 532 static __init void __attribute__((unused)) i_LA(u32 **buf, unsigned int rs, 533 long addr) 534 { 535 i_LA_mostly(buf, rs, addr); 536 if (rel_lo(addr)) 537 i_ADDIU(buf, rs, rs, rel_lo(addr)); 538 } 539 540 /* 541 * handle relocations 542 */ 543 544 struct reloc { 545 u32 *addr; 546 unsigned int type; 547 enum label_id lab; 548 }; 549 550 static __init void r_mips_pc16(struct reloc **rel, u32 *addr, 551 enum label_id l) 552 { 553 (*rel)->addr = addr; 554 (*rel)->type = R_MIPS_PC16; 555 (*rel)->lab = l; 556 (*rel)++; 557 } 558 559 static inline void __resolve_relocs(struct reloc *rel, struct label *lab) 560 { 561 long laddr = (long)lab->addr; 562 long raddr = (long)rel->addr; 563 564 switch (rel->type) { 565 case R_MIPS_PC16: 566 *rel->addr |= build_bimm(laddr - (raddr + 4)); 567 break; 568 569 default: 570 panic("Unsupported TLB synthesizer relocation %d", 571 rel->type); 572 } 573 } 574 575 static __init void resolve_relocs(struct reloc *rel, struct label *lab) 576 { 577 struct label *l; 578 579 for (; rel->lab != label_invalid; rel++) 580 for (l = lab; l->lab != label_invalid; l++) 581 if (rel->lab == l->lab) 582 __resolve_relocs(rel, l); 583 } 584 585 static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end, 586 long off) 587 { 588 for (; rel->lab != label_invalid; rel++) 589 if (rel->addr >= first && rel->addr < end) 590 rel->addr += off; 591 } 592 593 static __init void move_labels(struct label *lab, u32 *first, u32 *end, 594 long off) 595 { 596 for (; lab->lab != label_invalid; lab++) 597 if (lab->addr >= first && lab->addr < end) 598 lab->addr += off; 599 } 600 601 static __init void copy_handler(struct reloc *rel, struct label *lab, 602 u32 *first, u32 *end, u32 *target) 603 { 604 long off = (long)(target - first); 605 606 memcpy(target, first, (end - first) * sizeof(u32)); 607 608 move_relocs(rel, first, end, off); 609 move_labels(lab, first, end, off); 610 } 611 612 static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel, 613 u32 *addr) 614 { 615 for (; rel->lab != label_invalid; rel++) { 616 if (rel->addr == addr 617 && (rel->type == R_MIPS_PC16 618 || rel->type == R_MIPS_26)) 619 return 1; 620 } 621 622 return 0; 623 } 624 625 /* convenience functions for labeled branches */ 626 static void __attribute__((unused)) il_bltz(u32 **p, struct reloc **r, 627 unsigned int reg, enum label_id l) 628 { 629 r_mips_pc16(r, *p, l); 630 i_bltz(p, reg, 0); 631 } 632 633 static void __attribute__((unused)) il_b(u32 **p, struct reloc **r, 634 enum label_id l) 635 { 636 r_mips_pc16(r, *p, l); 637 i_b(p, 0); 638 } 639 640 static void il_beqz(u32 **p, struct reloc **r, unsigned int reg, 641 enum label_id l) 642 { 643 r_mips_pc16(r, *p, l); 644 i_beqz(p, reg, 0); 645 } 646 647 static void __attribute__((unused)) 648 il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) 649 { 650 r_mips_pc16(r, *p, l); 651 i_beqzl(p, reg, 0); 652 } 653 654 static void il_bnez(u32 **p, struct reloc **r, unsigned int reg, 655 enum label_id l) 656 { 657 r_mips_pc16(r, *p, l); 658 i_bnez(p, reg, 0); 659 } 660 661 static void il_bgezl(u32 **p, struct reloc **r, unsigned int reg, 662 enum label_id l) 663 { 664 r_mips_pc16(r, *p, l); 665 i_bgezl(p, reg, 0); 666 } 667 668 /* The only general purpose registers allowed in TLB handlers. */ 669 #define K0 26 670 #define K1 27 671 672 /* Some CP0 registers */ 673 #define C0_INDEX 0 674 #define C0_ENTRYLO0 2 675 #define C0_ENTRYLO1 3 676 #define C0_CONTEXT 4 677 #define C0_BADVADDR 8 678 #define C0_ENTRYHI 10 679 #define C0_EPC 14 680 #define C0_XCONTEXT 20 681 682 #ifdef CONFIG_64BIT 683 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT) 684 #else 685 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT) 686 #endif 687 688 /* The worst case length of the handler is around 18 instructions for 689 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 690 * Maximum space available is 32 instructions for R3000 and 64 691 * instructions for R4000. 692 * 693 * We deliberately chose a buffer size of 128, so we won't scribble 694 * over anything important on overflow before we panic. 695 */ 696 static __initdata u32 tlb_handler[128]; 697 698 /* simply assume worst case size for labels and relocs */ 699 static __initdata struct label labels[128]; 700 static __initdata struct reloc relocs[128]; 701 702 /* 703 * The R3000 TLB handler is simple. 704 */ 705 static void __init build_r3000_tlb_refill_handler(void) 706 { 707 long pgdc = (long)pgd_current; 708 u32 *p; 709 710 memset(tlb_handler, 0, sizeof(tlb_handler)); 711 p = tlb_handler; 712 713 i_mfc0(&p, K0, C0_BADVADDR); 714 i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */ 715 i_lw(&p, K1, rel_lo(pgdc), K1); 716 i_srl(&p, K0, K0, 22); /* load delay */ 717 i_sll(&p, K0, K0, 2); 718 i_addu(&p, K1, K1, K0); 719 i_mfc0(&p, K0, C0_CONTEXT); 720 i_lw(&p, K1, 0, K1); /* cp0 delay */ 721 i_andi(&p, K0, K0, 0xffc); /* load delay */ 722 i_addu(&p, K1, K1, K0); 723 i_lw(&p, K0, 0, K1); 724 i_nop(&p); /* load delay */ 725 i_mtc0(&p, K0, C0_ENTRYLO0); 726 i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 727 i_tlbwr(&p); /* cp0 delay */ 728 i_jr(&p, K1); 729 i_rfe(&p); /* branch delay */ 730 731 if (p > tlb_handler + 32) 732 panic("TLB refill handler space exceeded"); 733 734 printk("Synthesized TLB refill handler (%u instructions).\n", 735 (unsigned int)(p - tlb_handler)); 736 #ifdef DEBUG_TLB 737 { 738 int i; 739 740 for (i = 0; i < (p - tlb_handler); i++) 741 printk("%08x\n", tlb_handler[i]); 742 } 743 #endif 744 745 memcpy((void *)CAC_BASE, tlb_handler, 0x80); 746 } 747 748 /* 749 * The R4000 TLB handler is much more complicated. We have two 750 * consecutive handler areas with 32 instructions space each. 751 * Since they aren't used at the same time, we can overflow in the 752 * other one.To keep things simple, we first assume linear space, 753 * then we relocate it to the final handler layout as needed. 754 */ 755 static __initdata u32 final_handler[64]; 756 757 /* 758 * Hazards 759 * 760 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 761 * 2. A timing hazard exists for the TLBP instruction. 762 * 763 * stalling_instruction 764 * TLBP 765 * 766 * The JTLB is being read for the TLBP throughout the stall generated by the 767 * previous instruction. This is not really correct as the stalling instruction 768 * can modify the address used to access the JTLB. The failure symptom is that 769 * the TLBP instruction will use an address created for the stalling instruction 770 * and not the address held in C0_ENHI and thus report the wrong results. 771 * 772 * The software work-around is to not allow the instruction preceding the TLBP 773 * to stall - make it an NOP or some other instruction guaranteed not to stall. 774 * 775 * Errata 2 will not be fixed. This errata is also on the R5000. 776 * 777 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 778 */ 779 static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p) 780 { 781 switch (current_cpu_data.cputype) { 782 /* Found by experiment: R4600 v2.0 needs this, too. */ 783 case CPU_R4600: 784 case CPU_R5000: 785 case CPU_R5000A: 786 case CPU_NEVADA: 787 i_nop(p); 788 i_tlbp(p); 789 break; 790 791 default: 792 i_tlbp(p); 793 break; 794 } 795 } 796 797 /* 798 * Write random or indexed TLB entry, and care about the hazards from 799 * the preceeding mtc0 and for the following eret. 800 */ 801 enum tlb_write_entry { tlb_random, tlb_indexed }; 802 803 static __init void build_tlb_write_entry(u32 **p, struct label **l, 804 struct reloc **r, 805 enum tlb_write_entry wmode) 806 { 807 void(*tlbw)(u32 **) = NULL; 808 809 switch (wmode) { 810 case tlb_random: tlbw = i_tlbwr; break; 811 case tlb_indexed: tlbw = i_tlbwi; break; 812 } 813 814 switch (current_cpu_data.cputype) { 815 case CPU_R4000PC: 816 case CPU_R4000SC: 817 case CPU_R4000MC: 818 case CPU_R4400PC: 819 case CPU_R4400SC: 820 case CPU_R4400MC: 821 /* 822 * This branch uses up a mtc0 hazard nop slot and saves 823 * two nops after the tlbw instruction. 824 */ 825 il_bgezl(p, r, 0, label_tlbw_hazard); 826 tlbw(p); 827 l_tlbw_hazard(l, *p); 828 i_nop(p); 829 break; 830 831 case CPU_R4600: 832 case CPU_R4700: 833 case CPU_R5000: 834 case CPU_R5000A: 835 i_nop(p); 836 tlbw(p); 837 i_nop(p); 838 break; 839 840 case CPU_R4300: 841 case CPU_5KC: 842 case CPU_TX49XX: 843 case CPU_AU1000: 844 case CPU_AU1100: 845 case CPU_AU1500: 846 case CPU_AU1550: 847 case CPU_AU1200: 848 case CPU_PR4450: 849 i_nop(p); 850 tlbw(p); 851 break; 852 853 case CPU_R10000: 854 case CPU_R12000: 855 case CPU_4KC: 856 case CPU_SB1: 857 case CPU_SB1A: 858 case CPU_4KSC: 859 case CPU_20KC: 860 case CPU_25KF: 861 tlbw(p); 862 break; 863 864 case CPU_NEVADA: 865 i_nop(p); /* QED specifies 2 nops hazard */ 866 /* 867 * This branch uses up a mtc0 hazard nop slot and saves 868 * a nop after the tlbw instruction. 869 */ 870 il_bgezl(p, r, 0, label_tlbw_hazard); 871 tlbw(p); 872 l_tlbw_hazard(l, *p); 873 break; 874 875 case CPU_RM7000: 876 i_nop(p); 877 i_nop(p); 878 i_nop(p); 879 i_nop(p); 880 tlbw(p); 881 break; 882 883 case CPU_4KEC: 884 case CPU_24K: 885 case CPU_34K: 886 i_ehb(p); 887 tlbw(p); 888 break; 889 890 case CPU_RM9000: 891 /* 892 * When the JTLB is updated by tlbwi or tlbwr, a subsequent 893 * use of the JTLB for instructions should not occur for 4 894 * cpu cycles and use for data translations should not occur 895 * for 3 cpu cycles. 896 */ 897 i_ssnop(p); 898 i_ssnop(p); 899 i_ssnop(p); 900 i_ssnop(p); 901 tlbw(p); 902 i_ssnop(p); 903 i_ssnop(p); 904 i_ssnop(p); 905 i_ssnop(p); 906 break; 907 908 case CPU_VR4111: 909 case CPU_VR4121: 910 case CPU_VR4122: 911 case CPU_VR4181: 912 case CPU_VR4181A: 913 i_nop(p); 914 i_nop(p); 915 tlbw(p); 916 i_nop(p); 917 i_nop(p); 918 break; 919 920 case CPU_VR4131: 921 case CPU_VR4133: 922 case CPU_R5432: 923 i_nop(p); 924 i_nop(p); 925 tlbw(p); 926 break; 927 928 default: 929 panic("No TLB refill handler yet (CPU type: %d)", 930 current_cpu_data.cputype); 931 break; 932 } 933 } 934 935 #ifdef CONFIG_64BIT 936 /* 937 * TMP and PTR are scratch. 938 * TMP will be clobbered, PTR will hold the pmd entry. 939 */ 940 static __init void 941 build_get_pmde64(u32 **p, struct label **l, struct reloc **r, 942 unsigned int tmp, unsigned int ptr) 943 { 944 long pgdc = (long)pgd_current; 945 946 /* 947 * The vmalloc handling is not in the hotpath. 948 */ 949 i_dmfc0(p, tmp, C0_BADVADDR); 950 il_bltz(p, r, tmp, label_vmalloc); 951 /* No i_nop needed here, since the next insn doesn't touch TMP. */ 952 953 #ifdef CONFIG_SMP 954 # ifdef CONFIG_BUILD_ELF64 955 /* 956 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 957 * stored in CONTEXT. 958 */ 959 i_dmfc0(p, ptr, C0_CONTEXT); 960 i_dsrl(p, ptr, ptr, 23); 961 i_LA_mostly(p, tmp, pgdc); 962 i_daddu(p, ptr, ptr, tmp); 963 i_dmfc0(p, tmp, C0_BADVADDR); 964 i_ld(p, ptr, rel_lo(pgdc), ptr); 965 # else 966 /* 967 * 64 bit SMP running in compat space has the lower part of 968 * &pgd_current[smp_processor_id()] stored in CONTEXT. 969 */ 970 if (!in_compat_space_p(pgdc)) 971 panic("Invalid page directory address!"); 972 973 i_dmfc0(p, ptr, C0_CONTEXT); 974 i_dsra(p, ptr, ptr, 23); 975 i_ld(p, ptr, 0, ptr); 976 # endif 977 #else 978 i_LA_mostly(p, ptr, pgdc); 979 i_ld(p, ptr, rel_lo(pgdc), ptr); 980 #endif 981 982 l_vmalloc_done(l, *p); 983 i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); /* get pgd offset in bytes */ 984 i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 985 i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 986 i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 987 i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 988 i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 989 i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 990 i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 991 } 992 993 /* 994 * BVADDR is the faulting address, PTR is scratch. 995 * PTR will hold the pgd for vmalloc. 996 */ 997 static __init void 998 build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, 999 unsigned int bvaddr, unsigned int ptr) 1000 { 1001 long swpd = (long)swapper_pg_dir; 1002 1003 l_vmalloc(l, *p); 1004 i_LA(p, ptr, VMALLOC_START); 1005 i_dsubu(p, bvaddr, bvaddr, ptr); 1006 1007 if (in_compat_space_p(swpd) && !rel_lo(swpd)) { 1008 il_b(p, r, label_vmalloc_done); 1009 i_lui(p, ptr, rel_hi(swpd)); 1010 } else { 1011 i_LA_mostly(p, ptr, swpd); 1012 il_b(p, r, label_vmalloc_done); 1013 i_daddiu(p, ptr, ptr, rel_lo(swpd)); 1014 } 1015 } 1016 1017 #else /* !CONFIG_64BIT */ 1018 1019 /* 1020 * TMP and PTR are scratch. 1021 * TMP will be clobbered, PTR will hold the pgd entry. 1022 */ 1023 static __init void __attribute__((unused)) 1024 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 1025 { 1026 long pgdc = (long)pgd_current; 1027 1028 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 1029 #ifdef CONFIG_SMP 1030 i_mfc0(p, ptr, C0_CONTEXT); 1031 i_LA_mostly(p, tmp, pgdc); 1032 i_srl(p, ptr, ptr, 23); 1033 i_addu(p, ptr, tmp, ptr); 1034 #else 1035 i_LA_mostly(p, ptr, pgdc); 1036 #endif 1037 i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 1038 i_lw(p, ptr, rel_lo(pgdc), ptr); 1039 i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 1040 i_sll(p, tmp, tmp, PGD_T_LOG2); 1041 i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 1042 } 1043 1044 #endif /* !CONFIG_64BIT */ 1045 1046 static __init void build_adjust_context(u32 **p, unsigned int ctx) 1047 { 1048 unsigned int shift = 4 - (PTE_T_LOG2 + 1); 1049 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 1050 1051 switch (current_cpu_data.cputype) { 1052 case CPU_VR41XX: 1053 case CPU_VR4111: 1054 case CPU_VR4121: 1055 case CPU_VR4122: 1056 case CPU_VR4131: 1057 case CPU_VR4181: 1058 case CPU_VR4181A: 1059 case CPU_VR4133: 1060 shift += 2; 1061 break; 1062 1063 default: 1064 break; 1065 } 1066 1067 if (shift) 1068 i_SRL(p, ctx, ctx, shift); 1069 i_andi(p, ctx, ctx, mask); 1070 } 1071 1072 static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1073 { 1074 /* 1075 * Bug workaround for the Nevada. It seems as if under certain 1076 * circumstances the move from cp0_context might produce a 1077 * bogus result when the mfc0 instruction and its consumer are 1078 * in a different cacheline or a load instruction, probably any 1079 * memory reference, is between them. 1080 */ 1081 switch (current_cpu_data.cputype) { 1082 case CPU_NEVADA: 1083 i_LW(p, ptr, 0, ptr); 1084 GET_CONTEXT(p, tmp); /* get context reg */ 1085 break; 1086 1087 default: 1088 GET_CONTEXT(p, tmp); /* get context reg */ 1089 i_LW(p, ptr, 0, ptr); 1090 break; 1091 } 1092 1093 build_adjust_context(p, tmp); 1094 i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1095 } 1096 1097 static __init void build_update_entries(u32 **p, unsigned int tmp, 1098 unsigned int ptep) 1099 { 1100 /* 1101 * 64bit address support (36bit on a 32bit CPU) in a 32bit 1102 * Kernel is a special case. Only a few CPUs use it. 1103 */ 1104 #ifdef CONFIG_64BIT_PHYS_ADDR 1105 if (cpu_has_64bits) { 1106 i_ld(p, tmp, 0, ptep); /* get even pte */ 1107 i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 1108 i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ 1109 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1110 i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ 1111 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1112 } else { 1113 int pte_off_even = sizeof(pte_t) / 2; 1114 int pte_off_odd = pte_off_even + sizeof(pte_t); 1115 1116 /* The pte entries are pre-shifted */ 1117 i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ 1118 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1119 i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ 1120 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1121 } 1122 #else 1123 i_LW(p, tmp, 0, ptep); /* get even pte */ 1124 i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 1125 if (r45k_bvahwbug()) 1126 build_tlb_probe_entry(p); 1127 i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ 1128 if (r4k_250MHZhwbug()) 1129 i_mtc0(p, 0, C0_ENTRYLO0); 1130 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1131 i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ 1132 if (r45k_bvahwbug()) 1133 i_mfc0(p, tmp, C0_INDEX); 1134 if (r4k_250MHZhwbug()) 1135 i_mtc0(p, 0, C0_ENTRYLO1); 1136 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1137 #endif 1138 } 1139 1140 static void __init build_r4000_tlb_refill_handler(void) 1141 { 1142 u32 *p = tlb_handler; 1143 struct label *l = labels; 1144 struct reloc *r = relocs; 1145 u32 *f; 1146 unsigned int final_len; 1147 1148 memset(tlb_handler, 0, sizeof(tlb_handler)); 1149 memset(labels, 0, sizeof(labels)); 1150 memset(relocs, 0, sizeof(relocs)); 1151 memset(final_handler, 0, sizeof(final_handler)); 1152 1153 /* 1154 * create the plain linear handler 1155 */ 1156 if (bcm1250_m3_war()) { 1157 i_MFC0(&p, K0, C0_BADVADDR); 1158 i_MFC0(&p, K1, C0_ENTRYHI); 1159 i_xor(&p, K0, K0, K1); 1160 i_SRL(&p, K0, K0, PAGE_SHIFT + 1); 1161 il_bnez(&p, &r, K0, label_leave); 1162 /* No need for i_nop */ 1163 } 1164 1165 #ifdef CONFIG_64BIT 1166 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1167 #else 1168 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1169 #endif 1170 1171 build_get_ptep(&p, K0, K1); 1172 build_update_entries(&p, K0, K1); 1173 build_tlb_write_entry(&p, &l, &r, tlb_random); 1174 l_leave(&l, p); 1175 i_eret(&p); /* return from trap */ 1176 1177 #ifdef CONFIG_64BIT 1178 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); 1179 #endif 1180 1181 /* 1182 * Overflow check: For the 64bit handler, we need at least one 1183 * free instruction slot for the wrap-around branch. In worst 1184 * case, if the intended insertion point is a delay slot, we 1185 * need three, with the the second nop'ed and the third being 1186 * unused. 1187 */ 1188 #ifdef CONFIG_32BIT 1189 if ((p - tlb_handler) > 64) 1190 panic("TLB refill handler space exceeded"); 1191 #else 1192 if (((p - tlb_handler) > 63) 1193 || (((p - tlb_handler) > 61) 1194 && insn_has_bdelay(relocs, tlb_handler + 29))) 1195 panic("TLB refill handler space exceeded"); 1196 #endif 1197 1198 /* 1199 * Now fold the handler in the TLB refill handler space. 1200 */ 1201 #ifdef CONFIG_32BIT 1202 f = final_handler; 1203 /* Simplest case, just copy the handler. */ 1204 copy_handler(relocs, labels, tlb_handler, p, f); 1205 final_len = p - tlb_handler; 1206 #else /* CONFIG_64BIT */ 1207 f = final_handler + 32; 1208 if ((p - tlb_handler) <= 32) { 1209 /* Just copy the handler. */ 1210 copy_handler(relocs, labels, tlb_handler, p, f); 1211 final_len = p - tlb_handler; 1212 } else { 1213 u32 *split = tlb_handler + 30; 1214 1215 /* 1216 * Find the split point. 1217 */ 1218 if (insn_has_bdelay(relocs, split - 1)) 1219 split--; 1220 1221 /* Copy first part of the handler. */ 1222 copy_handler(relocs, labels, tlb_handler, split, f); 1223 f += split - tlb_handler; 1224 1225 /* Insert branch. */ 1226 l_split(&l, final_handler); 1227 il_b(&f, &r, label_split); 1228 if (insn_has_bdelay(relocs, split)) 1229 i_nop(&f); 1230 else { 1231 copy_handler(relocs, labels, split, split + 1, f); 1232 move_labels(labels, f, f + 1, -1); 1233 f++; 1234 split++; 1235 } 1236 1237 /* Copy the rest of the handler. */ 1238 copy_handler(relocs, labels, split, p, final_handler); 1239 final_len = (f - (final_handler + 32)) + (p - split); 1240 } 1241 #endif /* CONFIG_64BIT */ 1242 1243 resolve_relocs(relocs, labels); 1244 printk("Synthesized TLB refill handler (%u instructions).\n", 1245 final_len); 1246 1247 #ifdef DEBUG_TLB 1248 { 1249 int i; 1250 1251 f = final_handler; 1252 #ifdef CONFIG_64BIT 1253 if (final_len > 32) 1254 final_len = 64; 1255 else 1256 f = final_handler + 32; 1257 #endif /* CONFIG_64BIT */ 1258 for (i = 0; i < final_len; i++) 1259 printk("%08x\n", f[i]); 1260 } 1261 #endif 1262 1263 memcpy((void *)CAC_BASE, final_handler, 0x100); 1264 } 1265 1266 /* 1267 * TLB load/store/modify handlers. 1268 * 1269 * Only the fastpath gets synthesized at runtime, the slowpath for 1270 * do_page_fault remains normal asm. 1271 */ 1272 extern void tlb_do_page_fault_0(void); 1273 extern void tlb_do_page_fault_1(void); 1274 1275 #define __tlb_handler_align \ 1276 __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT))) 1277 1278 /* 1279 * 128 instructions for the fastpath handler is generous and should 1280 * never be exceeded. 1281 */ 1282 #define FASTPATH_SIZE 128 1283 1284 u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE]; 1285 u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE]; 1286 u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE]; 1287 1288 static void __init 1289 iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr) 1290 { 1291 #ifdef CONFIG_SMP 1292 # ifdef CONFIG_64BIT_PHYS_ADDR 1293 if (cpu_has_64bits) 1294 i_lld(p, pte, 0, ptr); 1295 else 1296 # endif 1297 i_LL(p, pte, 0, ptr); 1298 #else 1299 # ifdef CONFIG_64BIT_PHYS_ADDR 1300 if (cpu_has_64bits) 1301 i_ld(p, pte, 0, ptr); 1302 else 1303 # endif 1304 i_LW(p, pte, 0, ptr); 1305 #endif 1306 } 1307 1308 static void __init 1309 iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr, 1310 unsigned int mode) 1311 { 1312 #ifdef CONFIG_64BIT_PHYS_ADDR 1313 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1314 #endif 1315 1316 i_ori(p, pte, pte, mode); 1317 #ifdef CONFIG_SMP 1318 # ifdef CONFIG_64BIT_PHYS_ADDR 1319 if (cpu_has_64bits) 1320 i_scd(p, pte, 0, ptr); 1321 else 1322 # endif 1323 i_SC(p, pte, 0, ptr); 1324 1325 if (r10000_llsc_war()) 1326 il_beqzl(p, r, pte, label_smp_pgtable_change); 1327 else 1328 il_beqz(p, r, pte, label_smp_pgtable_change); 1329 1330 # ifdef CONFIG_64BIT_PHYS_ADDR 1331 if (!cpu_has_64bits) { 1332 /* no i_nop needed */ 1333 i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1334 i_ori(p, pte, pte, hwmode); 1335 i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1336 il_beqz(p, r, pte, label_smp_pgtable_change); 1337 /* no i_nop needed */ 1338 i_lw(p, pte, 0, ptr); 1339 } else 1340 i_nop(p); 1341 # else 1342 i_nop(p); 1343 # endif 1344 #else 1345 # ifdef CONFIG_64BIT_PHYS_ADDR 1346 if (cpu_has_64bits) 1347 i_sd(p, pte, 0, ptr); 1348 else 1349 # endif 1350 i_SW(p, pte, 0, ptr); 1351 1352 # ifdef CONFIG_64BIT_PHYS_ADDR 1353 if (!cpu_has_64bits) { 1354 i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1355 i_ori(p, pte, pte, hwmode); 1356 i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1357 i_lw(p, pte, 0, ptr); 1358 } 1359 # endif 1360 #endif 1361 } 1362 1363 /* 1364 * Check if PTE is present, if not then jump to LABEL. PTR points to 1365 * the page table where this PTE is located, PTE will be re-loaded 1366 * with it's original value. 1367 */ 1368 static void __init 1369 build_pte_present(u32 **p, struct label **l, struct reloc **r, 1370 unsigned int pte, unsigned int ptr, enum label_id lid) 1371 { 1372 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 1373 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 1374 il_bnez(p, r, pte, lid); 1375 iPTE_LW(p, l, pte, ptr); 1376 } 1377 1378 /* Make PTE valid, store result in PTR. */ 1379 static void __init 1380 build_make_valid(u32 **p, struct reloc **r, unsigned int pte, 1381 unsigned int ptr) 1382 { 1383 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 1384 1385 iPTE_SW(p, r, pte, ptr, mode); 1386 } 1387 1388 /* 1389 * Check if PTE can be written to, if not branch to LABEL. Regardless 1390 * restore PTE with value from PTR when done. 1391 */ 1392 static void __init 1393 build_pte_writable(u32 **p, struct label **l, struct reloc **r, 1394 unsigned int pte, unsigned int ptr, enum label_id lid) 1395 { 1396 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 1397 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 1398 il_bnez(p, r, pte, lid); 1399 iPTE_LW(p, l, pte, ptr); 1400 } 1401 1402 /* Make PTE writable, update software status bits as well, then store 1403 * at PTR. 1404 */ 1405 static void __init 1406 build_make_write(u32 **p, struct reloc **r, unsigned int pte, 1407 unsigned int ptr) 1408 { 1409 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 1410 | _PAGE_DIRTY); 1411 1412 iPTE_SW(p, r, pte, ptr, mode); 1413 } 1414 1415 /* 1416 * Check if PTE can be modified, if not branch to LABEL. Regardless 1417 * restore PTE with value from PTR when done. 1418 */ 1419 static void __init 1420 build_pte_modifiable(u32 **p, struct label **l, struct reloc **r, 1421 unsigned int pte, unsigned int ptr, enum label_id lid) 1422 { 1423 i_andi(p, pte, pte, _PAGE_WRITE); 1424 il_beqz(p, r, pte, lid); 1425 iPTE_LW(p, l, pte, ptr); 1426 } 1427 1428 /* 1429 * R3000 style TLB load/store/modify handlers. 1430 */ 1431 1432 /* 1433 * This places the pte into ENTRYLO0 and writes it with tlbwi. 1434 * Then it returns. 1435 */ 1436 static void __init 1437 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 1438 { 1439 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1440 i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 1441 i_tlbwi(p); 1442 i_jr(p, tmp); 1443 i_rfe(p); /* branch delay */ 1444 } 1445 1446 /* 1447 * This places the pte into ENTRYLO0 and writes it with tlbwi 1448 * or tlbwr as appropriate. This is because the index register 1449 * may have the probe fail bit set as a result of a trap on a 1450 * kseg2 access, i.e. without refill. Then it returns. 1451 */ 1452 static void __init 1453 build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r, 1454 unsigned int pte, unsigned int tmp) 1455 { 1456 i_mfc0(p, tmp, C0_INDEX); 1457 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1458 il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 1459 i_mfc0(p, tmp, C0_EPC); /* branch delay */ 1460 i_tlbwi(p); /* cp0 delay */ 1461 i_jr(p, tmp); 1462 i_rfe(p); /* branch delay */ 1463 l_r3000_write_probe_fail(l, *p); 1464 i_tlbwr(p); /* cp0 delay */ 1465 i_jr(p, tmp); 1466 i_rfe(p); /* branch delay */ 1467 } 1468 1469 static void __init 1470 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1471 unsigned int ptr) 1472 { 1473 long pgdc = (long)pgd_current; 1474 1475 i_mfc0(p, pte, C0_BADVADDR); 1476 i_lui(p, ptr, rel_hi(pgdc)); /* cp0 delay */ 1477 i_lw(p, ptr, rel_lo(pgdc), ptr); 1478 i_srl(p, pte, pte, 22); /* load delay */ 1479 i_sll(p, pte, pte, 2); 1480 i_addu(p, ptr, ptr, pte); 1481 i_mfc0(p, pte, C0_CONTEXT); 1482 i_lw(p, ptr, 0, ptr); /* cp0 delay */ 1483 i_andi(p, pte, pte, 0xffc); /* load delay */ 1484 i_addu(p, ptr, ptr, pte); 1485 i_lw(p, pte, 0, ptr); 1486 i_tlbp(p); /* load delay */ 1487 } 1488 1489 static void __init build_r3000_tlb_load_handler(void) 1490 { 1491 u32 *p = handle_tlbl; 1492 struct label *l = labels; 1493 struct reloc *r = relocs; 1494 1495 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1496 memset(labels, 0, sizeof(labels)); 1497 memset(relocs, 0, sizeof(relocs)); 1498 1499 build_r3000_tlbchange_handler_head(&p, K0, K1); 1500 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1501 i_nop(&p); /* load delay */ 1502 build_make_valid(&p, &r, K0, K1); 1503 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1504 1505 l_nopage_tlbl(&l, p); 1506 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1507 i_nop(&p); 1508 1509 if ((p - handle_tlbl) > FASTPATH_SIZE) 1510 panic("TLB load handler fastpath space exceeded"); 1511 1512 resolve_relocs(relocs, labels); 1513 printk("Synthesized TLB load handler fastpath (%u instructions).\n", 1514 (unsigned int)(p - handle_tlbl)); 1515 1516 #ifdef DEBUG_TLB 1517 { 1518 int i; 1519 1520 for (i = 0; i < (p - handle_tlbl); i++) 1521 printk("%08x\n", handle_tlbl[i]); 1522 } 1523 #endif 1524 } 1525 1526 static void __init build_r3000_tlb_store_handler(void) 1527 { 1528 u32 *p = handle_tlbs; 1529 struct label *l = labels; 1530 struct reloc *r = relocs; 1531 1532 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1533 memset(labels, 0, sizeof(labels)); 1534 memset(relocs, 0, sizeof(relocs)); 1535 1536 build_r3000_tlbchange_handler_head(&p, K0, K1); 1537 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1538 i_nop(&p); /* load delay */ 1539 build_make_write(&p, &r, K0, K1); 1540 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1541 1542 l_nopage_tlbs(&l, p); 1543 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1544 i_nop(&p); 1545 1546 if ((p - handle_tlbs) > FASTPATH_SIZE) 1547 panic("TLB store handler fastpath space exceeded"); 1548 1549 resolve_relocs(relocs, labels); 1550 printk("Synthesized TLB store handler fastpath (%u instructions).\n", 1551 (unsigned int)(p - handle_tlbs)); 1552 1553 #ifdef DEBUG_TLB 1554 { 1555 int i; 1556 1557 for (i = 0; i < (p - handle_tlbs); i++) 1558 printk("%08x\n", handle_tlbs[i]); 1559 } 1560 #endif 1561 } 1562 1563 static void __init build_r3000_tlb_modify_handler(void) 1564 { 1565 u32 *p = handle_tlbm; 1566 struct label *l = labels; 1567 struct reloc *r = relocs; 1568 1569 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1570 memset(labels, 0, sizeof(labels)); 1571 memset(relocs, 0, sizeof(relocs)); 1572 1573 build_r3000_tlbchange_handler_head(&p, K0, K1); 1574 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1575 i_nop(&p); /* load delay */ 1576 build_make_write(&p, &r, K0, K1); 1577 build_r3000_pte_reload_tlbwi(&p, K0, K1); 1578 1579 l_nopage_tlbm(&l, p); 1580 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1581 i_nop(&p); 1582 1583 if ((p - handle_tlbm) > FASTPATH_SIZE) 1584 panic("TLB modify handler fastpath space exceeded"); 1585 1586 resolve_relocs(relocs, labels); 1587 printk("Synthesized TLB modify handler fastpath (%u instructions).\n", 1588 (unsigned int)(p - handle_tlbm)); 1589 1590 #ifdef DEBUG_TLB 1591 { 1592 int i; 1593 1594 for (i = 0; i < (p - handle_tlbm); i++) 1595 printk("%08x\n", handle_tlbm[i]); 1596 } 1597 #endif 1598 } 1599 1600 /* 1601 * R4000 style TLB load/store/modify handlers. 1602 */ 1603 static void __init 1604 build_r4000_tlbchange_handler_head(u32 **p, struct label **l, 1605 struct reloc **r, unsigned int pte, 1606 unsigned int ptr) 1607 { 1608 #ifdef CONFIG_64BIT 1609 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ 1610 #else 1611 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ 1612 #endif 1613 1614 i_MFC0(p, pte, C0_BADVADDR); 1615 i_LW(p, ptr, 0, ptr); 1616 i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 1617 i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 1618 i_ADDU(p, ptr, ptr, pte); 1619 1620 #ifdef CONFIG_SMP 1621 l_smp_pgtable_change(l, *p); 1622 # endif 1623 iPTE_LW(p, l, pte, ptr); /* get even pte */ 1624 build_tlb_probe_entry(p); 1625 } 1626 1627 static void __init 1628 build_r4000_tlbchange_handler_tail(u32 **p, struct label **l, 1629 struct reloc **r, unsigned int tmp, 1630 unsigned int ptr) 1631 { 1632 i_ori(p, ptr, ptr, sizeof(pte_t)); 1633 i_xori(p, ptr, ptr, sizeof(pte_t)); 1634 build_update_entries(p, tmp, ptr); 1635 build_tlb_write_entry(p, l, r, tlb_indexed); 1636 l_leave(l, *p); 1637 i_eret(p); /* return from trap */ 1638 1639 #ifdef CONFIG_64BIT 1640 build_get_pgd_vmalloc64(p, l, r, tmp, ptr); 1641 #endif 1642 } 1643 1644 static void __init build_r4000_tlb_load_handler(void) 1645 { 1646 u32 *p = handle_tlbl; 1647 struct label *l = labels; 1648 struct reloc *r = relocs; 1649 1650 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1651 memset(labels, 0, sizeof(labels)); 1652 memset(relocs, 0, sizeof(relocs)); 1653 1654 if (bcm1250_m3_war()) { 1655 i_MFC0(&p, K0, C0_BADVADDR); 1656 i_MFC0(&p, K1, C0_ENTRYHI); 1657 i_xor(&p, K0, K0, K1); 1658 i_SRL(&p, K0, K0, PAGE_SHIFT + 1); 1659 il_bnez(&p, &r, K0, label_leave); 1660 /* No need for i_nop */ 1661 } 1662 1663 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1664 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1665 build_make_valid(&p, &r, K0, K1); 1666 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1667 1668 l_nopage_tlbl(&l, p); 1669 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1670 i_nop(&p); 1671 1672 if ((p - handle_tlbl) > FASTPATH_SIZE) 1673 panic("TLB load handler fastpath space exceeded"); 1674 1675 resolve_relocs(relocs, labels); 1676 printk("Synthesized TLB load handler fastpath (%u instructions).\n", 1677 (unsigned int)(p - handle_tlbl)); 1678 1679 #ifdef DEBUG_TLB 1680 { 1681 int i; 1682 1683 for (i = 0; i < (p - handle_tlbl); i++) 1684 printk("%08x\n", handle_tlbl[i]); 1685 } 1686 #endif 1687 } 1688 1689 static void __init build_r4000_tlb_store_handler(void) 1690 { 1691 u32 *p = handle_tlbs; 1692 struct label *l = labels; 1693 struct reloc *r = relocs; 1694 1695 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1696 memset(labels, 0, sizeof(labels)); 1697 memset(relocs, 0, sizeof(relocs)); 1698 1699 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1700 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1701 build_make_write(&p, &r, K0, K1); 1702 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1703 1704 l_nopage_tlbs(&l, p); 1705 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1706 i_nop(&p); 1707 1708 if ((p - handle_tlbs) > FASTPATH_SIZE) 1709 panic("TLB store handler fastpath space exceeded"); 1710 1711 resolve_relocs(relocs, labels); 1712 printk("Synthesized TLB store handler fastpath (%u instructions).\n", 1713 (unsigned int)(p - handle_tlbs)); 1714 1715 #ifdef DEBUG_TLB 1716 { 1717 int i; 1718 1719 for (i = 0; i < (p - handle_tlbs); i++) 1720 printk("%08x\n", handle_tlbs[i]); 1721 } 1722 #endif 1723 } 1724 1725 static void __init build_r4000_tlb_modify_handler(void) 1726 { 1727 u32 *p = handle_tlbm; 1728 struct label *l = labels; 1729 struct reloc *r = relocs; 1730 1731 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1732 memset(labels, 0, sizeof(labels)); 1733 memset(relocs, 0, sizeof(relocs)); 1734 1735 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1736 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1737 /* Present and writable bits set, set accessed and dirty bits. */ 1738 build_make_write(&p, &r, K0, K1); 1739 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1740 1741 l_nopage_tlbm(&l, p); 1742 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1743 i_nop(&p); 1744 1745 if ((p - handle_tlbm) > FASTPATH_SIZE) 1746 panic("TLB modify handler fastpath space exceeded"); 1747 1748 resolve_relocs(relocs, labels); 1749 printk("Synthesized TLB modify handler fastpath (%u instructions).\n", 1750 (unsigned int)(p - handle_tlbm)); 1751 1752 #ifdef DEBUG_TLB 1753 { 1754 int i; 1755 1756 for (i = 0; i < (p - handle_tlbm); i++) 1757 printk("%08x\n", handle_tlbm[i]); 1758 } 1759 #endif 1760 } 1761 1762 void __init build_tlb_refill_handler(void) 1763 { 1764 /* 1765 * The refill handler is generated per-CPU, multi-node systems 1766 * may have local storage for it. The other handlers are only 1767 * needed once. 1768 */ 1769 static int run_once = 0; 1770 1771 switch (current_cpu_data.cputype) { 1772 case CPU_R2000: 1773 case CPU_R3000: 1774 case CPU_R3000A: 1775 case CPU_R3081E: 1776 case CPU_TX3912: 1777 case CPU_TX3922: 1778 case CPU_TX3927: 1779 build_r3000_tlb_refill_handler(); 1780 if (!run_once) { 1781 build_r3000_tlb_load_handler(); 1782 build_r3000_tlb_store_handler(); 1783 build_r3000_tlb_modify_handler(); 1784 run_once++; 1785 } 1786 break; 1787 1788 case CPU_R6000: 1789 case CPU_R6000A: 1790 panic("No R6000 TLB refill handler yet"); 1791 break; 1792 1793 case CPU_R8000: 1794 panic("No R8000 TLB refill handler yet"); 1795 break; 1796 1797 default: 1798 build_r4000_tlb_refill_handler(); 1799 if (!run_once) { 1800 build_r4000_tlb_load_handler(); 1801 build_r4000_tlb_store_handler(); 1802 build_r4000_tlb_modify_handler(); 1803 run_once++; 1804 } 1805 } 1806 } 1807 1808 void __init flush_tlb_handlers(void) 1809 { 1810 flush_icache_range((unsigned long)handle_tlbl, 1811 (unsigned long)handle_tlbl + sizeof(handle_tlbl)); 1812 flush_icache_range((unsigned long)handle_tlbs, 1813 (unsigned long)handle_tlbs + sizeof(handle_tlbs)); 1814 flush_icache_range((unsigned long)handle_tlbm, 1815 (unsigned long)handle_tlbm + sizeof(handle_tlbm)); 1816 } 1817