1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 * Copyright (C) 2008, 2009 Cavium Networks, Inc. 12 * Copyright (C) 2011 MIPS Technologies, Inc. 13 * 14 * ... and the days got worse and worse and now you see 15 * I've gone completly out of my mind. 16 * 17 * They're coming to take me a away haha 18 * they're coming to take me a away hoho hihi haha 19 * to the funny farm where code is beautiful all the time ... 20 * 21 * (Condolences to Napoleon XIV) 22 */ 23 24 #include <linux/bug.h> 25 #include <linux/kernel.h> 26 #include <linux/types.h> 27 #include <linux/smp.h> 28 #include <linux/string.h> 29 #include <linux/cache.h> 30 31 #include <asm/cacheflush.h> 32 #include <asm/cpu-type.h> 33 #include <asm/pgtable.h> 34 #include <asm/war.h> 35 #include <asm/uasm.h> 36 #include <asm/setup.h> 37 38 static int mips_xpa_disabled; 39 40 static int __init xpa_disable(char *s) 41 { 42 mips_xpa_disabled = 1; 43 44 return 1; 45 } 46 47 __setup("noxpa", xpa_disable); 48 49 /* 50 * TLB load/store/modify handlers. 51 * 52 * Only the fastpath gets synthesized at runtime, the slowpath for 53 * do_page_fault remains normal asm. 54 */ 55 extern void tlb_do_page_fault_0(void); 56 extern void tlb_do_page_fault_1(void); 57 58 struct work_registers { 59 int r1; 60 int r2; 61 int r3; 62 }; 63 64 struct tlb_reg_save { 65 unsigned long a; 66 unsigned long b; 67 } ____cacheline_aligned_in_smp; 68 69 static struct tlb_reg_save handler_reg_save[NR_CPUS]; 70 71 static inline int r45k_bvahwbug(void) 72 { 73 /* XXX: We should probe for the presence of this bug, but we don't. */ 74 return 0; 75 } 76 77 static inline int r4k_250MHZhwbug(void) 78 { 79 /* XXX: We should probe for the presence of this bug, but we don't. */ 80 return 0; 81 } 82 83 static inline int __maybe_unused bcm1250_m3_war(void) 84 { 85 return BCM1250_M3_WAR; 86 } 87 88 static inline int __maybe_unused r10000_llsc_war(void) 89 { 90 return R10000_LLSC_WAR; 91 } 92 93 static int use_bbit_insns(void) 94 { 95 switch (current_cpu_type()) { 96 case CPU_CAVIUM_OCTEON: 97 case CPU_CAVIUM_OCTEON_PLUS: 98 case CPU_CAVIUM_OCTEON2: 99 case CPU_CAVIUM_OCTEON3: 100 return 1; 101 default: 102 return 0; 103 } 104 } 105 106 static int use_lwx_insns(void) 107 { 108 switch (current_cpu_type()) { 109 case CPU_CAVIUM_OCTEON2: 110 case CPU_CAVIUM_OCTEON3: 111 return 1; 112 default: 113 return 0; 114 } 115 } 116 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ 117 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 118 static bool scratchpad_available(void) 119 { 120 return true; 121 } 122 static int scratchpad_offset(int i) 123 { 124 /* 125 * CVMSEG starts at address -32768 and extends for 126 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. 127 */ 128 i += 1; /* Kernel use starts at the top and works down. */ 129 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; 130 } 131 #else 132 static bool scratchpad_available(void) 133 { 134 return false; 135 } 136 static int scratchpad_offset(int i) 137 { 138 BUG(); 139 /* Really unreachable, but evidently some GCC want this. */ 140 return 0; 141 } 142 #endif 143 /* 144 * Found by experiment: At least some revisions of the 4kc throw under 145 * some circumstances a machine check exception, triggered by invalid 146 * values in the index register. Delaying the tlbp instruction until 147 * after the next branch, plus adding an additional nop in front of 148 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows 149 * why; it's not an issue caused by the core RTL. 150 * 151 */ 152 static int m4kc_tlbp_war(void) 153 { 154 return (current_cpu_data.processor_id & 0xffff00) == 155 (PRID_COMP_MIPS | PRID_IMP_4KC); 156 } 157 158 /* Handle labels (which must be positive integers). */ 159 enum label_id { 160 label_second_part = 1, 161 label_leave, 162 label_vmalloc, 163 label_vmalloc_done, 164 label_tlbw_hazard_0, 165 label_split = label_tlbw_hazard_0 + 8, 166 label_tlbl_goaround1, 167 label_tlbl_goaround2, 168 label_nopage_tlbl, 169 label_nopage_tlbs, 170 label_nopage_tlbm, 171 label_smp_pgtable_change, 172 label_r3000_write_probe_fail, 173 label_large_segbits_fault, 174 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 175 label_tlb_huge_update, 176 #endif 177 }; 178 179 UASM_L_LA(_second_part) 180 UASM_L_LA(_leave) 181 UASM_L_LA(_vmalloc) 182 UASM_L_LA(_vmalloc_done) 183 /* _tlbw_hazard_x is handled differently. */ 184 UASM_L_LA(_split) 185 UASM_L_LA(_tlbl_goaround1) 186 UASM_L_LA(_tlbl_goaround2) 187 UASM_L_LA(_nopage_tlbl) 188 UASM_L_LA(_nopage_tlbs) 189 UASM_L_LA(_nopage_tlbm) 190 UASM_L_LA(_smp_pgtable_change) 191 UASM_L_LA(_r3000_write_probe_fail) 192 UASM_L_LA(_large_segbits_fault) 193 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 194 UASM_L_LA(_tlb_huge_update) 195 #endif 196 197 static int hazard_instance; 198 199 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) 200 { 201 switch (instance) { 202 case 0 ... 7: 203 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); 204 return; 205 default: 206 BUG(); 207 } 208 } 209 210 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) 211 { 212 switch (instance) { 213 case 0 ... 7: 214 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); 215 break; 216 default: 217 BUG(); 218 } 219 } 220 221 /* 222 * pgtable bits are assigned dynamically depending on processor feature 223 * and statically based on kernel configuration. This spits out the actual 224 * values the kernel is using. Required to make sense from disassembled 225 * TLB exception handlers. 226 */ 227 static void output_pgtable_bits_defines(void) 228 { 229 #define pr_define(fmt, ...) \ 230 pr_debug("#define " fmt, ##__VA_ARGS__) 231 232 pr_debug("#include <asm/asm.h>\n"); 233 pr_debug("#include <asm/regdef.h>\n"); 234 pr_debug("\n"); 235 236 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); 237 pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT); 238 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); 239 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); 240 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); 241 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 242 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); 243 pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT); 244 #endif 245 #ifdef CONFIG_CPU_MIPSR2 246 if (cpu_has_rixi) { 247 #ifdef _PAGE_NO_EXEC_SHIFT 248 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); 249 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); 250 #endif 251 } 252 #endif 253 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); 254 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); 255 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); 256 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); 257 pr_debug("\n"); 258 } 259 260 static inline void dump_handler(const char *symbol, const u32 *handler, int count) 261 { 262 int i; 263 264 pr_debug("LEAF(%s)\n", symbol); 265 266 pr_debug("\t.set push\n"); 267 pr_debug("\t.set noreorder\n"); 268 269 for (i = 0; i < count; i++) 270 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); 271 272 pr_debug("\t.set\tpop\n"); 273 274 pr_debug("\tEND(%s)\n", symbol); 275 } 276 277 /* The only general purpose registers allowed in TLB handlers. */ 278 #define K0 26 279 #define K1 27 280 281 /* Some CP0 registers */ 282 #define C0_INDEX 0, 0 283 #define C0_ENTRYLO0 2, 0 284 #define C0_TCBIND 2, 2 285 #define C0_ENTRYLO1 3, 0 286 #define C0_CONTEXT 4, 0 287 #define C0_PAGEMASK 5, 0 288 #define C0_BADVADDR 8, 0 289 #define C0_ENTRYHI 10, 0 290 #define C0_EPC 14, 0 291 #define C0_XCONTEXT 20, 0 292 293 #ifdef CONFIG_64BIT 294 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) 295 #else 296 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) 297 #endif 298 299 /* The worst case length of the handler is around 18 instructions for 300 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 301 * Maximum space available is 32 instructions for R3000 and 64 302 * instructions for R4000. 303 * 304 * We deliberately chose a buffer size of 128, so we won't scribble 305 * over anything important on overflow before we panic. 306 */ 307 static u32 tlb_handler[128]; 308 309 /* simply assume worst case size for labels and relocs */ 310 static struct uasm_label labels[128]; 311 static struct uasm_reloc relocs[128]; 312 313 static int check_for_high_segbits; 314 static bool fill_includes_sw_bits; 315 316 static unsigned int kscratch_used_mask; 317 318 static inline int __maybe_unused c0_kscratch(void) 319 { 320 switch (current_cpu_type()) { 321 case CPU_XLP: 322 case CPU_XLR: 323 return 22; 324 default: 325 return 31; 326 } 327 } 328 329 static int allocate_kscratch(void) 330 { 331 int r; 332 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; 333 334 r = ffs(a); 335 336 if (r == 0) 337 return -1; 338 339 r--; /* make it zero based */ 340 341 kscratch_used_mask |= (1 << r); 342 343 return r; 344 } 345 346 static int scratch_reg; 347 static int pgd_reg; 348 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; 349 350 static struct work_registers build_get_work_registers(u32 **p) 351 { 352 struct work_registers r; 353 354 if (scratch_reg >= 0) { 355 /* Save in CPU local C0_KScratch? */ 356 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); 357 r.r1 = K0; 358 r.r2 = K1; 359 r.r3 = 1; 360 return r; 361 } 362 363 if (num_possible_cpus() > 1) { 364 /* Get smp_processor_id */ 365 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); 366 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); 367 368 /* handler_reg_save index in K0 */ 369 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); 370 371 UASM_i_LA(p, K1, (long)&handler_reg_save); 372 UASM_i_ADDU(p, K0, K0, K1); 373 } else { 374 UASM_i_LA(p, K0, (long)&handler_reg_save); 375 } 376 /* K0 now points to save area, save $1 and $2 */ 377 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); 378 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); 379 380 r.r1 = K1; 381 r.r2 = 1; 382 r.r3 = 2; 383 return r; 384 } 385 386 static void build_restore_work_registers(u32 **p) 387 { 388 if (scratch_reg >= 0) { 389 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 390 return; 391 } 392 /* K0 already points to save area, restore $1 and $2 */ 393 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); 394 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); 395 } 396 397 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 398 399 /* 400 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, 401 * we cannot do r3000 under these circumstances. 402 * 403 * Declare pgd_current here instead of including mmu_context.h to avoid type 404 * conflicts for tlbmiss_handler_setup_pgd 405 */ 406 extern unsigned long pgd_current[]; 407 408 /* 409 * The R3000 TLB handler is simple. 410 */ 411 static void build_r3000_tlb_refill_handler(void) 412 { 413 long pgdc = (long)pgd_current; 414 u32 *p; 415 416 memset(tlb_handler, 0, sizeof(tlb_handler)); 417 p = tlb_handler; 418 419 uasm_i_mfc0(&p, K0, C0_BADVADDR); 420 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ 421 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); 422 uasm_i_srl(&p, K0, K0, 22); /* load delay */ 423 uasm_i_sll(&p, K0, K0, 2); 424 uasm_i_addu(&p, K1, K1, K0); 425 uasm_i_mfc0(&p, K0, C0_CONTEXT); 426 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ 427 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ 428 uasm_i_addu(&p, K1, K1, K0); 429 uasm_i_lw(&p, K0, 0, K1); 430 uasm_i_nop(&p); /* load delay */ 431 uasm_i_mtc0(&p, K0, C0_ENTRYLO0); 432 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 433 uasm_i_tlbwr(&p); /* cp0 delay */ 434 uasm_i_jr(&p, K1); 435 uasm_i_rfe(&p); /* branch delay */ 436 437 if (p > tlb_handler + 32) 438 panic("TLB refill handler space exceeded"); 439 440 pr_debug("Wrote TLB refill handler (%u instructions).\n", 441 (unsigned int)(p - tlb_handler)); 442 443 memcpy((void *)ebase, tlb_handler, 0x80); 444 local_flush_icache_range(ebase, ebase + 0x80); 445 446 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32); 447 } 448 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 449 450 /* 451 * The R4000 TLB handler is much more complicated. We have two 452 * consecutive handler areas with 32 instructions space each. 453 * Since they aren't used at the same time, we can overflow in the 454 * other one.To keep things simple, we first assume linear space, 455 * then we relocate it to the final handler layout as needed. 456 */ 457 static u32 final_handler[64]; 458 459 /* 460 * Hazards 461 * 462 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 463 * 2. A timing hazard exists for the TLBP instruction. 464 * 465 * stalling_instruction 466 * TLBP 467 * 468 * The JTLB is being read for the TLBP throughout the stall generated by the 469 * previous instruction. This is not really correct as the stalling instruction 470 * can modify the address used to access the JTLB. The failure symptom is that 471 * the TLBP instruction will use an address created for the stalling instruction 472 * and not the address held in C0_ENHI and thus report the wrong results. 473 * 474 * The software work-around is to not allow the instruction preceding the TLBP 475 * to stall - make it an NOP or some other instruction guaranteed not to stall. 476 * 477 * Errata 2 will not be fixed. This errata is also on the R5000. 478 * 479 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 480 */ 481 static void __maybe_unused build_tlb_probe_entry(u32 **p) 482 { 483 switch (current_cpu_type()) { 484 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ 485 case CPU_R4600: 486 case CPU_R4700: 487 case CPU_R5000: 488 case CPU_NEVADA: 489 uasm_i_nop(p); 490 uasm_i_tlbp(p); 491 break; 492 493 default: 494 uasm_i_tlbp(p); 495 break; 496 } 497 } 498 499 /* 500 * Write random or indexed TLB entry, and care about the hazards from 501 * the preceding mtc0 and for the following eret. 502 */ 503 enum tlb_write_entry { tlb_random, tlb_indexed }; 504 505 static void build_tlb_write_entry(u32 **p, struct uasm_label **l, 506 struct uasm_reloc **r, 507 enum tlb_write_entry wmode) 508 { 509 void(*tlbw)(u32 **) = NULL; 510 511 switch (wmode) { 512 case tlb_random: tlbw = uasm_i_tlbwr; break; 513 case tlb_indexed: tlbw = uasm_i_tlbwi; break; 514 } 515 516 if (cpu_has_mips_r2_r6) { 517 if (cpu_has_mips_r2_exec_hazard) 518 uasm_i_ehb(p); 519 tlbw(p); 520 return; 521 } 522 523 switch (current_cpu_type()) { 524 case CPU_R4000PC: 525 case CPU_R4000SC: 526 case CPU_R4000MC: 527 case CPU_R4400PC: 528 case CPU_R4400SC: 529 case CPU_R4400MC: 530 /* 531 * This branch uses up a mtc0 hazard nop slot and saves 532 * two nops after the tlbw instruction. 533 */ 534 uasm_bgezl_hazard(p, r, hazard_instance); 535 tlbw(p); 536 uasm_bgezl_label(l, p, hazard_instance); 537 hazard_instance++; 538 uasm_i_nop(p); 539 break; 540 541 case CPU_R4600: 542 case CPU_R4700: 543 uasm_i_nop(p); 544 tlbw(p); 545 uasm_i_nop(p); 546 break; 547 548 case CPU_R5000: 549 case CPU_NEVADA: 550 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 551 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 552 tlbw(p); 553 break; 554 555 case CPU_R4300: 556 case CPU_5KC: 557 case CPU_TX49XX: 558 case CPU_PR4450: 559 case CPU_XLR: 560 uasm_i_nop(p); 561 tlbw(p); 562 break; 563 564 case CPU_R10000: 565 case CPU_R12000: 566 case CPU_R14000: 567 case CPU_R16000: 568 case CPU_4KC: 569 case CPU_4KEC: 570 case CPU_M14KC: 571 case CPU_M14KEC: 572 case CPU_SB1: 573 case CPU_SB1A: 574 case CPU_4KSC: 575 case CPU_20KC: 576 case CPU_25KF: 577 case CPU_BMIPS32: 578 case CPU_BMIPS3300: 579 case CPU_BMIPS4350: 580 case CPU_BMIPS4380: 581 case CPU_BMIPS5000: 582 case CPU_LOONGSON2: 583 case CPU_LOONGSON3: 584 case CPU_R5500: 585 if (m4kc_tlbp_war()) 586 uasm_i_nop(p); 587 case CPU_ALCHEMY: 588 tlbw(p); 589 break; 590 591 case CPU_RM7000: 592 uasm_i_nop(p); 593 uasm_i_nop(p); 594 uasm_i_nop(p); 595 uasm_i_nop(p); 596 tlbw(p); 597 break; 598 599 case CPU_VR4111: 600 case CPU_VR4121: 601 case CPU_VR4122: 602 case CPU_VR4181: 603 case CPU_VR4181A: 604 uasm_i_nop(p); 605 uasm_i_nop(p); 606 tlbw(p); 607 uasm_i_nop(p); 608 uasm_i_nop(p); 609 break; 610 611 case CPU_VR4131: 612 case CPU_VR4133: 613 case CPU_R5432: 614 uasm_i_nop(p); 615 uasm_i_nop(p); 616 tlbw(p); 617 break; 618 619 case CPU_JZRISC: 620 tlbw(p); 621 uasm_i_nop(p); 622 break; 623 624 default: 625 panic("No TLB refill handler yet (CPU type: %d)", 626 current_cpu_type()); 627 break; 628 } 629 } 630 631 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, 632 unsigned int reg) 633 { 634 if (cpu_has_rixi && _PAGE_NO_EXEC) { 635 if (fill_includes_sw_bits) { 636 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); 637 } else { 638 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); 639 UASM_i_ROTR(p, reg, reg, 640 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); 641 } 642 } else { 643 #ifdef CONFIG_PHYS_ADDR_T_64BIT 644 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); 645 #else 646 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); 647 #endif 648 } 649 } 650 651 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 652 653 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, 654 unsigned int tmp, enum label_id lid, 655 int restore_scratch) 656 { 657 if (restore_scratch) { 658 /* Reset default page size */ 659 if (PM_DEFAULT_MASK >> 16) { 660 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 661 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 662 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 663 uasm_il_b(p, r, lid); 664 } else if (PM_DEFAULT_MASK) { 665 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 666 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 667 uasm_il_b(p, r, lid); 668 } else { 669 uasm_i_mtc0(p, 0, C0_PAGEMASK); 670 uasm_il_b(p, r, lid); 671 } 672 if (scratch_reg >= 0) 673 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 674 else 675 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 676 } else { 677 /* Reset default page size */ 678 if (PM_DEFAULT_MASK >> 16) { 679 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 680 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 681 uasm_il_b(p, r, lid); 682 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 683 } else if (PM_DEFAULT_MASK) { 684 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 685 uasm_il_b(p, r, lid); 686 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 687 } else { 688 uasm_il_b(p, r, lid); 689 uasm_i_mtc0(p, 0, C0_PAGEMASK); 690 } 691 } 692 } 693 694 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, 695 struct uasm_reloc **r, 696 unsigned int tmp, 697 enum tlb_write_entry wmode, 698 int restore_scratch) 699 { 700 /* Set huge page tlb entry size */ 701 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); 702 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); 703 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 704 705 build_tlb_write_entry(p, l, r, wmode); 706 707 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); 708 } 709 710 /* 711 * Check if Huge PTE is present, if so then jump to LABEL. 712 */ 713 static void 714 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, 715 unsigned int pmd, int lid) 716 { 717 UASM_i_LW(p, tmp, 0, pmd); 718 if (use_bbit_insns()) { 719 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); 720 } else { 721 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); 722 uasm_il_bnez(p, r, tmp, lid); 723 } 724 } 725 726 static void build_huge_update_entries(u32 **p, unsigned int pte, 727 unsigned int tmp) 728 { 729 int small_sequence; 730 731 /* 732 * A huge PTE describes an area the size of the 733 * configured huge page size. This is twice the 734 * of the large TLB entry size we intend to use. 735 * A TLB entry half the size of the configured 736 * huge page size is configured into entrylo0 737 * and entrylo1 to cover the contiguous huge PTE 738 * address space. 739 */ 740 small_sequence = (HPAGE_SIZE >> 7) < 0x10000; 741 742 /* We can clobber tmp. It isn't used after this.*/ 743 if (!small_sequence) 744 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); 745 746 build_convert_pte_to_entrylo(p, pte); 747 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ 748 /* convert to entrylo1 */ 749 if (small_sequence) 750 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); 751 else 752 UASM_i_ADDU(p, pte, pte, tmp); 753 754 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ 755 } 756 757 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, 758 struct uasm_label **l, 759 unsigned int pte, 760 unsigned int ptr) 761 { 762 #ifdef CONFIG_SMP 763 UASM_i_SC(p, pte, 0, ptr); 764 uasm_il_beqz(p, r, pte, label_tlb_huge_update); 765 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ 766 #else 767 UASM_i_SW(p, pte, 0, ptr); 768 #endif 769 build_huge_update_entries(p, pte, ptr); 770 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); 771 } 772 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 773 774 #ifdef CONFIG_64BIT 775 /* 776 * TMP and PTR are scratch. 777 * TMP will be clobbered, PTR will hold the pmd entry. 778 */ 779 static void 780 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 781 unsigned int tmp, unsigned int ptr) 782 { 783 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 784 long pgdc = (long)pgd_current; 785 #endif 786 /* 787 * The vmalloc handling is not in the hotpath. 788 */ 789 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 790 791 if (check_for_high_segbits) { 792 /* 793 * The kernel currently implicitely assumes that the 794 * MIPS SEGBITS parameter for the processor is 795 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never 796 * allocate virtual addresses outside the maximum 797 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But 798 * that doesn't prevent user code from accessing the 799 * higher xuseg addresses. Here, we make sure that 800 * everything but the lower xuseg addresses goes down 801 * the module_alloc/vmalloc path. 802 */ 803 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 804 uasm_il_bnez(p, r, ptr, label_vmalloc); 805 } else { 806 uasm_il_bltz(p, r, tmp, label_vmalloc); 807 } 808 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 809 810 if (pgd_reg != -1) { 811 /* pgd is in pgd_reg */ 812 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 813 } else { 814 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT) 815 /* 816 * &pgd << 11 stored in CONTEXT [23..63]. 817 */ 818 UASM_i_MFC0(p, ptr, C0_CONTEXT); 819 820 /* Clear lower 23 bits of context. */ 821 uasm_i_dins(p, ptr, 0, 0, 23); 822 823 /* 1 0 1 0 1 << 6 xkphys cached */ 824 uasm_i_ori(p, ptr, ptr, 0x540); 825 uasm_i_drotr(p, ptr, ptr, 11); 826 #elif defined(CONFIG_SMP) 827 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); 828 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 829 UASM_i_LA_mostly(p, tmp, pgdc); 830 uasm_i_daddu(p, ptr, ptr, tmp); 831 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 832 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 833 #else 834 UASM_i_LA_mostly(p, ptr, pgdc); 835 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 836 #endif 837 } 838 839 uasm_l_vmalloc_done(l, *p); 840 841 /* get pgd offset in bytes */ 842 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); 843 844 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 845 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 846 #ifndef __PAGETABLE_PMD_FOLDED 847 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 848 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 849 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 850 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 851 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 852 #endif 853 } 854 855 /* 856 * BVADDR is the faulting address, PTR is scratch. 857 * PTR will hold the pgd for vmalloc. 858 */ 859 static void 860 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 861 unsigned int bvaddr, unsigned int ptr, 862 enum vmalloc64_mode mode) 863 { 864 long swpd = (long)swapper_pg_dir; 865 int single_insn_swpd; 866 int did_vmalloc_branch = 0; 867 868 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); 869 870 uasm_l_vmalloc(l, *p); 871 872 if (mode != not_refill && check_for_high_segbits) { 873 if (single_insn_swpd) { 874 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); 875 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 876 did_vmalloc_branch = 1; 877 /* fall through */ 878 } else { 879 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); 880 } 881 } 882 if (!did_vmalloc_branch) { 883 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { 884 uasm_il_b(p, r, label_vmalloc_done); 885 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 886 } else { 887 UASM_i_LA_mostly(p, ptr, swpd); 888 uasm_il_b(p, r, label_vmalloc_done); 889 if (uasm_in_compat_space_p(swpd)) 890 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); 891 else 892 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); 893 } 894 } 895 if (mode != not_refill && check_for_high_segbits) { 896 uasm_l_large_segbits_fault(l, *p); 897 /* 898 * We get here if we are an xsseg address, or if we are 899 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. 900 * 901 * Ignoring xsseg (assume disabled so would generate 902 * (address errors?), the only remaining possibility 903 * is the upper xuseg addresses. On processors with 904 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these 905 * addresses would have taken an address error. We try 906 * to mimic that here by taking a load/istream page 907 * fault. 908 */ 909 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); 910 uasm_i_jr(p, ptr); 911 912 if (mode == refill_scratch) { 913 if (scratch_reg >= 0) 914 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 915 else 916 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 917 } else { 918 uasm_i_nop(p); 919 } 920 } 921 } 922 923 #else /* !CONFIG_64BIT */ 924 925 /* 926 * TMP and PTR are scratch. 927 * TMP will be clobbered, PTR will hold the pgd entry. 928 */ 929 static void __maybe_unused 930 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 931 { 932 if (pgd_reg != -1) { 933 /* pgd is in pgd_reg */ 934 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); 935 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 936 } else { 937 long pgdc = (long)pgd_current; 938 939 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 940 #ifdef CONFIG_SMP 941 uasm_i_mfc0(p, ptr, SMP_CPUID_REG); 942 UASM_i_LA_mostly(p, tmp, pgdc); 943 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 944 uasm_i_addu(p, ptr, tmp, ptr); 945 #else 946 UASM_i_LA_mostly(p, ptr, pgdc); 947 #endif 948 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 949 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 950 } 951 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 952 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); 953 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 954 } 955 956 #endif /* !CONFIG_64BIT */ 957 958 static void build_adjust_context(u32 **p, unsigned int ctx) 959 { 960 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 961 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 962 963 switch (current_cpu_type()) { 964 case CPU_VR41XX: 965 case CPU_VR4111: 966 case CPU_VR4121: 967 case CPU_VR4122: 968 case CPU_VR4131: 969 case CPU_VR4181: 970 case CPU_VR4181A: 971 case CPU_VR4133: 972 shift += 2; 973 break; 974 975 default: 976 break; 977 } 978 979 if (shift) 980 UASM_i_SRL(p, ctx, ctx, shift); 981 uasm_i_andi(p, ctx, ctx, mask); 982 } 983 984 static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 985 { 986 /* 987 * Bug workaround for the Nevada. It seems as if under certain 988 * circumstances the move from cp0_context might produce a 989 * bogus result when the mfc0 instruction and its consumer are 990 * in a different cacheline or a load instruction, probably any 991 * memory reference, is between them. 992 */ 993 switch (current_cpu_type()) { 994 case CPU_NEVADA: 995 UASM_i_LW(p, ptr, 0, ptr); 996 GET_CONTEXT(p, tmp); /* get context reg */ 997 break; 998 999 default: 1000 GET_CONTEXT(p, tmp); /* get context reg */ 1001 UASM_i_LW(p, ptr, 0, ptr); 1002 break; 1003 } 1004 1005 build_adjust_context(p, tmp); 1006 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1007 } 1008 1009 static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) 1010 { 1011 /* 1012 * 64bit address support (36bit on a 32bit CPU) in a 32bit 1013 * Kernel is a special case. Only a few CPUs use it. 1014 */ 1015 if (config_enabled(CONFIG_PHYS_ADDR_T_64BIT) && !cpu_has_64bits) { 1016 int pte_off_even = sizeof(pte_t) / 2; 1017 int pte_off_odd = pte_off_even + sizeof(pte_t); 1018 #ifdef CONFIG_XPA 1019 const int scratch = 1; /* Our extra working register */ 1020 1021 uasm_i_addu(p, scratch, 0, ptep); 1022 #endif 1023 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */ 1024 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* odd pte */ 1025 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1026 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); 1027 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); 1028 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); 1029 #ifdef CONFIG_XPA 1030 uasm_i_lw(p, tmp, 0, scratch); 1031 uasm_i_lw(p, ptep, sizeof(pte_t), scratch); 1032 uasm_i_lui(p, scratch, 0xff); 1033 uasm_i_ori(p, scratch, scratch, 0xffff); 1034 uasm_i_and(p, tmp, scratch, tmp); 1035 uasm_i_and(p, ptep, scratch, ptep); 1036 uasm_i_mthc0(p, tmp, C0_ENTRYLO0); 1037 uasm_i_mthc0(p, ptep, C0_ENTRYLO1); 1038 #endif 1039 return; 1040 } 1041 1042 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ 1043 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 1044 if (r45k_bvahwbug()) 1045 build_tlb_probe_entry(p); 1046 build_convert_pte_to_entrylo(p, tmp); 1047 if (r4k_250MHZhwbug()) 1048 UASM_i_MTC0(p, 0, C0_ENTRYLO0); 1049 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ 1050 build_convert_pte_to_entrylo(p, ptep); 1051 if (r45k_bvahwbug()) 1052 uasm_i_mfc0(p, tmp, C0_INDEX); 1053 if (r4k_250MHZhwbug()) 1054 UASM_i_MTC0(p, 0, C0_ENTRYLO1); 1055 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ 1056 } 1057 1058 struct mips_huge_tlb_info { 1059 int huge_pte; 1060 int restore_scratch; 1061 bool need_reload_pte; 1062 }; 1063 1064 static struct mips_huge_tlb_info 1065 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, 1066 struct uasm_reloc **r, unsigned int tmp, 1067 unsigned int ptr, int c0_scratch_reg) 1068 { 1069 struct mips_huge_tlb_info rv; 1070 unsigned int even, odd; 1071 int vmalloc_branch_delay_filled = 0; 1072 const int scratch = 1; /* Our extra working register */ 1073 1074 rv.huge_pte = scratch; 1075 rv.restore_scratch = 0; 1076 rv.need_reload_pte = false; 1077 1078 if (check_for_high_segbits) { 1079 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1080 1081 if (pgd_reg != -1) 1082 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1083 else 1084 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1085 1086 if (c0_scratch_reg >= 0) 1087 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1088 else 1089 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1090 1091 uasm_i_dsrl_safe(p, scratch, tmp, 1092 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1093 uasm_il_bnez(p, r, scratch, label_vmalloc); 1094 1095 if (pgd_reg == -1) { 1096 vmalloc_branch_delay_filled = 1; 1097 /* Clear lower 23 bits of context. */ 1098 uasm_i_dins(p, ptr, 0, 0, 23); 1099 } 1100 } else { 1101 if (pgd_reg != -1) 1102 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1103 else 1104 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1105 1106 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1107 1108 if (c0_scratch_reg >= 0) 1109 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1110 else 1111 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1112 1113 if (pgd_reg == -1) 1114 /* Clear lower 23 bits of context. */ 1115 uasm_i_dins(p, ptr, 0, 0, 23); 1116 1117 uasm_il_bltz(p, r, tmp, label_vmalloc); 1118 } 1119 1120 if (pgd_reg == -1) { 1121 vmalloc_branch_delay_filled = 1; 1122 /* 1 0 1 0 1 << 6 xkphys cached */ 1123 uasm_i_ori(p, ptr, ptr, 0x540); 1124 uasm_i_drotr(p, ptr, ptr, 11); 1125 } 1126 1127 #ifdef __PAGETABLE_PMD_FOLDED 1128 #define LOC_PTEP scratch 1129 #else 1130 #define LOC_PTEP ptr 1131 #endif 1132 1133 if (!vmalloc_branch_delay_filled) 1134 /* get pgd offset in bytes */ 1135 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1136 1137 uasm_l_vmalloc_done(l, *p); 1138 1139 /* 1140 * tmp ptr 1141 * fall-through case = badvaddr *pgd_current 1142 * vmalloc case = badvaddr swapper_pg_dir 1143 */ 1144 1145 if (vmalloc_branch_delay_filled) 1146 /* get pgd offset in bytes */ 1147 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1148 1149 #ifdef __PAGETABLE_PMD_FOLDED 1150 GET_CONTEXT(p, tmp); /* get context reg */ 1151 #endif 1152 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); 1153 1154 if (use_lwx_insns()) { 1155 UASM_i_LWX(p, LOC_PTEP, scratch, ptr); 1156 } else { 1157 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ 1158 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ 1159 } 1160 1161 #ifndef __PAGETABLE_PMD_FOLDED 1162 /* get pmd offset in bytes */ 1163 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); 1164 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); 1165 GET_CONTEXT(p, tmp); /* get context reg */ 1166 1167 if (use_lwx_insns()) { 1168 UASM_i_LWX(p, scratch, scratch, ptr); 1169 } else { 1170 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1171 UASM_i_LW(p, scratch, 0, ptr); 1172 } 1173 #endif 1174 /* Adjust the context during the load latency. */ 1175 build_adjust_context(p, tmp); 1176 1177 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1178 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); 1179 /* 1180 * The in the LWX case we don't want to do the load in the 1181 * delay slot. It cannot issue in the same cycle and may be 1182 * speculative and unneeded. 1183 */ 1184 if (use_lwx_insns()) 1185 uasm_i_nop(p); 1186 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 1187 1188 1189 /* build_update_entries */ 1190 if (use_lwx_insns()) { 1191 even = ptr; 1192 odd = tmp; 1193 UASM_i_LWX(p, even, scratch, tmp); 1194 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); 1195 UASM_i_LWX(p, odd, scratch, tmp); 1196 } else { 1197 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ 1198 even = tmp; 1199 odd = ptr; 1200 UASM_i_LW(p, even, 0, ptr); /* get even pte */ 1201 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ 1202 } 1203 if (cpu_has_rixi) { 1204 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); 1205 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1206 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1207 } else { 1208 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); 1209 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1210 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1211 } 1212 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ 1213 1214 if (c0_scratch_reg >= 0) { 1215 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1216 build_tlb_write_entry(p, l, r, tlb_random); 1217 uasm_l_leave(l, *p); 1218 rv.restore_scratch = 1; 1219 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { 1220 build_tlb_write_entry(p, l, r, tlb_random); 1221 uasm_l_leave(l, *p); 1222 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1223 } else { 1224 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1225 build_tlb_write_entry(p, l, r, tlb_random); 1226 uasm_l_leave(l, *p); 1227 rv.restore_scratch = 1; 1228 } 1229 1230 uasm_i_eret(p); /* return from trap */ 1231 1232 return rv; 1233 } 1234 1235 /* 1236 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception 1237 * because EXL == 0. If we wrap, we can also use the 32 instruction 1238 * slots before the XTLB refill exception handler which belong to the 1239 * unused TLB refill exception. 1240 */ 1241 #define MIPS64_REFILL_INSNS 32 1242 1243 static void build_r4000_tlb_refill_handler(void) 1244 { 1245 u32 *p = tlb_handler; 1246 struct uasm_label *l = labels; 1247 struct uasm_reloc *r = relocs; 1248 u32 *f; 1249 unsigned int final_len; 1250 struct mips_huge_tlb_info htlb_info __maybe_unused; 1251 enum vmalloc64_mode vmalloc_mode __maybe_unused; 1252 1253 memset(tlb_handler, 0, sizeof(tlb_handler)); 1254 memset(labels, 0, sizeof(labels)); 1255 memset(relocs, 0, sizeof(relocs)); 1256 memset(final_handler, 0, sizeof(final_handler)); 1257 1258 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { 1259 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, 1260 scratch_reg); 1261 vmalloc_mode = refill_scratch; 1262 } else { 1263 htlb_info.huge_pte = K0; 1264 htlb_info.restore_scratch = 0; 1265 htlb_info.need_reload_pte = true; 1266 vmalloc_mode = refill_noscratch; 1267 /* 1268 * create the plain linear handler 1269 */ 1270 if (bcm1250_m3_war()) { 1271 unsigned int segbits = 44; 1272 1273 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1274 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 1275 uasm_i_xor(&p, K0, K0, K1); 1276 uasm_i_dsrl_safe(&p, K1, K0, 62); 1277 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 1278 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 1279 uasm_i_or(&p, K0, K0, K1); 1280 uasm_il_bnez(&p, &r, K0, label_leave); 1281 /* No need for uasm_i_nop */ 1282 } 1283 1284 #ifdef CONFIG_64BIT 1285 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1286 #else 1287 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1288 #endif 1289 1290 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1291 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); 1292 #endif 1293 1294 build_get_ptep(&p, K0, K1); 1295 build_update_entries(&p, K0, K1); 1296 build_tlb_write_entry(&p, &l, &r, tlb_random); 1297 uasm_l_leave(&l, p); 1298 uasm_i_eret(&p); /* return from trap */ 1299 } 1300 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1301 uasm_l_tlb_huge_update(&l, p); 1302 if (htlb_info.need_reload_pte) 1303 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1); 1304 build_huge_update_entries(&p, htlb_info.huge_pte, K1); 1305 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, 1306 htlb_info.restore_scratch); 1307 #endif 1308 1309 #ifdef CONFIG_64BIT 1310 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); 1311 #endif 1312 1313 /* 1314 * Overflow check: For the 64bit handler, we need at least one 1315 * free instruction slot for the wrap-around branch. In worst 1316 * case, if the intended insertion point is a delay slot, we 1317 * need three, with the second nop'ed and the third being 1318 * unused. 1319 */ 1320 switch (boot_cpu_type()) { 1321 default: 1322 if (sizeof(long) == 4) { 1323 case CPU_LOONGSON2: 1324 /* Loongson2 ebase is different than r4k, we have more space */ 1325 if ((p - tlb_handler) > 64) 1326 panic("TLB refill handler space exceeded"); 1327 /* 1328 * Now fold the handler in the TLB refill handler space. 1329 */ 1330 f = final_handler; 1331 /* Simplest case, just copy the handler. */ 1332 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1333 final_len = p - tlb_handler; 1334 break; 1335 } else { 1336 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) 1337 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) 1338 && uasm_insn_has_bdelay(relocs, 1339 tlb_handler + MIPS64_REFILL_INSNS - 3))) 1340 panic("TLB refill handler space exceeded"); 1341 /* 1342 * Now fold the handler in the TLB refill handler space. 1343 */ 1344 f = final_handler + MIPS64_REFILL_INSNS; 1345 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { 1346 /* Just copy the handler. */ 1347 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1348 final_len = p - tlb_handler; 1349 } else { 1350 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1351 const enum label_id ls = label_tlb_huge_update; 1352 #else 1353 const enum label_id ls = label_vmalloc; 1354 #endif 1355 u32 *split; 1356 int ov = 0; 1357 int i; 1358 1359 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) 1360 ; 1361 BUG_ON(i == ARRAY_SIZE(labels)); 1362 split = labels[i].addr; 1363 1364 /* 1365 * See if we have overflown one way or the other. 1366 */ 1367 if (split > tlb_handler + MIPS64_REFILL_INSNS || 1368 split < p - MIPS64_REFILL_INSNS) 1369 ov = 1; 1370 1371 if (ov) { 1372 /* 1373 * Split two instructions before the end. One 1374 * for the branch and one for the instruction 1375 * in the delay slot. 1376 */ 1377 split = tlb_handler + MIPS64_REFILL_INSNS - 2; 1378 1379 /* 1380 * If the branch would fall in a delay slot, 1381 * we must back up an additional instruction 1382 * so that it is no longer in a delay slot. 1383 */ 1384 if (uasm_insn_has_bdelay(relocs, split - 1)) 1385 split--; 1386 } 1387 /* Copy first part of the handler. */ 1388 uasm_copy_handler(relocs, labels, tlb_handler, split, f); 1389 f += split - tlb_handler; 1390 1391 if (ov) { 1392 /* Insert branch. */ 1393 uasm_l_split(&l, final_handler); 1394 uasm_il_b(&f, &r, label_split); 1395 if (uasm_insn_has_bdelay(relocs, split)) 1396 uasm_i_nop(&f); 1397 else { 1398 uasm_copy_handler(relocs, labels, 1399 split, split + 1, f); 1400 uasm_move_labels(labels, f, f + 1, -1); 1401 f++; 1402 split++; 1403 } 1404 } 1405 1406 /* Copy the rest of the handler. */ 1407 uasm_copy_handler(relocs, labels, split, p, final_handler); 1408 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + 1409 (p - split); 1410 } 1411 } 1412 break; 1413 } 1414 1415 uasm_resolve_relocs(relocs, labels); 1416 pr_debug("Wrote TLB refill handler (%u instructions).\n", 1417 final_len); 1418 1419 memcpy((void *)ebase, final_handler, 0x100); 1420 local_flush_icache_range(ebase, ebase + 0x100); 1421 1422 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); 1423 } 1424 1425 extern u32 handle_tlbl[], handle_tlbl_end[]; 1426 extern u32 handle_tlbs[], handle_tlbs_end[]; 1427 extern u32 handle_tlbm[], handle_tlbm_end[]; 1428 extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[]; 1429 extern u32 tlbmiss_handler_setup_pgd_end[]; 1430 1431 static void build_setup_pgd(void) 1432 { 1433 const int a0 = 4; 1434 const int __maybe_unused a1 = 5; 1435 const int __maybe_unused a2 = 6; 1436 u32 *p = tlbmiss_handler_setup_pgd_start; 1437 const int tlbmiss_handler_setup_pgd_size = 1438 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start; 1439 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1440 long pgdc = (long)pgd_current; 1441 #endif 1442 1443 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * 1444 sizeof(tlbmiss_handler_setup_pgd[0])); 1445 memset(labels, 0, sizeof(labels)); 1446 memset(relocs, 0, sizeof(relocs)); 1447 pgd_reg = allocate_kscratch(); 1448 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 1449 if (pgd_reg == -1) { 1450 struct uasm_label *l = labels; 1451 struct uasm_reloc *r = relocs; 1452 1453 /* PGD << 11 in c0_Context */ 1454 /* 1455 * If it is a ckseg0 address, convert to a physical 1456 * address. Shifting right by 29 and adding 4 will 1457 * result in zero for these addresses. 1458 * 1459 */ 1460 UASM_i_SRA(&p, a1, a0, 29); 1461 UASM_i_ADDIU(&p, a1, a1, 4); 1462 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); 1463 uasm_i_nop(&p); 1464 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); 1465 uasm_l_tlbl_goaround1(&l, p); 1466 UASM_i_SLL(&p, a0, a0, 11); 1467 uasm_i_jr(&p, 31); 1468 UASM_i_MTC0(&p, a0, C0_CONTEXT); 1469 } else { 1470 /* PGD in c0_KScratch */ 1471 uasm_i_jr(&p, 31); 1472 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1473 } 1474 #else 1475 #ifdef CONFIG_SMP 1476 /* Save PGD to pgd_current[smp_processor_id()] */ 1477 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); 1478 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); 1479 UASM_i_LA_mostly(&p, a2, pgdc); 1480 UASM_i_ADDU(&p, a2, a2, a1); 1481 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1482 #else 1483 UASM_i_LA_mostly(&p, a2, pgdc); 1484 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1485 #endif /* SMP */ 1486 uasm_i_jr(&p, 31); 1487 1488 /* if pgd_reg is allocated, save PGD also to scratch register */ 1489 if (pgd_reg != -1) 1490 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1491 else 1492 uasm_i_nop(&p); 1493 #endif 1494 if (p >= tlbmiss_handler_setup_pgd_end) 1495 panic("tlbmiss_handler_setup_pgd space exceeded"); 1496 1497 uasm_resolve_relocs(relocs, labels); 1498 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", 1499 (unsigned int)(p - tlbmiss_handler_setup_pgd)); 1500 1501 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, 1502 tlbmiss_handler_setup_pgd_size); 1503 } 1504 1505 static void 1506 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) 1507 { 1508 #ifdef CONFIG_SMP 1509 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1510 if (cpu_has_64bits) 1511 uasm_i_lld(p, pte, 0, ptr); 1512 else 1513 # endif 1514 UASM_i_LL(p, pte, 0, ptr); 1515 #else 1516 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1517 if (cpu_has_64bits) 1518 uasm_i_ld(p, pte, 0, ptr); 1519 else 1520 # endif 1521 UASM_i_LW(p, pte, 0, ptr); 1522 #endif 1523 } 1524 1525 static void 1526 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, 1527 unsigned int mode) 1528 { 1529 #ifdef CONFIG_PHYS_ADDR_T_64BIT 1530 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1531 1532 if (!cpu_has_64bits) { 1533 const int scratch = 1; /* Our extra working register */ 1534 1535 uasm_i_lui(p, scratch, (mode >> 16)); 1536 uasm_i_or(p, pte, pte, scratch); 1537 } else 1538 #endif 1539 uasm_i_ori(p, pte, pte, mode); 1540 #ifdef CONFIG_SMP 1541 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1542 if (cpu_has_64bits) 1543 uasm_i_scd(p, pte, 0, ptr); 1544 else 1545 # endif 1546 UASM_i_SC(p, pte, 0, ptr); 1547 1548 if (r10000_llsc_war()) 1549 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); 1550 else 1551 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1552 1553 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1554 if (!cpu_has_64bits) { 1555 /* no uasm_i_nop needed */ 1556 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1557 uasm_i_ori(p, pte, pte, hwmode); 1558 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1559 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1560 /* no uasm_i_nop needed */ 1561 uasm_i_lw(p, pte, 0, ptr); 1562 } else 1563 uasm_i_nop(p); 1564 # else 1565 uasm_i_nop(p); 1566 # endif 1567 #else 1568 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1569 if (cpu_has_64bits) 1570 uasm_i_sd(p, pte, 0, ptr); 1571 else 1572 # endif 1573 UASM_i_SW(p, pte, 0, ptr); 1574 1575 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1576 if (!cpu_has_64bits) { 1577 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1578 uasm_i_ori(p, pte, pte, hwmode); 1579 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1580 uasm_i_lw(p, pte, 0, ptr); 1581 } 1582 # endif 1583 #endif 1584 } 1585 1586 /* 1587 * Check if PTE is present, if not then jump to LABEL. PTR points to 1588 * the page table where this PTE is located, PTE will be re-loaded 1589 * with it's original value. 1590 */ 1591 static void 1592 build_pte_present(u32 **p, struct uasm_reloc **r, 1593 int pte, int ptr, int scratch, enum label_id lid) 1594 { 1595 int t = scratch >= 0 ? scratch : pte; 1596 int cur = pte; 1597 1598 if (cpu_has_rixi) { 1599 if (use_bbit_insns()) { 1600 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); 1601 uasm_i_nop(p); 1602 } else { 1603 if (_PAGE_PRESENT_SHIFT) { 1604 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1605 cur = t; 1606 } 1607 uasm_i_andi(p, t, cur, 1); 1608 uasm_il_beqz(p, r, t, lid); 1609 if (pte == t) 1610 /* You lose the SMP race :-(*/ 1611 iPTE_LW(p, pte, ptr); 1612 } 1613 } else { 1614 if (_PAGE_PRESENT_SHIFT) { 1615 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1616 cur = t; 1617 } 1618 uasm_i_andi(p, t, cur, 1619 (_PAGE_PRESENT | _PAGE_READ) >> _PAGE_PRESENT_SHIFT); 1620 uasm_i_xori(p, t, t, 1621 (_PAGE_PRESENT | _PAGE_READ) >> _PAGE_PRESENT_SHIFT); 1622 uasm_il_bnez(p, r, t, lid); 1623 if (pte == t) 1624 /* You lose the SMP race :-(*/ 1625 iPTE_LW(p, pte, ptr); 1626 } 1627 } 1628 1629 /* Make PTE valid, store result in PTR. */ 1630 static void 1631 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, 1632 unsigned int ptr) 1633 { 1634 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 1635 1636 iPTE_SW(p, r, pte, ptr, mode); 1637 } 1638 1639 /* 1640 * Check if PTE can be written to, if not branch to LABEL. Regardless 1641 * restore PTE with value from PTR when done. 1642 */ 1643 static void 1644 build_pte_writable(u32 **p, struct uasm_reloc **r, 1645 unsigned int pte, unsigned int ptr, int scratch, 1646 enum label_id lid) 1647 { 1648 int t = scratch >= 0 ? scratch : pte; 1649 int cur = pte; 1650 1651 if (_PAGE_PRESENT_SHIFT) { 1652 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1653 cur = t; 1654 } 1655 uasm_i_andi(p, t, cur, 1656 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1657 uasm_i_xori(p, t, t, 1658 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1659 uasm_il_bnez(p, r, t, lid); 1660 if (pte == t) 1661 /* You lose the SMP race :-(*/ 1662 iPTE_LW(p, pte, ptr); 1663 else 1664 uasm_i_nop(p); 1665 } 1666 1667 /* Make PTE writable, update software status bits as well, then store 1668 * at PTR. 1669 */ 1670 static void 1671 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, 1672 unsigned int ptr) 1673 { 1674 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 1675 | _PAGE_DIRTY); 1676 1677 iPTE_SW(p, r, pte, ptr, mode); 1678 } 1679 1680 /* 1681 * Check if PTE can be modified, if not branch to LABEL. Regardless 1682 * restore PTE with value from PTR when done. 1683 */ 1684 static void 1685 build_pte_modifiable(u32 **p, struct uasm_reloc **r, 1686 unsigned int pte, unsigned int ptr, int scratch, 1687 enum label_id lid) 1688 { 1689 if (use_bbit_insns()) { 1690 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); 1691 uasm_i_nop(p); 1692 } else { 1693 int t = scratch >= 0 ? scratch : pte; 1694 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT); 1695 uasm_i_andi(p, t, t, 1); 1696 uasm_il_beqz(p, r, t, lid); 1697 if (pte == t) 1698 /* You lose the SMP race :-(*/ 1699 iPTE_LW(p, pte, ptr); 1700 } 1701 } 1702 1703 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1704 1705 1706 /* 1707 * R3000 style TLB load/store/modify handlers. 1708 */ 1709 1710 /* 1711 * This places the pte into ENTRYLO0 and writes it with tlbwi. 1712 * Then it returns. 1713 */ 1714 static void 1715 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 1716 { 1717 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1718 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 1719 uasm_i_tlbwi(p); 1720 uasm_i_jr(p, tmp); 1721 uasm_i_rfe(p); /* branch delay */ 1722 } 1723 1724 /* 1725 * This places the pte into ENTRYLO0 and writes it with tlbwi 1726 * or tlbwr as appropriate. This is because the index register 1727 * may have the probe fail bit set as a result of a trap on a 1728 * kseg2 access, i.e. without refill. Then it returns. 1729 */ 1730 static void 1731 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, 1732 struct uasm_reloc **r, unsigned int pte, 1733 unsigned int tmp) 1734 { 1735 uasm_i_mfc0(p, tmp, C0_INDEX); 1736 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1737 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 1738 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ 1739 uasm_i_tlbwi(p); /* cp0 delay */ 1740 uasm_i_jr(p, tmp); 1741 uasm_i_rfe(p); /* branch delay */ 1742 uasm_l_r3000_write_probe_fail(l, *p); 1743 uasm_i_tlbwr(p); /* cp0 delay */ 1744 uasm_i_jr(p, tmp); 1745 uasm_i_rfe(p); /* branch delay */ 1746 } 1747 1748 static void 1749 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1750 unsigned int ptr) 1751 { 1752 long pgdc = (long)pgd_current; 1753 1754 uasm_i_mfc0(p, pte, C0_BADVADDR); 1755 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ 1756 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 1757 uasm_i_srl(p, pte, pte, 22); /* load delay */ 1758 uasm_i_sll(p, pte, pte, 2); 1759 uasm_i_addu(p, ptr, ptr, pte); 1760 uasm_i_mfc0(p, pte, C0_CONTEXT); 1761 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ 1762 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ 1763 uasm_i_addu(p, ptr, ptr, pte); 1764 uasm_i_lw(p, pte, 0, ptr); 1765 uasm_i_tlbp(p); /* load delay */ 1766 } 1767 1768 static void build_r3000_tlb_load_handler(void) 1769 { 1770 u32 *p = handle_tlbl; 1771 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; 1772 struct uasm_label *l = labels; 1773 struct uasm_reloc *r = relocs; 1774 1775 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); 1776 memset(labels, 0, sizeof(labels)); 1777 memset(relocs, 0, sizeof(relocs)); 1778 1779 build_r3000_tlbchange_handler_head(&p, K0, K1); 1780 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); 1781 uasm_i_nop(&p); /* load delay */ 1782 build_make_valid(&p, &r, K0, K1); 1783 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1784 1785 uasm_l_nopage_tlbl(&l, p); 1786 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1787 uasm_i_nop(&p); 1788 1789 if (p >= handle_tlbl_end) 1790 panic("TLB load handler fastpath space exceeded"); 1791 1792 uasm_resolve_relocs(relocs, labels); 1793 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1794 (unsigned int)(p - handle_tlbl)); 1795 1796 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size); 1797 } 1798 1799 static void build_r3000_tlb_store_handler(void) 1800 { 1801 u32 *p = handle_tlbs; 1802 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; 1803 struct uasm_label *l = labels; 1804 struct uasm_reloc *r = relocs; 1805 1806 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); 1807 memset(labels, 0, sizeof(labels)); 1808 memset(relocs, 0, sizeof(relocs)); 1809 1810 build_r3000_tlbchange_handler_head(&p, K0, K1); 1811 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); 1812 uasm_i_nop(&p); /* load delay */ 1813 build_make_write(&p, &r, K0, K1); 1814 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1815 1816 uasm_l_nopage_tlbs(&l, p); 1817 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1818 uasm_i_nop(&p); 1819 1820 if (p >= handle_tlbs_end) 1821 panic("TLB store handler fastpath space exceeded"); 1822 1823 uasm_resolve_relocs(relocs, labels); 1824 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1825 (unsigned int)(p - handle_tlbs)); 1826 1827 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size); 1828 } 1829 1830 static void build_r3000_tlb_modify_handler(void) 1831 { 1832 u32 *p = handle_tlbm; 1833 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; 1834 struct uasm_label *l = labels; 1835 struct uasm_reloc *r = relocs; 1836 1837 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); 1838 memset(labels, 0, sizeof(labels)); 1839 memset(relocs, 0, sizeof(relocs)); 1840 1841 build_r3000_tlbchange_handler_head(&p, K0, K1); 1842 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); 1843 uasm_i_nop(&p); /* load delay */ 1844 build_make_write(&p, &r, K0, K1); 1845 build_r3000_pte_reload_tlbwi(&p, K0, K1); 1846 1847 uasm_l_nopage_tlbm(&l, p); 1848 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1849 uasm_i_nop(&p); 1850 1851 if (p >= handle_tlbm_end) 1852 panic("TLB modify handler fastpath space exceeded"); 1853 1854 uasm_resolve_relocs(relocs, labels); 1855 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 1856 (unsigned int)(p - handle_tlbm)); 1857 1858 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size); 1859 } 1860 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 1861 1862 /* 1863 * R4000 style TLB load/store/modify handlers. 1864 */ 1865 static struct work_registers 1866 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, 1867 struct uasm_reloc **r) 1868 { 1869 struct work_registers wr = build_get_work_registers(p); 1870 1871 #ifdef CONFIG_64BIT 1872 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ 1873 #else 1874 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ 1875 #endif 1876 1877 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1878 /* 1879 * For huge tlb entries, pmd doesn't contain an address but 1880 * instead contains the tlb pte. Check the PAGE_HUGE bit and 1881 * see if we need to jump to huge tlb processing. 1882 */ 1883 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); 1884 #endif 1885 1886 UASM_i_MFC0(p, wr.r1, C0_BADVADDR); 1887 UASM_i_LW(p, wr.r2, 0, wr.r2); 1888 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 1889 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 1890 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); 1891 1892 #ifdef CONFIG_SMP 1893 uasm_l_smp_pgtable_change(l, *p); 1894 #endif 1895 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ 1896 if (!m4kc_tlbp_war()) { 1897 build_tlb_probe_entry(p); 1898 if (cpu_has_htw) { 1899 /* race condition happens, leaving */ 1900 uasm_i_ehb(p); 1901 uasm_i_mfc0(p, wr.r3, C0_INDEX); 1902 uasm_il_bltz(p, r, wr.r3, label_leave); 1903 uasm_i_nop(p); 1904 } 1905 } 1906 return wr; 1907 } 1908 1909 static void 1910 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, 1911 struct uasm_reloc **r, unsigned int tmp, 1912 unsigned int ptr) 1913 { 1914 uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); 1915 uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); 1916 build_update_entries(p, tmp, ptr); 1917 build_tlb_write_entry(p, l, r, tlb_indexed); 1918 uasm_l_leave(l, *p); 1919 build_restore_work_registers(p); 1920 uasm_i_eret(p); /* return from trap */ 1921 1922 #ifdef CONFIG_64BIT 1923 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); 1924 #endif 1925 } 1926 1927 static void build_r4000_tlb_load_handler(void) 1928 { 1929 u32 *p = handle_tlbl; 1930 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; 1931 struct uasm_label *l = labels; 1932 struct uasm_reloc *r = relocs; 1933 struct work_registers wr; 1934 1935 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); 1936 memset(labels, 0, sizeof(labels)); 1937 memset(relocs, 0, sizeof(relocs)); 1938 1939 if (bcm1250_m3_war()) { 1940 unsigned int segbits = 44; 1941 1942 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1943 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 1944 uasm_i_xor(&p, K0, K0, K1); 1945 uasm_i_dsrl_safe(&p, K1, K0, 62); 1946 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 1947 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 1948 uasm_i_or(&p, K0, K0, K1); 1949 uasm_il_bnez(&p, &r, K0, label_leave); 1950 /* No need for uasm_i_nop */ 1951 } 1952 1953 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 1954 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 1955 if (m4kc_tlbp_war()) 1956 build_tlb_probe_entry(&p); 1957 1958 if (cpu_has_rixi && !cpu_has_rixiex) { 1959 /* 1960 * If the page is not _PAGE_VALID, RI or XI could not 1961 * have triggered it. Skip the expensive test.. 1962 */ 1963 if (use_bbit_insns()) { 1964 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 1965 label_tlbl_goaround1); 1966 } else { 1967 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 1968 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); 1969 } 1970 uasm_i_nop(&p); 1971 1972 uasm_i_tlbr(&p); 1973 1974 switch (current_cpu_type()) { 1975 default: 1976 if (cpu_has_mips_r2_exec_hazard) { 1977 uasm_i_ehb(&p); 1978 1979 case CPU_CAVIUM_OCTEON: 1980 case CPU_CAVIUM_OCTEON_PLUS: 1981 case CPU_CAVIUM_OCTEON2: 1982 break; 1983 } 1984 } 1985 1986 /* Examine entrylo 0 or 1 based on ptr. */ 1987 if (use_bbit_insns()) { 1988 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 1989 } else { 1990 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 1991 uasm_i_beqz(&p, wr.r3, 8); 1992 } 1993 /* load it in the delay slot*/ 1994 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 1995 /* load it if ptr is odd */ 1996 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 1997 /* 1998 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 1999 * XI must have triggered it. 2000 */ 2001 if (use_bbit_insns()) { 2002 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); 2003 uasm_i_nop(&p); 2004 uasm_l_tlbl_goaround1(&l, p); 2005 } else { 2006 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2007 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); 2008 uasm_i_nop(&p); 2009 } 2010 uasm_l_tlbl_goaround1(&l, p); 2011 } 2012 build_make_valid(&p, &r, wr.r1, wr.r2); 2013 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2014 2015 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2016 /* 2017 * This is the entry point when build_r4000_tlbchange_handler_head 2018 * spots a huge page. 2019 */ 2020 uasm_l_tlb_huge_update(&l, p); 2021 iPTE_LW(&p, wr.r1, wr.r2); 2022 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2023 build_tlb_probe_entry(&p); 2024 2025 if (cpu_has_rixi && !cpu_has_rixiex) { 2026 /* 2027 * If the page is not _PAGE_VALID, RI or XI could not 2028 * have triggered it. Skip the expensive test.. 2029 */ 2030 if (use_bbit_insns()) { 2031 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2032 label_tlbl_goaround2); 2033 } else { 2034 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2035 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2036 } 2037 uasm_i_nop(&p); 2038 2039 uasm_i_tlbr(&p); 2040 2041 switch (current_cpu_type()) { 2042 default: 2043 if (cpu_has_mips_r2_exec_hazard) { 2044 uasm_i_ehb(&p); 2045 2046 case CPU_CAVIUM_OCTEON: 2047 case CPU_CAVIUM_OCTEON_PLUS: 2048 case CPU_CAVIUM_OCTEON2: 2049 break; 2050 } 2051 } 2052 2053 /* Examine entrylo 0 or 1 based on ptr. */ 2054 if (use_bbit_insns()) { 2055 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2056 } else { 2057 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2058 uasm_i_beqz(&p, wr.r3, 8); 2059 } 2060 /* load it in the delay slot*/ 2061 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2062 /* load it if ptr is odd */ 2063 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2064 /* 2065 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2066 * XI must have triggered it. 2067 */ 2068 if (use_bbit_insns()) { 2069 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); 2070 } else { 2071 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2072 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2073 } 2074 if (PM_DEFAULT_MASK == 0) 2075 uasm_i_nop(&p); 2076 /* 2077 * We clobbered C0_PAGEMASK, restore it. On the other branch 2078 * it is restored in build_huge_tlb_write_entry. 2079 */ 2080 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); 2081 2082 uasm_l_tlbl_goaround2(&l, p); 2083 } 2084 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); 2085 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); 2086 #endif 2087 2088 uasm_l_nopage_tlbl(&l, p); 2089 build_restore_work_registers(&p); 2090 #ifdef CONFIG_CPU_MICROMIPS 2091 if ((unsigned long)tlb_do_page_fault_0 & 1) { 2092 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); 2093 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); 2094 uasm_i_jr(&p, K0); 2095 } else 2096 #endif 2097 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 2098 uasm_i_nop(&p); 2099 2100 if (p >= handle_tlbl_end) 2101 panic("TLB load handler fastpath space exceeded"); 2102 2103 uasm_resolve_relocs(relocs, labels); 2104 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 2105 (unsigned int)(p - handle_tlbl)); 2106 2107 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size); 2108 } 2109 2110 static void build_r4000_tlb_store_handler(void) 2111 { 2112 u32 *p = handle_tlbs; 2113 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; 2114 struct uasm_label *l = labels; 2115 struct uasm_reloc *r = relocs; 2116 struct work_registers wr; 2117 2118 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); 2119 memset(labels, 0, sizeof(labels)); 2120 memset(relocs, 0, sizeof(relocs)); 2121 2122 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2123 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2124 if (m4kc_tlbp_war()) 2125 build_tlb_probe_entry(&p); 2126 build_make_write(&p, &r, wr.r1, wr.r2); 2127 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2128 2129 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2130 /* 2131 * This is the entry point when 2132 * build_r4000_tlbchange_handler_head spots a huge page. 2133 */ 2134 uasm_l_tlb_huge_update(&l, p); 2135 iPTE_LW(&p, wr.r1, wr.r2); 2136 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2137 build_tlb_probe_entry(&p); 2138 uasm_i_ori(&p, wr.r1, wr.r1, 2139 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2140 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); 2141 #endif 2142 2143 uasm_l_nopage_tlbs(&l, p); 2144 build_restore_work_registers(&p); 2145 #ifdef CONFIG_CPU_MICROMIPS 2146 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2147 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2148 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2149 uasm_i_jr(&p, K0); 2150 } else 2151 #endif 2152 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2153 uasm_i_nop(&p); 2154 2155 if (p >= handle_tlbs_end) 2156 panic("TLB store handler fastpath space exceeded"); 2157 2158 uasm_resolve_relocs(relocs, labels); 2159 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 2160 (unsigned int)(p - handle_tlbs)); 2161 2162 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size); 2163 } 2164 2165 static void build_r4000_tlb_modify_handler(void) 2166 { 2167 u32 *p = handle_tlbm; 2168 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; 2169 struct uasm_label *l = labels; 2170 struct uasm_reloc *r = relocs; 2171 struct work_registers wr; 2172 2173 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); 2174 memset(labels, 0, sizeof(labels)); 2175 memset(relocs, 0, sizeof(relocs)); 2176 2177 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2178 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2179 if (m4kc_tlbp_war()) 2180 build_tlb_probe_entry(&p); 2181 /* Present and writable bits set, set accessed and dirty bits. */ 2182 build_make_write(&p, &r, wr.r1, wr.r2); 2183 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2184 2185 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2186 /* 2187 * This is the entry point when 2188 * build_r4000_tlbchange_handler_head spots a huge page. 2189 */ 2190 uasm_l_tlb_huge_update(&l, p); 2191 iPTE_LW(&p, wr.r1, wr.r2); 2192 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2193 build_tlb_probe_entry(&p); 2194 uasm_i_ori(&p, wr.r1, wr.r1, 2195 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2196 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); 2197 #endif 2198 2199 uasm_l_nopage_tlbm(&l, p); 2200 build_restore_work_registers(&p); 2201 #ifdef CONFIG_CPU_MICROMIPS 2202 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2203 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2204 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2205 uasm_i_jr(&p, K0); 2206 } else 2207 #endif 2208 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2209 uasm_i_nop(&p); 2210 2211 if (p >= handle_tlbm_end) 2212 panic("TLB modify handler fastpath space exceeded"); 2213 2214 uasm_resolve_relocs(relocs, labels); 2215 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2216 (unsigned int)(p - handle_tlbm)); 2217 2218 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size); 2219 } 2220 2221 static void flush_tlb_handlers(void) 2222 { 2223 local_flush_icache_range((unsigned long)handle_tlbl, 2224 (unsigned long)handle_tlbl_end); 2225 local_flush_icache_range((unsigned long)handle_tlbs, 2226 (unsigned long)handle_tlbs_end); 2227 local_flush_icache_range((unsigned long)handle_tlbm, 2228 (unsigned long)handle_tlbm_end); 2229 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, 2230 (unsigned long)tlbmiss_handler_setup_pgd_end); 2231 } 2232 2233 static void print_htw_config(void) 2234 { 2235 unsigned long config; 2236 unsigned int pwctl; 2237 const int field = 2 * sizeof(unsigned long); 2238 2239 config = read_c0_pwfield(); 2240 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n", 2241 field, config, 2242 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT, 2243 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT, 2244 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT, 2245 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT, 2246 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); 2247 2248 config = read_c0_pwsize(); 2249 pr_debug("PWSize (0x%0*lx): GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", 2250 field, config, 2251 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, 2252 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, 2253 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, 2254 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT, 2255 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); 2256 2257 pwctl = read_c0_pwctl(); 2258 pr_debug("PWCtl (0x%x): PWEn: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", 2259 pwctl, 2260 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, 2261 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, 2262 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, 2263 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); 2264 } 2265 2266 static void config_htw_params(void) 2267 { 2268 unsigned long pwfield, pwsize, ptei; 2269 unsigned int config; 2270 2271 /* 2272 * We are using 2-level page tables, so we only need to 2273 * setup GDW and PTW appropriately. UDW and MDW will remain 0. 2274 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to 2275 * write values less than 0xc in these fields because the entire 2276 * write will be dropped. As a result of which, we must preserve 2277 * the original reset values and overwrite only what we really want. 2278 */ 2279 2280 pwfield = read_c0_pwfield(); 2281 /* re-initialize the GDI field */ 2282 pwfield &= ~MIPS_PWFIELD_GDI_MASK; 2283 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT; 2284 /* re-initialize the PTI field including the even/odd bit */ 2285 pwfield &= ~MIPS_PWFIELD_PTI_MASK; 2286 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT; 2287 if (CONFIG_PGTABLE_LEVELS >= 3) { 2288 pwfield &= ~MIPS_PWFIELD_MDI_MASK; 2289 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT; 2290 } 2291 /* Set the PTEI right shift */ 2292 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT; 2293 pwfield |= ptei; 2294 write_c0_pwfield(pwfield); 2295 /* Check whether the PTEI value is supported */ 2296 back_to_back_c0_hazard(); 2297 pwfield = read_c0_pwfield(); 2298 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT) 2299 != ptei) { 2300 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled", 2301 ptei); 2302 /* 2303 * Drop option to avoid HTW being enabled via another path 2304 * (eg htw_reset()) 2305 */ 2306 current_cpu_data.options &= ~MIPS_CPU_HTW; 2307 return; 2308 } 2309 2310 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; 2311 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; 2312 if (CONFIG_PGTABLE_LEVELS >= 3) 2313 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; 2314 2315 /* If XPA has been enabled, PTEs are 64-bit in size. */ 2316 if (config_enabled(CONFIG_64BITS) || (read_c0_pagegrain() & PG_ELPA)) 2317 pwsize |= 1; 2318 2319 write_c0_pwsize(pwsize); 2320 2321 /* Make sure everything is set before we enable the HTW */ 2322 back_to_back_c0_hazard(); 2323 2324 /* Enable HTW and disable the rest of the pwctl fields */ 2325 config = 1 << MIPS_PWCTL_PWEN_SHIFT; 2326 write_c0_pwctl(config); 2327 pr_info("Hardware Page Table Walker enabled\n"); 2328 2329 print_htw_config(); 2330 } 2331 2332 static void config_xpa_params(void) 2333 { 2334 #ifdef CONFIG_XPA 2335 unsigned int pagegrain; 2336 2337 if (mips_xpa_disabled) { 2338 pr_info("Extended Physical Addressing (XPA) disabled\n"); 2339 return; 2340 } 2341 2342 pagegrain = read_c0_pagegrain(); 2343 write_c0_pagegrain(pagegrain | PG_ELPA); 2344 back_to_back_c0_hazard(); 2345 pagegrain = read_c0_pagegrain(); 2346 2347 if (pagegrain & PG_ELPA) 2348 pr_info("Extended Physical Addressing (XPA) enabled\n"); 2349 else 2350 panic("Extended Physical Addressing (XPA) disabled"); 2351 #endif 2352 } 2353 2354 static void check_pabits(void) 2355 { 2356 unsigned long entry; 2357 unsigned pabits, fillbits; 2358 2359 if (!cpu_has_rixi || !_PAGE_NO_EXEC) { 2360 /* 2361 * We'll only be making use of the fact that we can rotate bits 2362 * into the fill if the CPU supports RIXI, so don't bother 2363 * probing this for CPUs which don't. 2364 */ 2365 return; 2366 } 2367 2368 write_c0_entrylo0(~0ul); 2369 back_to_back_c0_hazard(); 2370 entry = read_c0_entrylo0(); 2371 2372 /* clear all non-PFN bits */ 2373 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1); 2374 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); 2375 2376 /* find a lower bound on PABITS, and upper bound on fill bits */ 2377 pabits = fls_long(entry) + 6; 2378 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0); 2379 2380 /* minus the RI & XI bits */ 2381 fillbits -= min_t(unsigned, fillbits, 2); 2382 2383 if (fillbits >= ilog2(_PAGE_NO_EXEC)) 2384 fill_includes_sw_bits = true; 2385 2386 pr_debug("Entry* registers contain %u fill bits\n", fillbits); 2387 } 2388 2389 void build_tlb_refill_handler(void) 2390 { 2391 /* 2392 * The refill handler is generated per-CPU, multi-node systems 2393 * may have local storage for it. The other handlers are only 2394 * needed once. 2395 */ 2396 static int run_once = 0; 2397 2398 output_pgtable_bits_defines(); 2399 check_pabits(); 2400 2401 #ifdef CONFIG_64BIT 2402 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 2403 #endif 2404 2405 switch (current_cpu_type()) { 2406 case CPU_R2000: 2407 case CPU_R3000: 2408 case CPU_R3000A: 2409 case CPU_R3081E: 2410 case CPU_TX3912: 2411 case CPU_TX3922: 2412 case CPU_TX3927: 2413 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 2414 if (cpu_has_local_ebase) 2415 build_r3000_tlb_refill_handler(); 2416 if (!run_once) { 2417 if (!cpu_has_local_ebase) 2418 build_r3000_tlb_refill_handler(); 2419 build_setup_pgd(); 2420 build_r3000_tlb_load_handler(); 2421 build_r3000_tlb_store_handler(); 2422 build_r3000_tlb_modify_handler(); 2423 flush_tlb_handlers(); 2424 run_once++; 2425 } 2426 #else 2427 panic("No R3000 TLB refill handler"); 2428 #endif 2429 break; 2430 2431 case CPU_R6000: 2432 case CPU_R6000A: 2433 panic("No R6000 TLB refill handler yet"); 2434 break; 2435 2436 case CPU_R8000: 2437 panic("No R8000 TLB refill handler yet"); 2438 break; 2439 2440 default: 2441 if (!run_once) { 2442 scratch_reg = allocate_kscratch(); 2443 build_setup_pgd(); 2444 build_r4000_tlb_load_handler(); 2445 build_r4000_tlb_store_handler(); 2446 build_r4000_tlb_modify_handler(); 2447 if (!cpu_has_local_ebase) 2448 build_r4000_tlb_refill_handler(); 2449 flush_tlb_handlers(); 2450 run_once++; 2451 } 2452 if (cpu_has_local_ebase) 2453 build_r4000_tlb_refill_handler(); 2454 if (cpu_has_xpa) 2455 config_xpa_params(); 2456 if (cpu_has_htw) 2457 config_htw_params(); 2458 } 2459 } 2460