1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 * Copyright (C) 2008, 2009 Cavium Networks, Inc. 12 * Copyright (C) 2011 MIPS Technologies, Inc. 13 * 14 * ... and the days got worse and worse and now you see 15 * I've gone completely out of my mind. 16 * 17 * They're coming to take me a away haha 18 * they're coming to take me a away hoho hihi haha 19 * to the funny farm where code is beautiful all the time ... 20 * 21 * (Condolences to Napoleon XIV) 22 */ 23 24 #include <linux/bug.h> 25 #include <linux/export.h> 26 #include <linux/kernel.h> 27 #include <linux/types.h> 28 #include <linux/smp.h> 29 #include <linux/string.h> 30 #include <linux/cache.h> 31 #include <linux/pgtable.h> 32 33 #include <asm/cacheflush.h> 34 #include <asm/cpu-type.h> 35 #include <asm/mmu_context.h> 36 #include <asm/uasm.h> 37 #include <asm/setup.h> 38 #include <asm/tlbex.h> 39 40 static int mips_xpa_disabled; 41 42 static int __init xpa_disable(char *s) 43 { 44 mips_xpa_disabled = 1; 45 46 return 1; 47 } 48 49 __setup("noxpa", xpa_disable); 50 51 /* 52 * TLB load/store/modify handlers. 53 * 54 * Only the fastpath gets synthesized at runtime, the slowpath for 55 * do_page_fault remains normal asm. 56 */ 57 extern void tlb_do_page_fault_0(void); 58 extern void tlb_do_page_fault_1(void); 59 60 struct work_registers { 61 int r1; 62 int r2; 63 int r3; 64 }; 65 66 struct tlb_reg_save { 67 unsigned long a; 68 unsigned long b; 69 } ____cacheline_aligned_in_smp; 70 71 static struct tlb_reg_save handler_reg_save[NR_CPUS]; 72 73 static inline int r45k_bvahwbug(void) 74 { 75 /* XXX: We should probe for the presence of this bug, but we don't. */ 76 return 0; 77 } 78 79 static inline int r4k_250MHZhwbug(void) 80 { 81 /* XXX: We should probe for the presence of this bug, but we don't. */ 82 return 0; 83 } 84 85 extern int sb1250_m3_workaround_needed(void); 86 87 static inline int __maybe_unused bcm1250_m3_war(void) 88 { 89 if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS)) 90 return sb1250_m3_workaround_needed(); 91 return 0; 92 } 93 94 static inline int __maybe_unused r10000_llsc_war(void) 95 { 96 return IS_ENABLED(CONFIG_WAR_R10000_LLSC); 97 } 98 99 static int use_bbit_insns(void) 100 { 101 switch (current_cpu_type()) { 102 case CPU_CAVIUM_OCTEON: 103 case CPU_CAVIUM_OCTEON_PLUS: 104 case CPU_CAVIUM_OCTEON2: 105 case CPU_CAVIUM_OCTEON3: 106 return 1; 107 default: 108 return 0; 109 } 110 } 111 112 static int use_lwx_insns(void) 113 { 114 switch (current_cpu_type()) { 115 case CPU_CAVIUM_OCTEON2: 116 case CPU_CAVIUM_OCTEON3: 117 return 1; 118 default: 119 return 0; 120 } 121 } 122 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ 123 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 124 static bool scratchpad_available(void) 125 { 126 return true; 127 } 128 static int scratchpad_offset(int i) 129 { 130 /* 131 * CVMSEG starts at address -32768 and extends for 132 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. 133 */ 134 i += 1; /* Kernel use starts at the top and works down. */ 135 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; 136 } 137 #else 138 static bool scratchpad_available(void) 139 { 140 return false; 141 } 142 static int scratchpad_offset(int i) 143 { 144 BUG(); 145 /* Really unreachable, but evidently some GCC want this. */ 146 return 0; 147 } 148 #endif 149 /* 150 * Found by experiment: At least some revisions of the 4kc throw under 151 * some circumstances a machine check exception, triggered by invalid 152 * values in the index register. Delaying the tlbp instruction until 153 * after the next branch, plus adding an additional nop in front of 154 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows 155 * why; it's not an issue caused by the core RTL. 156 * 157 */ 158 static int m4kc_tlbp_war(void) 159 { 160 return current_cpu_type() == CPU_4KC; 161 } 162 163 /* Handle labels (which must be positive integers). */ 164 enum label_id { 165 label_second_part = 1, 166 label_leave, 167 label_vmalloc, 168 label_vmalloc_done, 169 label_tlbw_hazard_0, 170 label_split = label_tlbw_hazard_0 + 8, 171 label_tlbl_goaround1, 172 label_tlbl_goaround2, 173 label_nopage_tlbl, 174 label_nopage_tlbs, 175 label_nopage_tlbm, 176 label_smp_pgtable_change, 177 label_r3000_write_probe_fail, 178 label_large_segbits_fault, 179 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 180 label_tlb_huge_update, 181 #endif 182 }; 183 184 UASM_L_LA(_second_part) 185 UASM_L_LA(_leave) 186 UASM_L_LA(_vmalloc) 187 UASM_L_LA(_vmalloc_done) 188 /* _tlbw_hazard_x is handled differently. */ 189 UASM_L_LA(_split) 190 UASM_L_LA(_tlbl_goaround1) 191 UASM_L_LA(_tlbl_goaround2) 192 UASM_L_LA(_nopage_tlbl) 193 UASM_L_LA(_nopage_tlbs) 194 UASM_L_LA(_nopage_tlbm) 195 UASM_L_LA(_smp_pgtable_change) 196 UASM_L_LA(_r3000_write_probe_fail) 197 UASM_L_LA(_large_segbits_fault) 198 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 199 UASM_L_LA(_tlb_huge_update) 200 #endif 201 202 static int hazard_instance; 203 204 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) 205 { 206 switch (instance) { 207 case 0 ... 7: 208 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); 209 return; 210 default: 211 BUG(); 212 } 213 } 214 215 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) 216 { 217 switch (instance) { 218 case 0 ... 7: 219 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); 220 break; 221 default: 222 BUG(); 223 } 224 } 225 226 /* 227 * pgtable bits are assigned dynamically depending on processor feature 228 * and statically based on kernel configuration. This spits out the actual 229 * values the kernel is using. Required to make sense from disassembled 230 * TLB exception handlers. 231 */ 232 static void output_pgtable_bits_defines(void) 233 { 234 #define pr_define(fmt, ...) \ 235 pr_debug("#define " fmt, ##__VA_ARGS__) 236 237 pr_debug("#include <asm/asm.h>\n"); 238 pr_debug("#include <asm/regdef.h>\n"); 239 pr_debug("\n"); 240 241 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); 242 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); 243 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); 244 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); 245 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); 246 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 247 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); 248 #endif 249 #ifdef _PAGE_NO_EXEC_SHIFT 250 if (cpu_has_rixi) 251 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); 252 #endif 253 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); 254 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); 255 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); 256 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); 257 pr_debug("\n"); 258 } 259 260 static inline void dump_handler(const char *symbol, const void *start, const void *end) 261 { 262 unsigned int count = (end - start) / sizeof(u32); 263 const u32 *handler = start; 264 int i; 265 266 pr_debug("LEAF(%s)\n", symbol); 267 268 pr_debug("\t.set push\n"); 269 pr_debug("\t.set noreorder\n"); 270 271 for (i = 0; i < count; i++) 272 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); 273 274 pr_debug("\t.set\tpop\n"); 275 276 pr_debug("\tEND(%s)\n", symbol); 277 } 278 279 /* The only general purpose registers allowed in TLB handlers. */ 280 #define K0 26 281 #define K1 27 282 283 /* Some CP0 registers */ 284 #define C0_INDEX 0, 0 285 #define C0_ENTRYLO0 2, 0 286 #define C0_TCBIND 2, 2 287 #define C0_ENTRYLO1 3, 0 288 #define C0_CONTEXT 4, 0 289 #define C0_PAGEMASK 5, 0 290 #define C0_PWBASE 5, 5 291 #define C0_PWFIELD 5, 6 292 #define C0_PWSIZE 5, 7 293 #define C0_PWCTL 6, 6 294 #define C0_BADVADDR 8, 0 295 #define C0_PGD 9, 7 296 #define C0_ENTRYHI 10, 0 297 #define C0_EPC 14, 0 298 #define C0_XCONTEXT 20, 0 299 300 #ifdef CONFIG_64BIT 301 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) 302 #else 303 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) 304 #endif 305 306 /* The worst case length of the handler is around 18 instructions for 307 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 308 * Maximum space available is 32 instructions for R3000 and 64 309 * instructions for R4000. 310 * 311 * We deliberately chose a buffer size of 128, so we won't scribble 312 * over anything important on overflow before we panic. 313 */ 314 static u32 tlb_handler[128]; 315 316 /* simply assume worst case size for labels and relocs */ 317 static struct uasm_label labels[128]; 318 static struct uasm_reloc relocs[128]; 319 320 static int check_for_high_segbits; 321 static bool fill_includes_sw_bits; 322 323 static unsigned int kscratch_used_mask; 324 325 static inline int __maybe_unused c0_kscratch(void) 326 { 327 return 31; 328 } 329 330 static int allocate_kscratch(void) 331 { 332 int r; 333 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; 334 335 r = ffs(a); 336 337 if (r == 0) 338 return -1; 339 340 r--; /* make it zero based */ 341 342 kscratch_used_mask |= (1 << r); 343 344 return r; 345 } 346 347 static int scratch_reg; 348 int pgd_reg; 349 EXPORT_SYMBOL_GPL(pgd_reg); 350 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; 351 352 static struct work_registers build_get_work_registers(u32 **p) 353 { 354 struct work_registers r; 355 356 if (scratch_reg >= 0) { 357 /* Save in CPU local C0_KScratch? */ 358 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); 359 r.r1 = K0; 360 r.r2 = K1; 361 r.r3 = 1; 362 return r; 363 } 364 365 if (num_possible_cpus() > 1) { 366 /* Get smp_processor_id */ 367 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); 368 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); 369 370 /* handler_reg_save index in K0 */ 371 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); 372 373 UASM_i_LA(p, K1, (long)&handler_reg_save); 374 UASM_i_ADDU(p, K0, K0, K1); 375 } else { 376 UASM_i_LA(p, K0, (long)&handler_reg_save); 377 } 378 /* K0 now points to save area, save $1 and $2 */ 379 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); 380 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); 381 382 r.r1 = K1; 383 r.r2 = 1; 384 r.r3 = 2; 385 return r; 386 } 387 388 static void build_restore_work_registers(u32 **p) 389 { 390 if (scratch_reg >= 0) { 391 uasm_i_ehb(p); 392 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 393 return; 394 } 395 /* K0 already points to save area, restore $1 and $2 */ 396 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); 397 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); 398 } 399 400 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 401 402 /* 403 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, 404 * we cannot do r3000 under these circumstances. 405 * 406 * The R3000 TLB handler is simple. 407 */ 408 static void build_r3000_tlb_refill_handler(void) 409 { 410 long pgdc = (long)pgd_current; 411 u32 *p; 412 413 memset(tlb_handler, 0, sizeof(tlb_handler)); 414 p = tlb_handler; 415 416 uasm_i_mfc0(&p, K0, C0_BADVADDR); 417 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ 418 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); 419 uasm_i_srl(&p, K0, K0, 22); /* load delay */ 420 uasm_i_sll(&p, K0, K0, 2); 421 uasm_i_addu(&p, K1, K1, K0); 422 uasm_i_mfc0(&p, K0, C0_CONTEXT); 423 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ 424 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ 425 uasm_i_addu(&p, K1, K1, K0); 426 uasm_i_lw(&p, K0, 0, K1); 427 uasm_i_nop(&p); /* load delay */ 428 uasm_i_mtc0(&p, K0, C0_ENTRYLO0); 429 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 430 uasm_i_tlbwr(&p); /* cp0 delay */ 431 uasm_i_jr(&p, K1); 432 uasm_i_rfe(&p); /* branch delay */ 433 434 if (p > tlb_handler + 32) 435 panic("TLB refill handler space exceeded"); 436 437 pr_debug("Wrote TLB refill handler (%u instructions).\n", 438 (unsigned int)(p - tlb_handler)); 439 440 memcpy((void *)ebase, tlb_handler, 0x80); 441 local_flush_icache_range(ebase, ebase + 0x80); 442 dump_handler("r3000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x80)); 443 } 444 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 445 446 /* 447 * The R4000 TLB handler is much more complicated. We have two 448 * consecutive handler areas with 32 instructions space each. 449 * Since they aren't used at the same time, we can overflow in the 450 * other one.To keep things simple, we first assume linear space, 451 * then we relocate it to the final handler layout as needed. 452 */ 453 static u32 final_handler[64]; 454 455 /* 456 * Hazards 457 * 458 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 459 * 2. A timing hazard exists for the TLBP instruction. 460 * 461 * stalling_instruction 462 * TLBP 463 * 464 * The JTLB is being read for the TLBP throughout the stall generated by the 465 * previous instruction. This is not really correct as the stalling instruction 466 * can modify the address used to access the JTLB. The failure symptom is that 467 * the TLBP instruction will use an address created for the stalling instruction 468 * and not the address held in C0_ENHI and thus report the wrong results. 469 * 470 * The software work-around is to not allow the instruction preceding the TLBP 471 * to stall - make it an NOP or some other instruction guaranteed not to stall. 472 * 473 * Errata 2 will not be fixed. This errata is also on the R5000. 474 * 475 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 476 */ 477 static void __maybe_unused build_tlb_probe_entry(u32 **p) 478 { 479 switch (current_cpu_type()) { 480 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ 481 case CPU_R4600: 482 case CPU_R4700: 483 case CPU_R5000: 484 case CPU_NEVADA: 485 uasm_i_nop(p); 486 uasm_i_tlbp(p); 487 break; 488 489 default: 490 uasm_i_tlbp(p); 491 break; 492 } 493 } 494 495 void build_tlb_write_entry(u32 **p, struct uasm_label **l, 496 struct uasm_reloc **r, 497 enum tlb_write_entry wmode) 498 { 499 void(*tlbw)(u32 **) = NULL; 500 501 switch (wmode) { 502 case tlb_random: tlbw = uasm_i_tlbwr; break; 503 case tlb_indexed: tlbw = uasm_i_tlbwi; break; 504 } 505 506 if (cpu_has_mips_r2_r6) { 507 if (cpu_has_mips_r2_exec_hazard) 508 uasm_i_ehb(p); 509 tlbw(p); 510 return; 511 } 512 513 switch (current_cpu_type()) { 514 case CPU_R4000PC: 515 case CPU_R4000SC: 516 case CPU_R4000MC: 517 case CPU_R4400PC: 518 case CPU_R4400SC: 519 case CPU_R4400MC: 520 /* 521 * This branch uses up a mtc0 hazard nop slot and saves 522 * two nops after the tlbw instruction. 523 */ 524 uasm_bgezl_hazard(p, r, hazard_instance); 525 tlbw(p); 526 uasm_bgezl_label(l, p, hazard_instance); 527 hazard_instance++; 528 uasm_i_nop(p); 529 break; 530 531 case CPU_R4600: 532 case CPU_R4700: 533 uasm_i_nop(p); 534 tlbw(p); 535 uasm_i_nop(p); 536 break; 537 538 case CPU_R5000: 539 case CPU_NEVADA: 540 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 541 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 542 tlbw(p); 543 break; 544 545 case CPU_R4300: 546 case CPU_5KC: 547 case CPU_TX49XX: 548 case CPU_PR4450: 549 uasm_i_nop(p); 550 tlbw(p); 551 break; 552 553 case CPU_R10000: 554 case CPU_R12000: 555 case CPU_R14000: 556 case CPU_R16000: 557 case CPU_4KC: 558 case CPU_4KEC: 559 case CPU_M14KC: 560 case CPU_M14KEC: 561 case CPU_SB1: 562 case CPU_SB1A: 563 case CPU_4KSC: 564 case CPU_20KC: 565 case CPU_25KF: 566 case CPU_BMIPS32: 567 case CPU_BMIPS3300: 568 case CPU_BMIPS4350: 569 case CPU_BMIPS4380: 570 case CPU_BMIPS5000: 571 case CPU_LOONGSON2EF: 572 case CPU_LOONGSON64: 573 case CPU_R5500: 574 if (m4kc_tlbp_war()) 575 uasm_i_nop(p); 576 fallthrough; 577 case CPU_ALCHEMY: 578 tlbw(p); 579 break; 580 581 case CPU_RM7000: 582 uasm_i_nop(p); 583 uasm_i_nop(p); 584 uasm_i_nop(p); 585 uasm_i_nop(p); 586 tlbw(p); 587 break; 588 589 case CPU_VR4111: 590 case CPU_VR4121: 591 case CPU_VR4122: 592 case CPU_VR4181: 593 case CPU_VR4181A: 594 uasm_i_nop(p); 595 uasm_i_nop(p); 596 tlbw(p); 597 uasm_i_nop(p); 598 uasm_i_nop(p); 599 break; 600 601 case CPU_VR4131: 602 case CPU_VR4133: 603 uasm_i_nop(p); 604 uasm_i_nop(p); 605 tlbw(p); 606 break; 607 608 case CPU_XBURST: 609 tlbw(p); 610 uasm_i_nop(p); 611 break; 612 613 default: 614 panic("No TLB refill handler yet (CPU type: %d)", 615 current_cpu_type()); 616 break; 617 } 618 } 619 EXPORT_SYMBOL_GPL(build_tlb_write_entry); 620 621 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, 622 unsigned int reg) 623 { 624 if (_PAGE_GLOBAL_SHIFT == 0) { 625 /* pte_t is already in EntryLo format */ 626 return; 627 } 628 629 if (cpu_has_rixi && !!_PAGE_NO_EXEC) { 630 if (fill_includes_sw_bits) { 631 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); 632 } else { 633 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); 634 UASM_i_ROTR(p, reg, reg, 635 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); 636 } 637 } else { 638 #ifdef CONFIG_PHYS_ADDR_T_64BIT 639 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); 640 #else 641 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); 642 #endif 643 } 644 } 645 646 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 647 648 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, 649 unsigned int tmp, enum label_id lid, 650 int restore_scratch) 651 { 652 if (restore_scratch) { 653 /* 654 * Ensure the MFC0 below observes the value written to the 655 * KScratch register by the prior MTC0. 656 */ 657 if (scratch_reg >= 0) 658 uasm_i_ehb(p); 659 660 /* Reset default page size */ 661 if (PM_DEFAULT_MASK >> 16) { 662 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 663 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 664 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 665 uasm_il_b(p, r, lid); 666 } else if (PM_DEFAULT_MASK) { 667 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 668 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 669 uasm_il_b(p, r, lid); 670 } else { 671 uasm_i_mtc0(p, 0, C0_PAGEMASK); 672 uasm_il_b(p, r, lid); 673 } 674 if (scratch_reg >= 0) 675 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 676 else 677 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 678 } else { 679 /* Reset default page size */ 680 if (PM_DEFAULT_MASK >> 16) { 681 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 682 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 683 uasm_il_b(p, r, lid); 684 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 685 } else if (PM_DEFAULT_MASK) { 686 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 687 uasm_il_b(p, r, lid); 688 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 689 } else { 690 uasm_il_b(p, r, lid); 691 uasm_i_mtc0(p, 0, C0_PAGEMASK); 692 } 693 } 694 } 695 696 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, 697 struct uasm_reloc **r, 698 unsigned int tmp, 699 enum tlb_write_entry wmode, 700 int restore_scratch) 701 { 702 /* Set huge page tlb entry size */ 703 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); 704 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); 705 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 706 707 build_tlb_write_entry(p, l, r, wmode); 708 709 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); 710 } 711 712 /* 713 * Check if Huge PTE is present, if so then jump to LABEL. 714 */ 715 static void 716 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, 717 unsigned int pmd, int lid) 718 { 719 UASM_i_LW(p, tmp, 0, pmd); 720 if (use_bbit_insns()) { 721 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); 722 } else { 723 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); 724 uasm_il_bnez(p, r, tmp, lid); 725 } 726 } 727 728 static void build_huge_update_entries(u32 **p, unsigned int pte, 729 unsigned int tmp) 730 { 731 int small_sequence; 732 733 /* 734 * A huge PTE describes an area the size of the 735 * configured huge page size. This is twice the 736 * of the large TLB entry size we intend to use. 737 * A TLB entry half the size of the configured 738 * huge page size is configured into entrylo0 739 * and entrylo1 to cover the contiguous huge PTE 740 * address space. 741 */ 742 small_sequence = (HPAGE_SIZE >> 7) < 0x10000; 743 744 /* We can clobber tmp. It isn't used after this.*/ 745 if (!small_sequence) 746 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); 747 748 build_convert_pte_to_entrylo(p, pte); 749 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ 750 /* convert to entrylo1 */ 751 if (small_sequence) 752 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); 753 else 754 UASM_i_ADDU(p, pte, pte, tmp); 755 756 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ 757 } 758 759 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, 760 struct uasm_label **l, 761 unsigned int pte, 762 unsigned int ptr, 763 unsigned int flush) 764 { 765 #ifdef CONFIG_SMP 766 UASM_i_SC(p, pte, 0, ptr); 767 uasm_il_beqz(p, r, pte, label_tlb_huge_update); 768 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ 769 #else 770 UASM_i_SW(p, pte, 0, ptr); 771 #endif 772 if (cpu_has_ftlb && flush) { 773 BUG_ON(!cpu_has_tlbinv); 774 775 UASM_i_MFC0(p, ptr, C0_ENTRYHI); 776 uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); 777 UASM_i_MTC0(p, ptr, C0_ENTRYHI); 778 build_tlb_write_entry(p, l, r, tlb_indexed); 779 780 uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); 781 UASM_i_MTC0(p, ptr, C0_ENTRYHI); 782 build_huge_update_entries(p, pte, ptr); 783 build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0); 784 785 return; 786 } 787 788 build_huge_update_entries(p, pte, ptr); 789 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); 790 } 791 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 792 793 #ifdef CONFIG_64BIT 794 /* 795 * TMP and PTR are scratch. 796 * TMP will be clobbered, PTR will hold the pmd entry. 797 */ 798 void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 799 unsigned int tmp, unsigned int ptr) 800 { 801 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 802 long pgdc = (long)pgd_current; 803 #endif 804 /* 805 * The vmalloc handling is not in the hotpath. 806 */ 807 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 808 809 if (check_for_high_segbits) { 810 /* 811 * The kernel currently implicitely assumes that the 812 * MIPS SEGBITS parameter for the processor is 813 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never 814 * allocate virtual addresses outside the maximum 815 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But 816 * that doesn't prevent user code from accessing the 817 * higher xuseg addresses. Here, we make sure that 818 * everything but the lower xuseg addresses goes down 819 * the module_alloc/vmalloc path. 820 */ 821 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 822 uasm_il_bnez(p, r, ptr, label_vmalloc); 823 } else { 824 uasm_il_bltz(p, r, tmp, label_vmalloc); 825 } 826 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 827 828 if (pgd_reg != -1) { 829 /* pgd is in pgd_reg */ 830 if (cpu_has_ldpte) 831 UASM_i_MFC0(p, ptr, C0_PWBASE); 832 else 833 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 834 } else { 835 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT) 836 /* 837 * &pgd << 11 stored in CONTEXT [23..63]. 838 */ 839 UASM_i_MFC0(p, ptr, C0_CONTEXT); 840 841 /* Clear lower 23 bits of context. */ 842 uasm_i_dins(p, ptr, 0, 0, 23); 843 844 /* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */ 845 uasm_i_ori(p, ptr, ptr, ((u64)(CAC_BASE) >> 53)); 846 uasm_i_drotr(p, ptr, ptr, 11); 847 #elif defined(CONFIG_SMP) 848 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); 849 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 850 UASM_i_LA_mostly(p, tmp, pgdc); 851 uasm_i_daddu(p, ptr, ptr, tmp); 852 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 853 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 854 #else 855 UASM_i_LA_mostly(p, ptr, pgdc); 856 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 857 #endif 858 } 859 860 uasm_l_vmalloc_done(l, *p); 861 862 /* get pgd offset in bytes */ 863 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); 864 865 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 866 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 867 #ifndef __PAGETABLE_PUD_FOLDED 868 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 869 uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */ 870 uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */ 871 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3); 872 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */ 873 #endif 874 #ifndef __PAGETABLE_PMD_FOLDED 875 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 876 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 877 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 878 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 879 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 880 #endif 881 } 882 EXPORT_SYMBOL_GPL(build_get_pmde64); 883 884 /* 885 * BVADDR is the faulting address, PTR is scratch. 886 * PTR will hold the pgd for vmalloc. 887 */ 888 static void 889 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 890 unsigned int bvaddr, unsigned int ptr, 891 enum vmalloc64_mode mode) 892 { 893 long swpd = (long)swapper_pg_dir; 894 int single_insn_swpd; 895 int did_vmalloc_branch = 0; 896 897 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); 898 899 uasm_l_vmalloc(l, *p); 900 901 if (mode != not_refill && check_for_high_segbits) { 902 if (single_insn_swpd) { 903 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); 904 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 905 did_vmalloc_branch = 1; 906 /* fall through */ 907 } else { 908 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); 909 } 910 } 911 if (!did_vmalloc_branch) { 912 if (single_insn_swpd) { 913 uasm_il_b(p, r, label_vmalloc_done); 914 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 915 } else { 916 UASM_i_LA_mostly(p, ptr, swpd); 917 uasm_il_b(p, r, label_vmalloc_done); 918 if (uasm_in_compat_space_p(swpd)) 919 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); 920 else 921 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); 922 } 923 } 924 if (mode != not_refill && check_for_high_segbits) { 925 uasm_l_large_segbits_fault(l, *p); 926 927 if (mode == refill_scratch && scratch_reg >= 0) 928 uasm_i_ehb(p); 929 930 /* 931 * We get here if we are an xsseg address, or if we are 932 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. 933 * 934 * Ignoring xsseg (assume disabled so would generate 935 * (address errors?), the only remaining possibility 936 * is the upper xuseg addresses. On processors with 937 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these 938 * addresses would have taken an address error. We try 939 * to mimic that here by taking a load/istream page 940 * fault. 941 */ 942 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 943 uasm_i_sync(p, 0); 944 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); 945 uasm_i_jr(p, ptr); 946 947 if (mode == refill_scratch) { 948 if (scratch_reg >= 0) 949 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 950 else 951 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 952 } else { 953 uasm_i_nop(p); 954 } 955 } 956 } 957 958 #else /* !CONFIG_64BIT */ 959 960 /* 961 * TMP and PTR are scratch. 962 * TMP will be clobbered, PTR will hold the pgd entry. 963 */ 964 void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 965 { 966 if (pgd_reg != -1) { 967 /* pgd is in pgd_reg */ 968 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); 969 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 970 } else { 971 long pgdc = (long)pgd_current; 972 973 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 974 #ifdef CONFIG_SMP 975 uasm_i_mfc0(p, ptr, SMP_CPUID_REG); 976 UASM_i_LA_mostly(p, tmp, pgdc); 977 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 978 uasm_i_addu(p, ptr, tmp, ptr); 979 #else 980 UASM_i_LA_mostly(p, ptr, pgdc); 981 #endif 982 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 983 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 984 } 985 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 986 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); 987 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 988 } 989 EXPORT_SYMBOL_GPL(build_get_pgde32); 990 991 #endif /* !CONFIG_64BIT */ 992 993 static void build_adjust_context(u32 **p, unsigned int ctx) 994 { 995 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 996 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 997 998 switch (current_cpu_type()) { 999 case CPU_VR41XX: 1000 case CPU_VR4111: 1001 case CPU_VR4121: 1002 case CPU_VR4122: 1003 case CPU_VR4131: 1004 case CPU_VR4181: 1005 case CPU_VR4181A: 1006 case CPU_VR4133: 1007 shift += 2; 1008 break; 1009 1010 default: 1011 break; 1012 } 1013 1014 if (shift) 1015 UASM_i_SRL(p, ctx, ctx, shift); 1016 uasm_i_andi(p, ctx, ctx, mask); 1017 } 1018 1019 void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1020 { 1021 /* 1022 * Bug workaround for the Nevada. It seems as if under certain 1023 * circumstances the move from cp0_context might produce a 1024 * bogus result when the mfc0 instruction and its consumer are 1025 * in a different cacheline or a load instruction, probably any 1026 * memory reference, is between them. 1027 */ 1028 switch (current_cpu_type()) { 1029 case CPU_NEVADA: 1030 UASM_i_LW(p, ptr, 0, ptr); 1031 GET_CONTEXT(p, tmp); /* get context reg */ 1032 break; 1033 1034 default: 1035 GET_CONTEXT(p, tmp); /* get context reg */ 1036 UASM_i_LW(p, ptr, 0, ptr); 1037 break; 1038 } 1039 1040 build_adjust_context(p, tmp); 1041 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1042 } 1043 EXPORT_SYMBOL_GPL(build_get_ptep); 1044 1045 void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) 1046 { 1047 int pte_off_even = 0; 1048 int pte_off_odd = sizeof(pte_t); 1049 1050 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT) 1051 /* The low 32 bits of EntryLo is stored in pte_high */ 1052 pte_off_even += offsetof(pte_t, pte_high); 1053 pte_off_odd += offsetof(pte_t, pte_high); 1054 #endif 1055 1056 if (IS_ENABLED(CONFIG_XPA)) { 1057 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */ 1058 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1059 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); 1060 1061 if (cpu_has_xpa && !mips_xpa_disabled) { 1062 uasm_i_lw(p, tmp, 0, ptep); 1063 uasm_i_ext(p, tmp, tmp, 0, 24); 1064 uasm_i_mthc0(p, tmp, C0_ENTRYLO0); 1065 } 1066 1067 uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */ 1068 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1069 UASM_i_MTC0(p, tmp, C0_ENTRYLO1); 1070 1071 if (cpu_has_xpa && !mips_xpa_disabled) { 1072 uasm_i_lw(p, tmp, sizeof(pte_t), ptep); 1073 uasm_i_ext(p, tmp, tmp, 0, 24); 1074 uasm_i_mthc0(p, tmp, C0_ENTRYLO1); 1075 } 1076 return; 1077 } 1078 1079 UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */ 1080 UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */ 1081 if (r45k_bvahwbug()) 1082 build_tlb_probe_entry(p); 1083 build_convert_pte_to_entrylo(p, tmp); 1084 if (r4k_250MHZhwbug()) 1085 UASM_i_MTC0(p, 0, C0_ENTRYLO0); 1086 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ 1087 build_convert_pte_to_entrylo(p, ptep); 1088 if (r45k_bvahwbug()) 1089 uasm_i_mfc0(p, tmp, C0_INDEX); 1090 if (r4k_250MHZhwbug()) 1091 UASM_i_MTC0(p, 0, C0_ENTRYLO1); 1092 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ 1093 } 1094 EXPORT_SYMBOL_GPL(build_update_entries); 1095 1096 struct mips_huge_tlb_info { 1097 int huge_pte; 1098 int restore_scratch; 1099 bool need_reload_pte; 1100 }; 1101 1102 static struct mips_huge_tlb_info 1103 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, 1104 struct uasm_reloc **r, unsigned int tmp, 1105 unsigned int ptr, int c0_scratch_reg) 1106 { 1107 struct mips_huge_tlb_info rv; 1108 unsigned int even, odd; 1109 int vmalloc_branch_delay_filled = 0; 1110 const int scratch = 1; /* Our extra working register */ 1111 1112 rv.huge_pte = scratch; 1113 rv.restore_scratch = 0; 1114 rv.need_reload_pte = false; 1115 1116 if (check_for_high_segbits) { 1117 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1118 1119 if (pgd_reg != -1) 1120 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1121 else 1122 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1123 1124 if (c0_scratch_reg >= 0) 1125 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1126 else 1127 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1128 1129 uasm_i_dsrl_safe(p, scratch, tmp, 1130 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1131 uasm_il_bnez(p, r, scratch, label_vmalloc); 1132 1133 if (pgd_reg == -1) { 1134 vmalloc_branch_delay_filled = 1; 1135 /* Clear lower 23 bits of context. */ 1136 uasm_i_dins(p, ptr, 0, 0, 23); 1137 } 1138 } else { 1139 if (pgd_reg != -1) 1140 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1141 else 1142 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1143 1144 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1145 1146 if (c0_scratch_reg >= 0) 1147 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1148 else 1149 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1150 1151 if (pgd_reg == -1) 1152 /* Clear lower 23 bits of context. */ 1153 uasm_i_dins(p, ptr, 0, 0, 23); 1154 1155 uasm_il_bltz(p, r, tmp, label_vmalloc); 1156 } 1157 1158 if (pgd_reg == -1) { 1159 vmalloc_branch_delay_filled = 1; 1160 /* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */ 1161 uasm_i_ori(p, ptr, ptr, ((u64)(CAC_BASE) >> 53)); 1162 1163 uasm_i_drotr(p, ptr, ptr, 11); 1164 } 1165 1166 #ifdef __PAGETABLE_PMD_FOLDED 1167 #define LOC_PTEP scratch 1168 #else 1169 #define LOC_PTEP ptr 1170 #endif 1171 1172 if (!vmalloc_branch_delay_filled) 1173 /* get pgd offset in bytes */ 1174 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1175 1176 uasm_l_vmalloc_done(l, *p); 1177 1178 /* 1179 * tmp ptr 1180 * fall-through case = badvaddr *pgd_current 1181 * vmalloc case = badvaddr swapper_pg_dir 1182 */ 1183 1184 if (vmalloc_branch_delay_filled) 1185 /* get pgd offset in bytes */ 1186 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1187 1188 #ifdef __PAGETABLE_PMD_FOLDED 1189 GET_CONTEXT(p, tmp); /* get context reg */ 1190 #endif 1191 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); 1192 1193 if (use_lwx_insns()) { 1194 UASM_i_LWX(p, LOC_PTEP, scratch, ptr); 1195 } else { 1196 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ 1197 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ 1198 } 1199 1200 #ifndef __PAGETABLE_PUD_FOLDED 1201 /* get pud offset in bytes */ 1202 uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3); 1203 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3); 1204 1205 if (use_lwx_insns()) { 1206 UASM_i_LWX(p, ptr, scratch, ptr); 1207 } else { 1208 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1209 UASM_i_LW(p, ptr, 0, ptr); 1210 } 1211 /* ptr contains a pointer to PMD entry */ 1212 /* tmp contains the address */ 1213 #endif 1214 1215 #ifndef __PAGETABLE_PMD_FOLDED 1216 /* get pmd offset in bytes */ 1217 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); 1218 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); 1219 GET_CONTEXT(p, tmp); /* get context reg */ 1220 1221 if (use_lwx_insns()) { 1222 UASM_i_LWX(p, scratch, scratch, ptr); 1223 } else { 1224 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1225 UASM_i_LW(p, scratch, 0, ptr); 1226 } 1227 #endif 1228 /* Adjust the context during the load latency. */ 1229 build_adjust_context(p, tmp); 1230 1231 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1232 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); 1233 /* 1234 * The in the LWX case we don't want to do the load in the 1235 * delay slot. It cannot issue in the same cycle and may be 1236 * speculative and unneeded. 1237 */ 1238 if (use_lwx_insns()) 1239 uasm_i_nop(p); 1240 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 1241 1242 1243 /* build_update_entries */ 1244 if (use_lwx_insns()) { 1245 even = ptr; 1246 odd = tmp; 1247 UASM_i_LWX(p, even, scratch, tmp); 1248 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); 1249 UASM_i_LWX(p, odd, scratch, tmp); 1250 } else { 1251 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ 1252 even = tmp; 1253 odd = ptr; 1254 UASM_i_LW(p, even, 0, ptr); /* get even pte */ 1255 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ 1256 } 1257 if (cpu_has_rixi) { 1258 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); 1259 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1260 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1261 } else { 1262 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); 1263 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1264 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1265 } 1266 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ 1267 1268 if (c0_scratch_reg >= 0) { 1269 uasm_i_ehb(p); 1270 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1271 build_tlb_write_entry(p, l, r, tlb_random); 1272 uasm_l_leave(l, *p); 1273 rv.restore_scratch = 1; 1274 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { 1275 build_tlb_write_entry(p, l, r, tlb_random); 1276 uasm_l_leave(l, *p); 1277 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1278 } else { 1279 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1280 build_tlb_write_entry(p, l, r, tlb_random); 1281 uasm_l_leave(l, *p); 1282 rv.restore_scratch = 1; 1283 } 1284 1285 uasm_i_eret(p); /* return from trap */ 1286 1287 return rv; 1288 } 1289 1290 /* 1291 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception 1292 * because EXL == 0. If we wrap, we can also use the 32 instruction 1293 * slots before the XTLB refill exception handler which belong to the 1294 * unused TLB refill exception. 1295 */ 1296 #define MIPS64_REFILL_INSNS 32 1297 1298 static void build_r4000_tlb_refill_handler(void) 1299 { 1300 u32 *p = tlb_handler; 1301 struct uasm_label *l = labels; 1302 struct uasm_reloc *r = relocs; 1303 u32 *f; 1304 unsigned int final_len; 1305 struct mips_huge_tlb_info htlb_info __maybe_unused; 1306 enum vmalloc64_mode vmalloc_mode __maybe_unused; 1307 1308 memset(tlb_handler, 0, sizeof(tlb_handler)); 1309 memset(labels, 0, sizeof(labels)); 1310 memset(relocs, 0, sizeof(relocs)); 1311 memset(final_handler, 0, sizeof(final_handler)); 1312 1313 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { 1314 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, 1315 scratch_reg); 1316 vmalloc_mode = refill_scratch; 1317 } else { 1318 htlb_info.huge_pte = K0; 1319 htlb_info.restore_scratch = 0; 1320 htlb_info.need_reload_pte = true; 1321 vmalloc_mode = refill_noscratch; 1322 /* 1323 * create the plain linear handler 1324 */ 1325 if (bcm1250_m3_war()) { 1326 unsigned int segbits = 44; 1327 1328 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1329 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 1330 uasm_i_xor(&p, K0, K0, K1); 1331 uasm_i_dsrl_safe(&p, K1, K0, 62); 1332 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 1333 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 1334 uasm_i_or(&p, K0, K0, K1); 1335 uasm_il_bnez(&p, &r, K0, label_leave); 1336 /* No need for uasm_i_nop */ 1337 } 1338 1339 #ifdef CONFIG_64BIT 1340 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1341 #else 1342 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1343 #endif 1344 1345 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1346 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); 1347 #endif 1348 1349 build_get_ptep(&p, K0, K1); 1350 build_update_entries(&p, K0, K1); 1351 build_tlb_write_entry(&p, &l, &r, tlb_random); 1352 uasm_l_leave(&l, p); 1353 uasm_i_eret(&p); /* return from trap */ 1354 } 1355 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1356 uasm_l_tlb_huge_update(&l, p); 1357 if (htlb_info.need_reload_pte) 1358 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1); 1359 build_huge_update_entries(&p, htlb_info.huge_pte, K1); 1360 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, 1361 htlb_info.restore_scratch); 1362 #endif 1363 1364 #ifdef CONFIG_64BIT 1365 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); 1366 #endif 1367 1368 /* 1369 * Overflow check: For the 64bit handler, we need at least one 1370 * free instruction slot for the wrap-around branch. In worst 1371 * case, if the intended insertion point is a delay slot, we 1372 * need three, with the second nop'ed and the third being 1373 * unused. 1374 */ 1375 switch (boot_cpu_type()) { 1376 default: 1377 if (sizeof(long) == 4) { 1378 fallthrough; 1379 case CPU_LOONGSON2EF: 1380 /* Loongson2 ebase is different than r4k, we have more space */ 1381 if ((p - tlb_handler) > 64) 1382 panic("TLB refill handler space exceeded"); 1383 /* 1384 * Now fold the handler in the TLB refill handler space. 1385 */ 1386 f = final_handler; 1387 /* Simplest case, just copy the handler. */ 1388 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1389 final_len = p - tlb_handler; 1390 break; 1391 } else { 1392 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) 1393 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) 1394 && uasm_insn_has_bdelay(relocs, 1395 tlb_handler + MIPS64_REFILL_INSNS - 3))) 1396 panic("TLB refill handler space exceeded"); 1397 /* 1398 * Now fold the handler in the TLB refill handler space. 1399 */ 1400 f = final_handler + MIPS64_REFILL_INSNS; 1401 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { 1402 /* Just copy the handler. */ 1403 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1404 final_len = p - tlb_handler; 1405 } else { 1406 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1407 const enum label_id ls = label_tlb_huge_update; 1408 #else 1409 const enum label_id ls = label_vmalloc; 1410 #endif 1411 u32 *split; 1412 int ov = 0; 1413 int i; 1414 1415 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) 1416 ; 1417 BUG_ON(i == ARRAY_SIZE(labels)); 1418 split = labels[i].addr; 1419 1420 /* 1421 * See if we have overflown one way or the other. 1422 */ 1423 if (split > tlb_handler + MIPS64_REFILL_INSNS || 1424 split < p - MIPS64_REFILL_INSNS) 1425 ov = 1; 1426 1427 if (ov) { 1428 /* 1429 * Split two instructions before the end. One 1430 * for the branch and one for the instruction 1431 * in the delay slot. 1432 */ 1433 split = tlb_handler + MIPS64_REFILL_INSNS - 2; 1434 1435 /* 1436 * If the branch would fall in a delay slot, 1437 * we must back up an additional instruction 1438 * so that it is no longer in a delay slot. 1439 */ 1440 if (uasm_insn_has_bdelay(relocs, split - 1)) 1441 split--; 1442 } 1443 /* Copy first part of the handler. */ 1444 uasm_copy_handler(relocs, labels, tlb_handler, split, f); 1445 f += split - tlb_handler; 1446 1447 if (ov) { 1448 /* Insert branch. */ 1449 uasm_l_split(&l, final_handler); 1450 uasm_il_b(&f, &r, label_split); 1451 if (uasm_insn_has_bdelay(relocs, split)) 1452 uasm_i_nop(&f); 1453 else { 1454 uasm_copy_handler(relocs, labels, 1455 split, split + 1, f); 1456 uasm_move_labels(labels, f, f + 1, -1); 1457 f++; 1458 split++; 1459 } 1460 } 1461 1462 /* Copy the rest of the handler. */ 1463 uasm_copy_handler(relocs, labels, split, p, final_handler); 1464 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + 1465 (p - split); 1466 } 1467 } 1468 break; 1469 } 1470 1471 uasm_resolve_relocs(relocs, labels); 1472 pr_debug("Wrote TLB refill handler (%u instructions).\n", 1473 final_len); 1474 1475 memcpy((void *)ebase, final_handler, 0x100); 1476 local_flush_icache_range(ebase, ebase + 0x100); 1477 dump_handler("r4000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x100)); 1478 } 1479 1480 static void setup_pw(void) 1481 { 1482 unsigned int pwctl; 1483 unsigned long pgd_i, pgd_w; 1484 #ifndef __PAGETABLE_PMD_FOLDED 1485 unsigned long pmd_i, pmd_w; 1486 #endif 1487 unsigned long pt_i, pt_w; 1488 unsigned long pte_i, pte_w; 1489 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1490 unsigned long psn; 1491 1492 psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */ 1493 #endif 1494 pgd_i = PGDIR_SHIFT; /* 1st level PGD */ 1495 #ifndef __PAGETABLE_PMD_FOLDED 1496 pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER; 1497 1498 pmd_i = PMD_SHIFT; /* 2nd level PMD */ 1499 pmd_w = PMD_SHIFT - PAGE_SHIFT; 1500 #else 1501 pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER; 1502 #endif 1503 1504 pt_i = PAGE_SHIFT; /* 3rd level PTE */ 1505 pt_w = PAGE_SHIFT - 3; 1506 1507 pte_i = ilog2(_PAGE_GLOBAL); 1508 pte_w = 0; 1509 pwctl = 1 << 30; /* Set PWDirExt */ 1510 1511 #ifndef __PAGETABLE_PMD_FOLDED 1512 write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i); 1513 write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w); 1514 #else 1515 write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i); 1516 write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w); 1517 #endif 1518 1519 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1520 pwctl |= (1 << 6 | psn); 1521 #endif 1522 write_c0_pwctl(pwctl); 1523 write_c0_kpgd((long)swapper_pg_dir); 1524 kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */ 1525 } 1526 1527 static void build_loongson3_tlb_refill_handler(void) 1528 { 1529 u32 *p = tlb_handler; 1530 struct uasm_label *l = labels; 1531 struct uasm_reloc *r = relocs; 1532 1533 memset(labels, 0, sizeof(labels)); 1534 memset(relocs, 0, sizeof(relocs)); 1535 memset(tlb_handler, 0, sizeof(tlb_handler)); 1536 1537 if (check_for_high_segbits) { 1538 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1539 uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1540 uasm_il_beqz(&p, &r, K1, label_vmalloc); 1541 uasm_i_nop(&p); 1542 1543 uasm_il_bgez(&p, &r, K0, label_large_segbits_fault); 1544 uasm_i_nop(&p); 1545 uasm_l_vmalloc(&l, p); 1546 } 1547 1548 uasm_i_dmfc0(&p, K1, C0_PGD); 1549 1550 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */ 1551 #ifndef __PAGETABLE_PMD_FOLDED 1552 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */ 1553 #endif 1554 uasm_i_ldpte(&p, K1, 0); /* even */ 1555 uasm_i_ldpte(&p, K1, 1); /* odd */ 1556 uasm_i_tlbwr(&p); 1557 1558 /* restore page mask */ 1559 if (PM_DEFAULT_MASK >> 16) { 1560 uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16); 1561 uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff); 1562 uasm_i_mtc0(&p, K0, C0_PAGEMASK); 1563 } else if (PM_DEFAULT_MASK) { 1564 uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK); 1565 uasm_i_mtc0(&p, K0, C0_PAGEMASK); 1566 } else { 1567 uasm_i_mtc0(&p, 0, C0_PAGEMASK); 1568 } 1569 1570 uasm_i_eret(&p); 1571 1572 if (check_for_high_segbits) { 1573 uasm_l_large_segbits_fault(&l, p); 1574 UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0); 1575 uasm_i_jr(&p, K1); 1576 uasm_i_nop(&p); 1577 } 1578 1579 uasm_resolve_relocs(relocs, labels); 1580 memcpy((void *)(ebase + 0x80), tlb_handler, 0x80); 1581 local_flush_icache_range(ebase + 0x80, ebase + 0x100); 1582 dump_handler("loongson3_tlb_refill", 1583 (u32 *)(ebase + 0x80), (u32 *)(ebase + 0x100)); 1584 } 1585 1586 static void build_setup_pgd(void) 1587 { 1588 const int a0 = 4; 1589 const int __maybe_unused a1 = 5; 1590 const int __maybe_unused a2 = 6; 1591 u32 *p = (u32 *)msk_isa16_mode((ulong)tlbmiss_handler_setup_pgd); 1592 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1593 long pgdc = (long)pgd_current; 1594 #endif 1595 1596 memset(p, 0, tlbmiss_handler_setup_pgd_end - (char *)p); 1597 memset(labels, 0, sizeof(labels)); 1598 memset(relocs, 0, sizeof(relocs)); 1599 pgd_reg = allocate_kscratch(); 1600 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 1601 if (pgd_reg == -1) { 1602 struct uasm_label *l = labels; 1603 struct uasm_reloc *r = relocs; 1604 1605 /* PGD << 11 in c0_Context */ 1606 /* 1607 * If it is a ckseg0 address, convert to a physical 1608 * address. Shifting right by 29 and adding 4 will 1609 * result in zero for these addresses. 1610 * 1611 */ 1612 UASM_i_SRA(&p, a1, a0, 29); 1613 UASM_i_ADDIU(&p, a1, a1, 4); 1614 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); 1615 uasm_i_nop(&p); 1616 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); 1617 uasm_l_tlbl_goaround1(&l, p); 1618 UASM_i_SLL(&p, a0, a0, 11); 1619 UASM_i_MTC0(&p, a0, C0_CONTEXT); 1620 uasm_i_jr(&p, 31); 1621 uasm_i_ehb(&p); 1622 } else { 1623 /* PGD in c0_KScratch */ 1624 if (cpu_has_ldpte) 1625 UASM_i_MTC0(&p, a0, C0_PWBASE); 1626 else 1627 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1628 uasm_i_jr(&p, 31); 1629 uasm_i_ehb(&p); 1630 } 1631 #else 1632 #ifdef CONFIG_SMP 1633 /* Save PGD to pgd_current[smp_processor_id()] */ 1634 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); 1635 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); 1636 UASM_i_LA_mostly(&p, a2, pgdc); 1637 UASM_i_ADDU(&p, a2, a2, a1); 1638 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1639 #else 1640 UASM_i_LA_mostly(&p, a2, pgdc); 1641 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1642 #endif /* SMP */ 1643 1644 /* if pgd_reg is allocated, save PGD also to scratch register */ 1645 if (pgd_reg != -1) { 1646 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1647 uasm_i_jr(&p, 31); 1648 uasm_i_ehb(&p); 1649 } else { 1650 uasm_i_jr(&p, 31); 1651 uasm_i_nop(&p); 1652 } 1653 #endif 1654 if (p >= (u32 *)tlbmiss_handler_setup_pgd_end) 1655 panic("tlbmiss_handler_setup_pgd space exceeded"); 1656 1657 uasm_resolve_relocs(relocs, labels); 1658 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", 1659 (unsigned int)(p - (u32 *)tlbmiss_handler_setup_pgd)); 1660 1661 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, 1662 tlbmiss_handler_setup_pgd_end); 1663 } 1664 1665 static void 1666 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) 1667 { 1668 #ifdef CONFIG_SMP 1669 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 1670 uasm_i_sync(p, 0); 1671 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1672 if (cpu_has_64bits) 1673 uasm_i_lld(p, pte, 0, ptr); 1674 else 1675 # endif 1676 UASM_i_LL(p, pte, 0, ptr); 1677 #else 1678 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1679 if (cpu_has_64bits) 1680 uasm_i_ld(p, pte, 0, ptr); 1681 else 1682 # endif 1683 UASM_i_LW(p, pte, 0, ptr); 1684 #endif 1685 } 1686 1687 static void 1688 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, 1689 unsigned int mode, unsigned int scratch) 1690 { 1691 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1692 unsigned int swmode = mode & ~hwmode; 1693 1694 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) { 1695 uasm_i_lui(p, scratch, swmode >> 16); 1696 uasm_i_or(p, pte, pte, scratch); 1697 BUG_ON(swmode & 0xffff); 1698 } else { 1699 uasm_i_ori(p, pte, pte, mode); 1700 } 1701 1702 #ifdef CONFIG_SMP 1703 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1704 if (cpu_has_64bits) 1705 uasm_i_scd(p, pte, 0, ptr); 1706 else 1707 # endif 1708 UASM_i_SC(p, pte, 0, ptr); 1709 1710 if (r10000_llsc_war()) 1711 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); 1712 else 1713 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1714 1715 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1716 if (!cpu_has_64bits) { 1717 /* no uasm_i_nop needed */ 1718 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1719 uasm_i_ori(p, pte, pte, hwmode); 1720 BUG_ON(hwmode & ~0xffff); 1721 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1722 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1723 /* no uasm_i_nop needed */ 1724 uasm_i_lw(p, pte, 0, ptr); 1725 } else 1726 uasm_i_nop(p); 1727 # else 1728 uasm_i_nop(p); 1729 # endif 1730 #else 1731 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1732 if (cpu_has_64bits) 1733 uasm_i_sd(p, pte, 0, ptr); 1734 else 1735 # endif 1736 UASM_i_SW(p, pte, 0, ptr); 1737 1738 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1739 if (!cpu_has_64bits) { 1740 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1741 uasm_i_ori(p, pte, pte, hwmode); 1742 BUG_ON(hwmode & ~0xffff); 1743 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1744 uasm_i_lw(p, pte, 0, ptr); 1745 } 1746 # endif 1747 #endif 1748 } 1749 1750 /* 1751 * Check if PTE is present, if not then jump to LABEL. PTR points to 1752 * the page table where this PTE is located, PTE will be re-loaded 1753 * with it's original value. 1754 */ 1755 static void 1756 build_pte_present(u32 **p, struct uasm_reloc **r, 1757 int pte, int ptr, int scratch, enum label_id lid) 1758 { 1759 int t = scratch >= 0 ? scratch : pte; 1760 int cur = pte; 1761 1762 if (cpu_has_rixi) { 1763 if (use_bbit_insns()) { 1764 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); 1765 uasm_i_nop(p); 1766 } else { 1767 if (_PAGE_PRESENT_SHIFT) { 1768 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1769 cur = t; 1770 } 1771 uasm_i_andi(p, t, cur, 1); 1772 uasm_il_beqz(p, r, t, lid); 1773 if (pte == t) 1774 /* You lose the SMP race :-(*/ 1775 iPTE_LW(p, pte, ptr); 1776 } 1777 } else { 1778 if (_PAGE_PRESENT_SHIFT) { 1779 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1780 cur = t; 1781 } 1782 uasm_i_andi(p, t, cur, 1783 (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT); 1784 uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT); 1785 uasm_il_bnez(p, r, t, lid); 1786 if (pte == t) 1787 /* You lose the SMP race :-(*/ 1788 iPTE_LW(p, pte, ptr); 1789 } 1790 } 1791 1792 /* Make PTE valid, store result in PTR. */ 1793 static void 1794 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, 1795 unsigned int ptr, unsigned int scratch) 1796 { 1797 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 1798 1799 iPTE_SW(p, r, pte, ptr, mode, scratch); 1800 } 1801 1802 /* 1803 * Check if PTE can be written to, if not branch to LABEL. Regardless 1804 * restore PTE with value from PTR when done. 1805 */ 1806 static void 1807 build_pte_writable(u32 **p, struct uasm_reloc **r, 1808 unsigned int pte, unsigned int ptr, int scratch, 1809 enum label_id lid) 1810 { 1811 int t = scratch >= 0 ? scratch : pte; 1812 int cur = pte; 1813 1814 if (_PAGE_PRESENT_SHIFT) { 1815 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1816 cur = t; 1817 } 1818 uasm_i_andi(p, t, cur, 1819 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1820 uasm_i_xori(p, t, t, 1821 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1822 uasm_il_bnez(p, r, t, lid); 1823 if (pte == t) 1824 /* You lose the SMP race :-(*/ 1825 iPTE_LW(p, pte, ptr); 1826 else 1827 uasm_i_nop(p); 1828 } 1829 1830 /* Make PTE writable, update software status bits as well, then store 1831 * at PTR. 1832 */ 1833 static void 1834 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, 1835 unsigned int ptr, unsigned int scratch) 1836 { 1837 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 1838 | _PAGE_DIRTY); 1839 1840 iPTE_SW(p, r, pte, ptr, mode, scratch); 1841 } 1842 1843 /* 1844 * Check if PTE can be modified, if not branch to LABEL. Regardless 1845 * restore PTE with value from PTR when done. 1846 */ 1847 static void 1848 build_pte_modifiable(u32 **p, struct uasm_reloc **r, 1849 unsigned int pte, unsigned int ptr, int scratch, 1850 enum label_id lid) 1851 { 1852 if (use_bbit_insns()) { 1853 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); 1854 uasm_i_nop(p); 1855 } else { 1856 int t = scratch >= 0 ? scratch : pte; 1857 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT); 1858 uasm_i_andi(p, t, t, 1); 1859 uasm_il_beqz(p, r, t, lid); 1860 if (pte == t) 1861 /* You lose the SMP race :-(*/ 1862 iPTE_LW(p, pte, ptr); 1863 } 1864 } 1865 1866 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1867 1868 1869 /* 1870 * R3000 style TLB load/store/modify handlers. 1871 */ 1872 1873 /* 1874 * This places the pte into ENTRYLO0 and writes it with tlbwi. 1875 * Then it returns. 1876 */ 1877 static void 1878 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 1879 { 1880 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1881 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 1882 uasm_i_tlbwi(p); 1883 uasm_i_jr(p, tmp); 1884 uasm_i_rfe(p); /* branch delay */ 1885 } 1886 1887 /* 1888 * This places the pte into ENTRYLO0 and writes it with tlbwi 1889 * or tlbwr as appropriate. This is because the index register 1890 * may have the probe fail bit set as a result of a trap on a 1891 * kseg2 access, i.e. without refill. Then it returns. 1892 */ 1893 static void 1894 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, 1895 struct uasm_reloc **r, unsigned int pte, 1896 unsigned int tmp) 1897 { 1898 uasm_i_mfc0(p, tmp, C0_INDEX); 1899 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1900 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 1901 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ 1902 uasm_i_tlbwi(p); /* cp0 delay */ 1903 uasm_i_jr(p, tmp); 1904 uasm_i_rfe(p); /* branch delay */ 1905 uasm_l_r3000_write_probe_fail(l, *p); 1906 uasm_i_tlbwr(p); /* cp0 delay */ 1907 uasm_i_jr(p, tmp); 1908 uasm_i_rfe(p); /* branch delay */ 1909 } 1910 1911 static void 1912 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1913 unsigned int ptr) 1914 { 1915 long pgdc = (long)pgd_current; 1916 1917 uasm_i_mfc0(p, pte, C0_BADVADDR); 1918 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ 1919 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 1920 uasm_i_srl(p, pte, pte, 22); /* load delay */ 1921 uasm_i_sll(p, pte, pte, 2); 1922 uasm_i_addu(p, ptr, ptr, pte); 1923 uasm_i_mfc0(p, pte, C0_CONTEXT); 1924 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ 1925 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ 1926 uasm_i_addu(p, ptr, ptr, pte); 1927 uasm_i_lw(p, pte, 0, ptr); 1928 uasm_i_tlbp(p); /* load delay */ 1929 } 1930 1931 static void build_r3000_tlb_load_handler(void) 1932 { 1933 u32 *p = (u32 *)handle_tlbl; 1934 struct uasm_label *l = labels; 1935 struct uasm_reloc *r = relocs; 1936 1937 memset(p, 0, handle_tlbl_end - (char *)p); 1938 memset(labels, 0, sizeof(labels)); 1939 memset(relocs, 0, sizeof(relocs)); 1940 1941 build_r3000_tlbchange_handler_head(&p, K0, K1); 1942 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); 1943 uasm_i_nop(&p); /* load delay */ 1944 build_make_valid(&p, &r, K0, K1, -1); 1945 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1946 1947 uasm_l_nopage_tlbl(&l, p); 1948 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1949 uasm_i_nop(&p); 1950 1951 if (p >= (u32 *)handle_tlbl_end) 1952 panic("TLB load handler fastpath space exceeded"); 1953 1954 uasm_resolve_relocs(relocs, labels); 1955 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1956 (unsigned int)(p - (u32 *)handle_tlbl)); 1957 1958 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_end); 1959 } 1960 1961 static void build_r3000_tlb_store_handler(void) 1962 { 1963 u32 *p = (u32 *)handle_tlbs; 1964 struct uasm_label *l = labels; 1965 struct uasm_reloc *r = relocs; 1966 1967 memset(p, 0, handle_tlbs_end - (char *)p); 1968 memset(labels, 0, sizeof(labels)); 1969 memset(relocs, 0, sizeof(relocs)); 1970 1971 build_r3000_tlbchange_handler_head(&p, K0, K1); 1972 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); 1973 uasm_i_nop(&p); /* load delay */ 1974 build_make_write(&p, &r, K0, K1, -1); 1975 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1976 1977 uasm_l_nopage_tlbs(&l, p); 1978 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1979 uasm_i_nop(&p); 1980 1981 if (p >= (u32 *)handle_tlbs_end) 1982 panic("TLB store handler fastpath space exceeded"); 1983 1984 uasm_resolve_relocs(relocs, labels); 1985 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1986 (unsigned int)(p - (u32 *)handle_tlbs)); 1987 1988 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_end); 1989 } 1990 1991 static void build_r3000_tlb_modify_handler(void) 1992 { 1993 u32 *p = (u32 *)handle_tlbm; 1994 struct uasm_label *l = labels; 1995 struct uasm_reloc *r = relocs; 1996 1997 memset(p, 0, handle_tlbm_end - (char *)p); 1998 memset(labels, 0, sizeof(labels)); 1999 memset(relocs, 0, sizeof(relocs)); 2000 2001 build_r3000_tlbchange_handler_head(&p, K0, K1); 2002 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); 2003 uasm_i_nop(&p); /* load delay */ 2004 build_make_write(&p, &r, K0, K1, -1); 2005 build_r3000_pte_reload_tlbwi(&p, K0, K1); 2006 2007 uasm_l_nopage_tlbm(&l, p); 2008 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2009 uasm_i_nop(&p); 2010 2011 if (p >= (u32 *)handle_tlbm_end) 2012 panic("TLB modify handler fastpath space exceeded"); 2013 2014 uasm_resolve_relocs(relocs, labels); 2015 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2016 (unsigned int)(p - (u32 *)handle_tlbm)); 2017 2018 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_end); 2019 } 2020 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 2021 2022 static bool cpu_has_tlbex_tlbp_race(void) 2023 { 2024 /* 2025 * When a Hardware Table Walker is running it can replace TLB entries 2026 * at any time, leading to a race between it & the CPU. 2027 */ 2028 if (cpu_has_htw) 2029 return true; 2030 2031 /* 2032 * If the CPU shares FTLB RAM with its siblings then our entry may be 2033 * replaced at any time by a sibling performing a write to the FTLB. 2034 */ 2035 if (cpu_has_shared_ftlb_ram) 2036 return true; 2037 2038 /* In all other cases there ought to be no race condition to handle */ 2039 return false; 2040 } 2041 2042 /* 2043 * R4000 style TLB load/store/modify handlers. 2044 */ 2045 static struct work_registers 2046 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, 2047 struct uasm_reloc **r) 2048 { 2049 struct work_registers wr = build_get_work_registers(p); 2050 2051 #ifdef CONFIG_64BIT 2052 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ 2053 #else 2054 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ 2055 #endif 2056 2057 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2058 /* 2059 * For huge tlb entries, pmd doesn't contain an address but 2060 * instead contains the tlb pte. Check the PAGE_HUGE bit and 2061 * see if we need to jump to huge tlb processing. 2062 */ 2063 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); 2064 #endif 2065 2066 UASM_i_MFC0(p, wr.r1, C0_BADVADDR); 2067 UASM_i_LW(p, wr.r2, 0, wr.r2); 2068 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 2069 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 2070 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); 2071 2072 #ifdef CONFIG_SMP 2073 uasm_l_smp_pgtable_change(l, *p); 2074 #endif 2075 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ 2076 if (!m4kc_tlbp_war()) { 2077 build_tlb_probe_entry(p); 2078 if (cpu_has_tlbex_tlbp_race()) { 2079 /* race condition happens, leaving */ 2080 uasm_i_ehb(p); 2081 uasm_i_mfc0(p, wr.r3, C0_INDEX); 2082 uasm_il_bltz(p, r, wr.r3, label_leave); 2083 uasm_i_nop(p); 2084 } 2085 } 2086 return wr; 2087 } 2088 2089 static void 2090 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, 2091 struct uasm_reloc **r, unsigned int tmp, 2092 unsigned int ptr) 2093 { 2094 uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); 2095 uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); 2096 build_update_entries(p, tmp, ptr); 2097 build_tlb_write_entry(p, l, r, tlb_indexed); 2098 uasm_l_leave(l, *p); 2099 build_restore_work_registers(p); 2100 uasm_i_eret(p); /* return from trap */ 2101 2102 #ifdef CONFIG_64BIT 2103 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); 2104 #endif 2105 } 2106 2107 static void build_r4000_tlb_load_handler(void) 2108 { 2109 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl); 2110 struct uasm_label *l = labels; 2111 struct uasm_reloc *r = relocs; 2112 struct work_registers wr; 2113 2114 memset(p, 0, handle_tlbl_end - (char *)p); 2115 memset(labels, 0, sizeof(labels)); 2116 memset(relocs, 0, sizeof(relocs)); 2117 2118 if (bcm1250_m3_war()) { 2119 unsigned int segbits = 44; 2120 2121 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 2122 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 2123 uasm_i_xor(&p, K0, K0, K1); 2124 uasm_i_dsrl_safe(&p, K1, K0, 62); 2125 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 2126 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 2127 uasm_i_or(&p, K0, K0, K1); 2128 uasm_il_bnez(&p, &r, K0, label_leave); 2129 /* No need for uasm_i_nop */ 2130 } 2131 2132 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2133 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2134 if (m4kc_tlbp_war()) 2135 build_tlb_probe_entry(&p); 2136 2137 if (cpu_has_rixi && !cpu_has_rixiex) { 2138 /* 2139 * If the page is not _PAGE_VALID, RI or XI could not 2140 * have triggered it. Skip the expensive test.. 2141 */ 2142 if (use_bbit_insns()) { 2143 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2144 label_tlbl_goaround1); 2145 } else { 2146 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2147 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); 2148 } 2149 uasm_i_nop(&p); 2150 2151 /* 2152 * Warn if something may race with us & replace the TLB entry 2153 * before we read it here. Everything with such races should 2154 * also have dedicated RiXi exception handlers, so this 2155 * shouldn't be hit. 2156 */ 2157 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path"); 2158 2159 uasm_i_tlbr(&p); 2160 2161 switch (current_cpu_type()) { 2162 default: 2163 if (cpu_has_mips_r2_exec_hazard) { 2164 uasm_i_ehb(&p); 2165 fallthrough; 2166 2167 case CPU_CAVIUM_OCTEON: 2168 case CPU_CAVIUM_OCTEON_PLUS: 2169 case CPU_CAVIUM_OCTEON2: 2170 break; 2171 } 2172 } 2173 2174 /* Examine entrylo 0 or 1 based on ptr. */ 2175 if (use_bbit_insns()) { 2176 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2177 } else { 2178 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2179 uasm_i_beqz(&p, wr.r3, 8); 2180 } 2181 /* load it in the delay slot*/ 2182 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2183 /* load it if ptr is odd */ 2184 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2185 /* 2186 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2187 * XI must have triggered it. 2188 */ 2189 if (use_bbit_insns()) { 2190 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); 2191 uasm_i_nop(&p); 2192 uasm_l_tlbl_goaround1(&l, p); 2193 } else { 2194 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2195 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); 2196 uasm_i_nop(&p); 2197 } 2198 uasm_l_tlbl_goaround1(&l, p); 2199 } 2200 build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3); 2201 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2202 2203 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2204 /* 2205 * This is the entry point when build_r4000_tlbchange_handler_head 2206 * spots a huge page. 2207 */ 2208 uasm_l_tlb_huge_update(&l, p); 2209 iPTE_LW(&p, wr.r1, wr.r2); 2210 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2211 build_tlb_probe_entry(&p); 2212 2213 if (cpu_has_rixi && !cpu_has_rixiex) { 2214 /* 2215 * If the page is not _PAGE_VALID, RI or XI could not 2216 * have triggered it. Skip the expensive test.. 2217 */ 2218 if (use_bbit_insns()) { 2219 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2220 label_tlbl_goaround2); 2221 } else { 2222 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2223 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2224 } 2225 uasm_i_nop(&p); 2226 2227 /* 2228 * Warn if something may race with us & replace the TLB entry 2229 * before we read it here. Everything with such races should 2230 * also have dedicated RiXi exception handlers, so this 2231 * shouldn't be hit. 2232 */ 2233 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path"); 2234 2235 uasm_i_tlbr(&p); 2236 2237 switch (current_cpu_type()) { 2238 default: 2239 if (cpu_has_mips_r2_exec_hazard) { 2240 uasm_i_ehb(&p); 2241 2242 case CPU_CAVIUM_OCTEON: 2243 case CPU_CAVIUM_OCTEON_PLUS: 2244 case CPU_CAVIUM_OCTEON2: 2245 break; 2246 } 2247 } 2248 2249 /* Examine entrylo 0 or 1 based on ptr. */ 2250 if (use_bbit_insns()) { 2251 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2252 } else { 2253 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2254 uasm_i_beqz(&p, wr.r3, 8); 2255 } 2256 /* load it in the delay slot*/ 2257 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2258 /* load it if ptr is odd */ 2259 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2260 /* 2261 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2262 * XI must have triggered it. 2263 */ 2264 if (use_bbit_insns()) { 2265 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); 2266 } else { 2267 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2268 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2269 } 2270 if (PM_DEFAULT_MASK == 0) 2271 uasm_i_nop(&p); 2272 /* 2273 * We clobbered C0_PAGEMASK, restore it. On the other branch 2274 * it is restored in build_huge_tlb_write_entry. 2275 */ 2276 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); 2277 2278 uasm_l_tlbl_goaround2(&l, p); 2279 } 2280 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); 2281 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); 2282 #endif 2283 2284 uasm_l_nopage_tlbl(&l, p); 2285 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2286 uasm_i_sync(&p, 0); 2287 build_restore_work_registers(&p); 2288 #ifdef CONFIG_CPU_MICROMIPS 2289 if ((unsigned long)tlb_do_page_fault_0 & 1) { 2290 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); 2291 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); 2292 uasm_i_jr(&p, K0); 2293 } else 2294 #endif 2295 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 2296 uasm_i_nop(&p); 2297 2298 if (p >= (u32 *)handle_tlbl_end) 2299 panic("TLB load handler fastpath space exceeded"); 2300 2301 uasm_resolve_relocs(relocs, labels); 2302 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 2303 (unsigned int)(p - (u32 *)handle_tlbl)); 2304 2305 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_end); 2306 } 2307 2308 static void build_r4000_tlb_store_handler(void) 2309 { 2310 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs); 2311 struct uasm_label *l = labels; 2312 struct uasm_reloc *r = relocs; 2313 struct work_registers wr; 2314 2315 memset(p, 0, handle_tlbs_end - (char *)p); 2316 memset(labels, 0, sizeof(labels)); 2317 memset(relocs, 0, sizeof(relocs)); 2318 2319 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2320 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2321 if (m4kc_tlbp_war()) 2322 build_tlb_probe_entry(&p); 2323 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); 2324 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2325 2326 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2327 /* 2328 * This is the entry point when 2329 * build_r4000_tlbchange_handler_head spots a huge page. 2330 */ 2331 uasm_l_tlb_huge_update(&l, p); 2332 iPTE_LW(&p, wr.r1, wr.r2); 2333 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2334 build_tlb_probe_entry(&p); 2335 uasm_i_ori(&p, wr.r1, wr.r1, 2336 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2337 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); 2338 #endif 2339 2340 uasm_l_nopage_tlbs(&l, p); 2341 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2342 uasm_i_sync(&p, 0); 2343 build_restore_work_registers(&p); 2344 #ifdef CONFIG_CPU_MICROMIPS 2345 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2346 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2347 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2348 uasm_i_jr(&p, K0); 2349 } else 2350 #endif 2351 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2352 uasm_i_nop(&p); 2353 2354 if (p >= (u32 *)handle_tlbs_end) 2355 panic("TLB store handler fastpath space exceeded"); 2356 2357 uasm_resolve_relocs(relocs, labels); 2358 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 2359 (unsigned int)(p - (u32 *)handle_tlbs)); 2360 2361 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_end); 2362 } 2363 2364 static void build_r4000_tlb_modify_handler(void) 2365 { 2366 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm); 2367 struct uasm_label *l = labels; 2368 struct uasm_reloc *r = relocs; 2369 struct work_registers wr; 2370 2371 memset(p, 0, handle_tlbm_end - (char *)p); 2372 memset(labels, 0, sizeof(labels)); 2373 memset(relocs, 0, sizeof(relocs)); 2374 2375 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2376 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2377 if (m4kc_tlbp_war()) 2378 build_tlb_probe_entry(&p); 2379 /* Present and writable bits set, set accessed and dirty bits. */ 2380 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); 2381 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2382 2383 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2384 /* 2385 * This is the entry point when 2386 * build_r4000_tlbchange_handler_head spots a huge page. 2387 */ 2388 uasm_l_tlb_huge_update(&l, p); 2389 iPTE_LW(&p, wr.r1, wr.r2); 2390 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2391 build_tlb_probe_entry(&p); 2392 uasm_i_ori(&p, wr.r1, wr.r1, 2393 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2394 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0); 2395 #endif 2396 2397 uasm_l_nopage_tlbm(&l, p); 2398 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2399 uasm_i_sync(&p, 0); 2400 build_restore_work_registers(&p); 2401 #ifdef CONFIG_CPU_MICROMIPS 2402 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2403 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2404 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2405 uasm_i_jr(&p, K0); 2406 } else 2407 #endif 2408 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2409 uasm_i_nop(&p); 2410 2411 if (p >= (u32 *)handle_tlbm_end) 2412 panic("TLB modify handler fastpath space exceeded"); 2413 2414 uasm_resolve_relocs(relocs, labels); 2415 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2416 (unsigned int)(p - (u32 *)handle_tlbm)); 2417 2418 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_end); 2419 } 2420 2421 static void flush_tlb_handlers(void) 2422 { 2423 local_flush_icache_range((unsigned long)handle_tlbl, 2424 (unsigned long)handle_tlbl_end); 2425 local_flush_icache_range((unsigned long)handle_tlbs, 2426 (unsigned long)handle_tlbs_end); 2427 local_flush_icache_range((unsigned long)handle_tlbm, 2428 (unsigned long)handle_tlbm_end); 2429 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, 2430 (unsigned long)tlbmiss_handler_setup_pgd_end); 2431 } 2432 2433 static void print_htw_config(void) 2434 { 2435 unsigned long config; 2436 unsigned int pwctl; 2437 const int field = 2 * sizeof(unsigned long); 2438 2439 config = read_c0_pwfield(); 2440 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n", 2441 field, config, 2442 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT, 2443 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT, 2444 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT, 2445 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT, 2446 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); 2447 2448 config = read_c0_pwsize(); 2449 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", 2450 field, config, 2451 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT, 2452 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, 2453 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, 2454 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, 2455 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT, 2456 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); 2457 2458 pwctl = read_c0_pwctl(); 2459 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", 2460 pwctl, 2461 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, 2462 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT, 2463 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT, 2464 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT, 2465 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, 2466 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, 2467 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); 2468 } 2469 2470 static void config_htw_params(void) 2471 { 2472 unsigned long pwfield, pwsize, ptei; 2473 unsigned int config; 2474 2475 /* 2476 * We are using 2-level page tables, so we only need to 2477 * setup GDW and PTW appropriately. UDW and MDW will remain 0. 2478 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to 2479 * write values less than 0xc in these fields because the entire 2480 * write will be dropped. As a result of which, we must preserve 2481 * the original reset values and overwrite only what we really want. 2482 */ 2483 2484 pwfield = read_c0_pwfield(); 2485 /* re-initialize the GDI field */ 2486 pwfield &= ~MIPS_PWFIELD_GDI_MASK; 2487 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT; 2488 /* re-initialize the PTI field including the even/odd bit */ 2489 pwfield &= ~MIPS_PWFIELD_PTI_MASK; 2490 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT; 2491 if (CONFIG_PGTABLE_LEVELS >= 3) { 2492 pwfield &= ~MIPS_PWFIELD_MDI_MASK; 2493 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT; 2494 } 2495 /* Set the PTEI right shift */ 2496 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT; 2497 pwfield |= ptei; 2498 write_c0_pwfield(pwfield); 2499 /* Check whether the PTEI value is supported */ 2500 back_to_back_c0_hazard(); 2501 pwfield = read_c0_pwfield(); 2502 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT) 2503 != ptei) { 2504 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled", 2505 ptei); 2506 /* 2507 * Drop option to avoid HTW being enabled via another path 2508 * (eg htw_reset()) 2509 */ 2510 current_cpu_data.options &= ~MIPS_CPU_HTW; 2511 return; 2512 } 2513 2514 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; 2515 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; 2516 if (CONFIG_PGTABLE_LEVELS >= 3) 2517 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; 2518 2519 /* Set pointer size to size of directory pointers */ 2520 if (IS_ENABLED(CONFIG_64BIT)) 2521 pwsize |= MIPS_PWSIZE_PS_MASK; 2522 /* PTEs may be multiple pointers long (e.g. with XPA) */ 2523 pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT) 2524 & MIPS_PWSIZE_PTEW_MASK; 2525 2526 write_c0_pwsize(pwsize); 2527 2528 /* Make sure everything is set before we enable the HTW */ 2529 back_to_back_c0_hazard(); 2530 2531 /* 2532 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of 2533 * the pwctl fields. 2534 */ 2535 config = 1 << MIPS_PWCTL_PWEN_SHIFT; 2536 if (IS_ENABLED(CONFIG_64BIT)) 2537 config |= MIPS_PWCTL_XU_MASK; 2538 write_c0_pwctl(config); 2539 pr_info("Hardware Page Table Walker enabled\n"); 2540 2541 print_htw_config(); 2542 } 2543 2544 static void config_xpa_params(void) 2545 { 2546 #ifdef CONFIG_XPA 2547 unsigned int pagegrain; 2548 2549 if (mips_xpa_disabled) { 2550 pr_info("Extended Physical Addressing (XPA) disabled\n"); 2551 return; 2552 } 2553 2554 pagegrain = read_c0_pagegrain(); 2555 write_c0_pagegrain(pagegrain | PG_ELPA); 2556 back_to_back_c0_hazard(); 2557 pagegrain = read_c0_pagegrain(); 2558 2559 if (pagegrain & PG_ELPA) 2560 pr_info("Extended Physical Addressing (XPA) enabled\n"); 2561 else 2562 panic("Extended Physical Addressing (XPA) disabled"); 2563 #endif 2564 } 2565 2566 static void check_pabits(void) 2567 { 2568 unsigned long entry; 2569 unsigned pabits, fillbits; 2570 2571 if (!cpu_has_rixi || !_PAGE_NO_EXEC) { 2572 /* 2573 * We'll only be making use of the fact that we can rotate bits 2574 * into the fill if the CPU supports RIXI, so don't bother 2575 * probing this for CPUs which don't. 2576 */ 2577 return; 2578 } 2579 2580 write_c0_entrylo0(~0ul); 2581 back_to_back_c0_hazard(); 2582 entry = read_c0_entrylo0(); 2583 2584 /* clear all non-PFN bits */ 2585 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1); 2586 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); 2587 2588 /* find a lower bound on PABITS, and upper bound on fill bits */ 2589 pabits = fls_long(entry) + 6; 2590 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0); 2591 2592 /* minus the RI & XI bits */ 2593 fillbits -= min_t(unsigned, fillbits, 2); 2594 2595 if (fillbits >= ilog2(_PAGE_NO_EXEC)) 2596 fill_includes_sw_bits = true; 2597 2598 pr_debug("Entry* registers contain %u fill bits\n", fillbits); 2599 } 2600 2601 void build_tlb_refill_handler(void) 2602 { 2603 /* 2604 * The refill handler is generated per-CPU, multi-node systems 2605 * may have local storage for it. The other handlers are only 2606 * needed once. 2607 */ 2608 static int run_once = 0; 2609 2610 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi) 2611 panic("Kernels supporting XPA currently require CPUs with RIXI"); 2612 2613 output_pgtable_bits_defines(); 2614 check_pabits(); 2615 2616 #ifdef CONFIG_64BIT 2617 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 2618 #endif 2619 2620 if (cpu_has_3kex) { 2621 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 2622 if (!run_once) { 2623 build_setup_pgd(); 2624 build_r3000_tlb_refill_handler(); 2625 build_r3000_tlb_load_handler(); 2626 build_r3000_tlb_store_handler(); 2627 build_r3000_tlb_modify_handler(); 2628 flush_tlb_handlers(); 2629 run_once++; 2630 } 2631 #else 2632 panic("No R3000 TLB refill handler"); 2633 #endif 2634 return; 2635 } 2636 2637 if (cpu_has_ldpte) 2638 setup_pw(); 2639 2640 if (!run_once) { 2641 scratch_reg = allocate_kscratch(); 2642 build_setup_pgd(); 2643 build_r4000_tlb_load_handler(); 2644 build_r4000_tlb_store_handler(); 2645 build_r4000_tlb_modify_handler(); 2646 if (cpu_has_ldpte) 2647 build_loongson3_tlb_refill_handler(); 2648 else 2649 build_r4000_tlb_refill_handler(); 2650 flush_tlb_handlers(); 2651 run_once++; 2652 } 2653 if (cpu_has_xpa) 2654 config_xpa_params(); 2655 if (cpu_has_htw) 2656 config_htw_params(); 2657 } 2658