1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 * Copyright (C) 2008, 2009 Cavium Networks, Inc. 12 * Copyright (C) 2011 MIPS Technologies, Inc. 13 * 14 * ... and the days got worse and worse and now you see 15 * I've gone completely out of my mind. 16 * 17 * They're coming to take me a away haha 18 * they're coming to take me a away hoho hihi haha 19 * to the funny farm where code is beautiful all the time ... 20 * 21 * (Condolences to Napoleon XIV) 22 */ 23 24 #include <linux/bug.h> 25 #include <linux/export.h> 26 #include <linux/kernel.h> 27 #include <linux/types.h> 28 #include <linux/smp.h> 29 #include <linux/string.h> 30 #include <linux/cache.h> 31 32 #include <asm/cacheflush.h> 33 #include <asm/cpu-type.h> 34 #include <asm/mmu_context.h> 35 #include <asm/pgtable.h> 36 #include <asm/war.h> 37 #include <asm/uasm.h> 38 #include <asm/setup.h> 39 #include <asm/tlbex.h> 40 41 static int mips_xpa_disabled; 42 43 static int __init xpa_disable(char *s) 44 { 45 mips_xpa_disabled = 1; 46 47 return 1; 48 } 49 50 __setup("noxpa", xpa_disable); 51 52 /* 53 * TLB load/store/modify handlers. 54 * 55 * Only the fastpath gets synthesized at runtime, the slowpath for 56 * do_page_fault remains normal asm. 57 */ 58 extern void tlb_do_page_fault_0(void); 59 extern void tlb_do_page_fault_1(void); 60 61 struct work_registers { 62 int r1; 63 int r2; 64 int r3; 65 }; 66 67 struct tlb_reg_save { 68 unsigned long a; 69 unsigned long b; 70 } ____cacheline_aligned_in_smp; 71 72 static struct tlb_reg_save handler_reg_save[NR_CPUS]; 73 74 static inline int r45k_bvahwbug(void) 75 { 76 /* XXX: We should probe for the presence of this bug, but we don't. */ 77 return 0; 78 } 79 80 static inline int r4k_250MHZhwbug(void) 81 { 82 /* XXX: We should probe for the presence of this bug, but we don't. */ 83 return 0; 84 } 85 86 static inline int __maybe_unused bcm1250_m3_war(void) 87 { 88 return BCM1250_M3_WAR; 89 } 90 91 static inline int __maybe_unused r10000_llsc_war(void) 92 { 93 return R10000_LLSC_WAR; 94 } 95 96 static int use_bbit_insns(void) 97 { 98 switch (current_cpu_type()) { 99 case CPU_CAVIUM_OCTEON: 100 case CPU_CAVIUM_OCTEON_PLUS: 101 case CPU_CAVIUM_OCTEON2: 102 case CPU_CAVIUM_OCTEON3: 103 return 1; 104 default: 105 return 0; 106 } 107 } 108 109 static int use_lwx_insns(void) 110 { 111 switch (current_cpu_type()) { 112 case CPU_CAVIUM_OCTEON2: 113 case CPU_CAVIUM_OCTEON3: 114 return 1; 115 default: 116 return 0; 117 } 118 } 119 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ 120 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 121 static bool scratchpad_available(void) 122 { 123 return true; 124 } 125 static int scratchpad_offset(int i) 126 { 127 /* 128 * CVMSEG starts at address -32768 and extends for 129 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. 130 */ 131 i += 1; /* Kernel use starts at the top and works down. */ 132 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; 133 } 134 #else 135 static bool scratchpad_available(void) 136 { 137 return false; 138 } 139 static int scratchpad_offset(int i) 140 { 141 BUG(); 142 /* Really unreachable, but evidently some GCC want this. */ 143 return 0; 144 } 145 #endif 146 /* 147 * Found by experiment: At least some revisions of the 4kc throw under 148 * some circumstances a machine check exception, triggered by invalid 149 * values in the index register. Delaying the tlbp instruction until 150 * after the next branch, plus adding an additional nop in front of 151 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows 152 * why; it's not an issue caused by the core RTL. 153 * 154 */ 155 static int m4kc_tlbp_war(void) 156 { 157 return current_cpu_type() == CPU_4KC; 158 } 159 160 /* Handle labels (which must be positive integers). */ 161 enum label_id { 162 label_second_part = 1, 163 label_leave, 164 label_vmalloc, 165 label_vmalloc_done, 166 label_tlbw_hazard_0, 167 label_split = label_tlbw_hazard_0 + 8, 168 label_tlbl_goaround1, 169 label_tlbl_goaround2, 170 label_nopage_tlbl, 171 label_nopage_tlbs, 172 label_nopage_tlbm, 173 label_smp_pgtable_change, 174 label_r3000_write_probe_fail, 175 label_large_segbits_fault, 176 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 177 label_tlb_huge_update, 178 #endif 179 }; 180 181 UASM_L_LA(_second_part) 182 UASM_L_LA(_leave) 183 UASM_L_LA(_vmalloc) 184 UASM_L_LA(_vmalloc_done) 185 /* _tlbw_hazard_x is handled differently. */ 186 UASM_L_LA(_split) 187 UASM_L_LA(_tlbl_goaround1) 188 UASM_L_LA(_tlbl_goaround2) 189 UASM_L_LA(_nopage_tlbl) 190 UASM_L_LA(_nopage_tlbs) 191 UASM_L_LA(_nopage_tlbm) 192 UASM_L_LA(_smp_pgtable_change) 193 UASM_L_LA(_r3000_write_probe_fail) 194 UASM_L_LA(_large_segbits_fault) 195 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 196 UASM_L_LA(_tlb_huge_update) 197 #endif 198 199 static int hazard_instance; 200 201 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) 202 { 203 switch (instance) { 204 case 0 ... 7: 205 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); 206 return; 207 default: 208 BUG(); 209 } 210 } 211 212 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) 213 { 214 switch (instance) { 215 case 0 ... 7: 216 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); 217 break; 218 default: 219 BUG(); 220 } 221 } 222 223 /* 224 * pgtable bits are assigned dynamically depending on processor feature 225 * and statically based on kernel configuration. This spits out the actual 226 * values the kernel is using. Required to make sense from disassembled 227 * TLB exception handlers. 228 */ 229 static void output_pgtable_bits_defines(void) 230 { 231 #define pr_define(fmt, ...) \ 232 pr_debug("#define " fmt, ##__VA_ARGS__) 233 234 pr_debug("#include <asm/asm.h>\n"); 235 pr_debug("#include <asm/regdef.h>\n"); 236 pr_debug("\n"); 237 238 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); 239 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); 240 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); 241 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); 242 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); 243 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 244 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); 245 #endif 246 #ifdef _PAGE_NO_EXEC_SHIFT 247 if (cpu_has_rixi) 248 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); 249 #endif 250 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); 251 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); 252 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); 253 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); 254 pr_debug("\n"); 255 } 256 257 static inline void dump_handler(const char *symbol, const void *start, const void *end) 258 { 259 unsigned int count = (end - start) / sizeof(u32); 260 const u32 *handler = start; 261 int i; 262 263 pr_debug("LEAF(%s)\n", symbol); 264 265 pr_debug("\t.set push\n"); 266 pr_debug("\t.set noreorder\n"); 267 268 for (i = 0; i < count; i++) 269 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); 270 271 pr_debug("\t.set\tpop\n"); 272 273 pr_debug("\tEND(%s)\n", symbol); 274 } 275 276 /* The only general purpose registers allowed in TLB handlers. */ 277 #define K0 26 278 #define K1 27 279 280 /* Some CP0 registers */ 281 #define C0_INDEX 0, 0 282 #define C0_ENTRYLO0 2, 0 283 #define C0_TCBIND 2, 2 284 #define C0_ENTRYLO1 3, 0 285 #define C0_CONTEXT 4, 0 286 #define C0_PAGEMASK 5, 0 287 #define C0_PWBASE 5, 5 288 #define C0_PWFIELD 5, 6 289 #define C0_PWSIZE 5, 7 290 #define C0_PWCTL 6, 6 291 #define C0_BADVADDR 8, 0 292 #define C0_PGD 9, 7 293 #define C0_ENTRYHI 10, 0 294 #define C0_EPC 14, 0 295 #define C0_XCONTEXT 20, 0 296 297 #ifdef CONFIG_64BIT 298 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) 299 #else 300 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) 301 #endif 302 303 /* The worst case length of the handler is around 18 instructions for 304 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 305 * Maximum space available is 32 instructions for R3000 and 64 306 * instructions for R4000. 307 * 308 * We deliberately chose a buffer size of 128, so we won't scribble 309 * over anything important on overflow before we panic. 310 */ 311 static u32 tlb_handler[128]; 312 313 /* simply assume worst case size for labels and relocs */ 314 static struct uasm_label labels[128]; 315 static struct uasm_reloc relocs[128]; 316 317 static int check_for_high_segbits; 318 static bool fill_includes_sw_bits; 319 320 static unsigned int kscratch_used_mask; 321 322 static inline int __maybe_unused c0_kscratch(void) 323 { 324 switch (current_cpu_type()) { 325 case CPU_XLP: 326 case CPU_XLR: 327 return 22; 328 default: 329 return 31; 330 } 331 } 332 333 static int allocate_kscratch(void) 334 { 335 int r; 336 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; 337 338 r = ffs(a); 339 340 if (r == 0) 341 return -1; 342 343 r--; /* make it zero based */ 344 345 kscratch_used_mask |= (1 << r); 346 347 return r; 348 } 349 350 static int scratch_reg; 351 int pgd_reg; 352 EXPORT_SYMBOL_GPL(pgd_reg); 353 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; 354 355 static struct work_registers build_get_work_registers(u32 **p) 356 { 357 struct work_registers r; 358 359 if (scratch_reg >= 0) { 360 /* Save in CPU local C0_KScratch? */ 361 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); 362 r.r1 = K0; 363 r.r2 = K1; 364 r.r3 = 1; 365 return r; 366 } 367 368 if (num_possible_cpus() > 1) { 369 /* Get smp_processor_id */ 370 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); 371 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); 372 373 /* handler_reg_save index in K0 */ 374 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); 375 376 UASM_i_LA(p, K1, (long)&handler_reg_save); 377 UASM_i_ADDU(p, K0, K0, K1); 378 } else { 379 UASM_i_LA(p, K0, (long)&handler_reg_save); 380 } 381 /* K0 now points to save area, save $1 and $2 */ 382 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); 383 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); 384 385 r.r1 = K1; 386 r.r2 = 1; 387 r.r3 = 2; 388 return r; 389 } 390 391 static void build_restore_work_registers(u32 **p) 392 { 393 if (scratch_reg >= 0) { 394 uasm_i_ehb(p); 395 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 396 return; 397 } 398 /* K0 already points to save area, restore $1 and $2 */ 399 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); 400 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); 401 } 402 403 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 404 405 /* 406 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, 407 * we cannot do r3000 under these circumstances. 408 * 409 * The R3000 TLB handler is simple. 410 */ 411 static void build_r3000_tlb_refill_handler(void) 412 { 413 long pgdc = (long)pgd_current; 414 u32 *p; 415 416 memset(tlb_handler, 0, sizeof(tlb_handler)); 417 p = tlb_handler; 418 419 uasm_i_mfc0(&p, K0, C0_BADVADDR); 420 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ 421 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); 422 uasm_i_srl(&p, K0, K0, 22); /* load delay */ 423 uasm_i_sll(&p, K0, K0, 2); 424 uasm_i_addu(&p, K1, K1, K0); 425 uasm_i_mfc0(&p, K0, C0_CONTEXT); 426 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ 427 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ 428 uasm_i_addu(&p, K1, K1, K0); 429 uasm_i_lw(&p, K0, 0, K1); 430 uasm_i_nop(&p); /* load delay */ 431 uasm_i_mtc0(&p, K0, C0_ENTRYLO0); 432 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 433 uasm_i_tlbwr(&p); /* cp0 delay */ 434 uasm_i_jr(&p, K1); 435 uasm_i_rfe(&p); /* branch delay */ 436 437 if (p > tlb_handler + 32) 438 panic("TLB refill handler space exceeded"); 439 440 pr_debug("Wrote TLB refill handler (%u instructions).\n", 441 (unsigned int)(p - tlb_handler)); 442 443 memcpy((void *)ebase, tlb_handler, 0x80); 444 local_flush_icache_range(ebase, ebase + 0x80); 445 dump_handler("r3000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x80)); 446 } 447 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 448 449 /* 450 * The R4000 TLB handler is much more complicated. We have two 451 * consecutive handler areas with 32 instructions space each. 452 * Since they aren't used at the same time, we can overflow in the 453 * other one.To keep things simple, we first assume linear space, 454 * then we relocate it to the final handler layout as needed. 455 */ 456 static u32 final_handler[64]; 457 458 /* 459 * Hazards 460 * 461 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 462 * 2. A timing hazard exists for the TLBP instruction. 463 * 464 * stalling_instruction 465 * TLBP 466 * 467 * The JTLB is being read for the TLBP throughout the stall generated by the 468 * previous instruction. This is not really correct as the stalling instruction 469 * can modify the address used to access the JTLB. The failure symptom is that 470 * the TLBP instruction will use an address created for the stalling instruction 471 * and not the address held in C0_ENHI and thus report the wrong results. 472 * 473 * The software work-around is to not allow the instruction preceding the TLBP 474 * to stall - make it an NOP or some other instruction guaranteed not to stall. 475 * 476 * Errata 2 will not be fixed. This errata is also on the R5000. 477 * 478 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 479 */ 480 static void __maybe_unused build_tlb_probe_entry(u32 **p) 481 { 482 switch (current_cpu_type()) { 483 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ 484 case CPU_R4600: 485 case CPU_R4700: 486 case CPU_R5000: 487 case CPU_NEVADA: 488 uasm_i_nop(p); 489 uasm_i_tlbp(p); 490 break; 491 492 default: 493 uasm_i_tlbp(p); 494 break; 495 } 496 } 497 498 void build_tlb_write_entry(u32 **p, struct uasm_label **l, 499 struct uasm_reloc **r, 500 enum tlb_write_entry wmode) 501 { 502 void(*tlbw)(u32 **) = NULL; 503 504 switch (wmode) { 505 case tlb_random: tlbw = uasm_i_tlbwr; break; 506 case tlb_indexed: tlbw = uasm_i_tlbwi; break; 507 } 508 509 if (cpu_has_mips_r2_r6) { 510 if (cpu_has_mips_r2_exec_hazard) 511 uasm_i_ehb(p); 512 tlbw(p); 513 return; 514 } 515 516 switch (current_cpu_type()) { 517 case CPU_R4000PC: 518 case CPU_R4000SC: 519 case CPU_R4000MC: 520 case CPU_R4400PC: 521 case CPU_R4400SC: 522 case CPU_R4400MC: 523 /* 524 * This branch uses up a mtc0 hazard nop slot and saves 525 * two nops after the tlbw instruction. 526 */ 527 uasm_bgezl_hazard(p, r, hazard_instance); 528 tlbw(p); 529 uasm_bgezl_label(l, p, hazard_instance); 530 hazard_instance++; 531 uasm_i_nop(p); 532 break; 533 534 case CPU_R4600: 535 case CPU_R4700: 536 uasm_i_nop(p); 537 tlbw(p); 538 uasm_i_nop(p); 539 break; 540 541 case CPU_R5000: 542 case CPU_NEVADA: 543 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 544 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 545 tlbw(p); 546 break; 547 548 case CPU_R4300: 549 case CPU_5KC: 550 case CPU_TX49XX: 551 case CPU_PR4450: 552 case CPU_XLR: 553 uasm_i_nop(p); 554 tlbw(p); 555 break; 556 557 case CPU_R10000: 558 case CPU_R12000: 559 case CPU_R14000: 560 case CPU_R16000: 561 case CPU_4KC: 562 case CPU_4KEC: 563 case CPU_M14KC: 564 case CPU_M14KEC: 565 case CPU_SB1: 566 case CPU_SB1A: 567 case CPU_4KSC: 568 case CPU_20KC: 569 case CPU_25KF: 570 case CPU_BMIPS32: 571 case CPU_BMIPS3300: 572 case CPU_BMIPS4350: 573 case CPU_BMIPS4380: 574 case CPU_BMIPS5000: 575 case CPU_LOONGSON2: 576 case CPU_LOONGSON3: 577 case CPU_R5500: 578 if (m4kc_tlbp_war()) 579 uasm_i_nop(p); 580 /* fall through */ 581 case CPU_ALCHEMY: 582 tlbw(p); 583 break; 584 585 case CPU_RM7000: 586 uasm_i_nop(p); 587 uasm_i_nop(p); 588 uasm_i_nop(p); 589 uasm_i_nop(p); 590 tlbw(p); 591 break; 592 593 case CPU_VR4111: 594 case CPU_VR4121: 595 case CPU_VR4122: 596 case CPU_VR4181: 597 case CPU_VR4181A: 598 uasm_i_nop(p); 599 uasm_i_nop(p); 600 tlbw(p); 601 uasm_i_nop(p); 602 uasm_i_nop(p); 603 break; 604 605 case CPU_VR4131: 606 case CPU_VR4133: 607 case CPU_R5432: 608 uasm_i_nop(p); 609 uasm_i_nop(p); 610 tlbw(p); 611 break; 612 613 case CPU_JZRISC: 614 tlbw(p); 615 uasm_i_nop(p); 616 break; 617 618 default: 619 panic("No TLB refill handler yet (CPU type: %d)", 620 current_cpu_type()); 621 break; 622 } 623 } 624 EXPORT_SYMBOL_GPL(build_tlb_write_entry); 625 626 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, 627 unsigned int reg) 628 { 629 if (_PAGE_GLOBAL_SHIFT == 0) { 630 /* pte_t is already in EntryLo format */ 631 return; 632 } 633 634 if (cpu_has_rixi && _PAGE_NO_EXEC) { 635 if (fill_includes_sw_bits) { 636 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); 637 } else { 638 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); 639 UASM_i_ROTR(p, reg, reg, 640 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); 641 } 642 } else { 643 #ifdef CONFIG_PHYS_ADDR_T_64BIT 644 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); 645 #else 646 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); 647 #endif 648 } 649 } 650 651 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 652 653 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, 654 unsigned int tmp, enum label_id lid, 655 int restore_scratch) 656 { 657 if (restore_scratch) { 658 /* Reset default page size */ 659 if (PM_DEFAULT_MASK >> 16) { 660 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 661 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 662 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 663 uasm_il_b(p, r, lid); 664 } else if (PM_DEFAULT_MASK) { 665 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 666 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 667 uasm_il_b(p, r, lid); 668 } else { 669 uasm_i_mtc0(p, 0, C0_PAGEMASK); 670 uasm_il_b(p, r, lid); 671 } 672 if (scratch_reg >= 0) { 673 uasm_i_ehb(p); 674 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 675 } else { 676 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 677 } 678 } else { 679 /* Reset default page size */ 680 if (PM_DEFAULT_MASK >> 16) { 681 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 682 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 683 uasm_il_b(p, r, lid); 684 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 685 } else if (PM_DEFAULT_MASK) { 686 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 687 uasm_il_b(p, r, lid); 688 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 689 } else { 690 uasm_il_b(p, r, lid); 691 uasm_i_mtc0(p, 0, C0_PAGEMASK); 692 } 693 } 694 } 695 696 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, 697 struct uasm_reloc **r, 698 unsigned int tmp, 699 enum tlb_write_entry wmode, 700 int restore_scratch) 701 { 702 /* Set huge page tlb entry size */ 703 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); 704 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); 705 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 706 707 build_tlb_write_entry(p, l, r, wmode); 708 709 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); 710 } 711 712 /* 713 * Check if Huge PTE is present, if so then jump to LABEL. 714 */ 715 static void 716 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, 717 unsigned int pmd, int lid) 718 { 719 UASM_i_LW(p, tmp, 0, pmd); 720 if (use_bbit_insns()) { 721 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); 722 } else { 723 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); 724 uasm_il_bnez(p, r, tmp, lid); 725 } 726 } 727 728 static void build_huge_update_entries(u32 **p, unsigned int pte, 729 unsigned int tmp) 730 { 731 int small_sequence; 732 733 /* 734 * A huge PTE describes an area the size of the 735 * configured huge page size. This is twice the 736 * of the large TLB entry size we intend to use. 737 * A TLB entry half the size of the configured 738 * huge page size is configured into entrylo0 739 * and entrylo1 to cover the contiguous huge PTE 740 * address space. 741 */ 742 small_sequence = (HPAGE_SIZE >> 7) < 0x10000; 743 744 /* We can clobber tmp. It isn't used after this.*/ 745 if (!small_sequence) 746 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); 747 748 build_convert_pte_to_entrylo(p, pte); 749 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ 750 /* convert to entrylo1 */ 751 if (small_sequence) 752 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); 753 else 754 UASM_i_ADDU(p, pte, pte, tmp); 755 756 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ 757 } 758 759 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, 760 struct uasm_label **l, 761 unsigned int pte, 762 unsigned int ptr, 763 unsigned int flush) 764 { 765 #ifdef CONFIG_SMP 766 UASM_i_SC(p, pte, 0, ptr); 767 uasm_il_beqz(p, r, pte, label_tlb_huge_update); 768 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ 769 #else 770 UASM_i_SW(p, pte, 0, ptr); 771 #endif 772 if (cpu_has_ftlb && flush) { 773 BUG_ON(!cpu_has_tlbinv); 774 775 UASM_i_MFC0(p, ptr, C0_ENTRYHI); 776 uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); 777 UASM_i_MTC0(p, ptr, C0_ENTRYHI); 778 build_tlb_write_entry(p, l, r, tlb_indexed); 779 780 uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); 781 UASM_i_MTC0(p, ptr, C0_ENTRYHI); 782 build_huge_update_entries(p, pte, ptr); 783 build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0); 784 785 return; 786 } 787 788 build_huge_update_entries(p, pte, ptr); 789 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); 790 } 791 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 792 793 #ifdef CONFIG_64BIT 794 /* 795 * TMP and PTR are scratch. 796 * TMP will be clobbered, PTR will hold the pmd entry. 797 */ 798 void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 799 unsigned int tmp, unsigned int ptr) 800 { 801 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 802 long pgdc = (long)pgd_current; 803 #endif 804 /* 805 * The vmalloc handling is not in the hotpath. 806 */ 807 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 808 809 if (check_for_high_segbits) { 810 /* 811 * The kernel currently implicitely assumes that the 812 * MIPS SEGBITS parameter for the processor is 813 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never 814 * allocate virtual addresses outside the maximum 815 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But 816 * that doesn't prevent user code from accessing the 817 * higher xuseg addresses. Here, we make sure that 818 * everything but the lower xuseg addresses goes down 819 * the module_alloc/vmalloc path. 820 */ 821 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 822 uasm_il_bnez(p, r, ptr, label_vmalloc); 823 } else { 824 uasm_il_bltz(p, r, tmp, label_vmalloc); 825 } 826 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 827 828 if (pgd_reg != -1) { 829 /* pgd is in pgd_reg */ 830 if (cpu_has_ldpte) 831 UASM_i_MFC0(p, ptr, C0_PWBASE); 832 else 833 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 834 } else { 835 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT) 836 /* 837 * &pgd << 11 stored in CONTEXT [23..63]. 838 */ 839 UASM_i_MFC0(p, ptr, C0_CONTEXT); 840 841 /* Clear lower 23 bits of context. */ 842 uasm_i_dins(p, ptr, 0, 0, 23); 843 844 /* 1 0 1 0 1 << 6 xkphys cached */ 845 uasm_i_ori(p, ptr, ptr, 0x540); 846 uasm_i_drotr(p, ptr, ptr, 11); 847 #elif defined(CONFIG_SMP) 848 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); 849 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 850 UASM_i_LA_mostly(p, tmp, pgdc); 851 uasm_i_daddu(p, ptr, ptr, tmp); 852 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 853 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 854 #else 855 UASM_i_LA_mostly(p, ptr, pgdc); 856 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 857 #endif 858 } 859 860 uasm_l_vmalloc_done(l, *p); 861 862 /* get pgd offset in bytes */ 863 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); 864 865 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 866 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 867 #ifndef __PAGETABLE_PUD_FOLDED 868 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 869 uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */ 870 uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */ 871 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3); 872 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */ 873 #endif 874 #ifndef __PAGETABLE_PMD_FOLDED 875 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 876 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 877 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 878 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 879 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 880 #endif 881 } 882 EXPORT_SYMBOL_GPL(build_get_pmde64); 883 884 /* 885 * BVADDR is the faulting address, PTR is scratch. 886 * PTR will hold the pgd for vmalloc. 887 */ 888 static void 889 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 890 unsigned int bvaddr, unsigned int ptr, 891 enum vmalloc64_mode mode) 892 { 893 long swpd = (long)swapper_pg_dir; 894 int single_insn_swpd; 895 int did_vmalloc_branch = 0; 896 897 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); 898 899 uasm_l_vmalloc(l, *p); 900 901 if (mode != not_refill && check_for_high_segbits) { 902 if (single_insn_swpd) { 903 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); 904 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 905 did_vmalloc_branch = 1; 906 /* fall through */ 907 } else { 908 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); 909 } 910 } 911 if (!did_vmalloc_branch) { 912 if (single_insn_swpd) { 913 uasm_il_b(p, r, label_vmalloc_done); 914 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 915 } else { 916 UASM_i_LA_mostly(p, ptr, swpd); 917 uasm_il_b(p, r, label_vmalloc_done); 918 if (uasm_in_compat_space_p(swpd)) 919 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); 920 else 921 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); 922 } 923 } 924 if (mode != not_refill && check_for_high_segbits) { 925 uasm_l_large_segbits_fault(l, *p); 926 /* 927 * We get here if we are an xsseg address, or if we are 928 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. 929 * 930 * Ignoring xsseg (assume disabled so would generate 931 * (address errors?), the only remaining possibility 932 * is the upper xuseg addresses. On processors with 933 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these 934 * addresses would have taken an address error. We try 935 * to mimic that here by taking a load/istream page 936 * fault. 937 */ 938 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 939 uasm_i_sync(p, 0); 940 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); 941 uasm_i_jr(p, ptr); 942 943 if (mode == refill_scratch) { 944 if (scratch_reg >= 0) { 945 uasm_i_ehb(p); 946 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 947 } else { 948 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 949 } 950 } else { 951 uasm_i_nop(p); 952 } 953 } 954 } 955 956 #else /* !CONFIG_64BIT */ 957 958 /* 959 * TMP and PTR are scratch. 960 * TMP will be clobbered, PTR will hold the pgd entry. 961 */ 962 void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 963 { 964 if (pgd_reg != -1) { 965 /* pgd is in pgd_reg */ 966 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); 967 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 968 } else { 969 long pgdc = (long)pgd_current; 970 971 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 972 #ifdef CONFIG_SMP 973 uasm_i_mfc0(p, ptr, SMP_CPUID_REG); 974 UASM_i_LA_mostly(p, tmp, pgdc); 975 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 976 uasm_i_addu(p, ptr, tmp, ptr); 977 #else 978 UASM_i_LA_mostly(p, ptr, pgdc); 979 #endif 980 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 981 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 982 } 983 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 984 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); 985 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 986 } 987 EXPORT_SYMBOL_GPL(build_get_pgde32); 988 989 #endif /* !CONFIG_64BIT */ 990 991 static void build_adjust_context(u32 **p, unsigned int ctx) 992 { 993 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 994 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 995 996 switch (current_cpu_type()) { 997 case CPU_VR41XX: 998 case CPU_VR4111: 999 case CPU_VR4121: 1000 case CPU_VR4122: 1001 case CPU_VR4131: 1002 case CPU_VR4181: 1003 case CPU_VR4181A: 1004 case CPU_VR4133: 1005 shift += 2; 1006 break; 1007 1008 default: 1009 break; 1010 } 1011 1012 if (shift) 1013 UASM_i_SRL(p, ctx, ctx, shift); 1014 uasm_i_andi(p, ctx, ctx, mask); 1015 } 1016 1017 void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1018 { 1019 /* 1020 * Bug workaround for the Nevada. It seems as if under certain 1021 * circumstances the move from cp0_context might produce a 1022 * bogus result when the mfc0 instruction and its consumer are 1023 * in a different cacheline or a load instruction, probably any 1024 * memory reference, is between them. 1025 */ 1026 switch (current_cpu_type()) { 1027 case CPU_NEVADA: 1028 UASM_i_LW(p, ptr, 0, ptr); 1029 GET_CONTEXT(p, tmp); /* get context reg */ 1030 break; 1031 1032 default: 1033 GET_CONTEXT(p, tmp); /* get context reg */ 1034 UASM_i_LW(p, ptr, 0, ptr); 1035 break; 1036 } 1037 1038 build_adjust_context(p, tmp); 1039 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1040 } 1041 EXPORT_SYMBOL_GPL(build_get_ptep); 1042 1043 void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) 1044 { 1045 int pte_off_even = 0; 1046 int pte_off_odd = sizeof(pte_t); 1047 1048 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT) 1049 /* The low 32 bits of EntryLo is stored in pte_high */ 1050 pte_off_even += offsetof(pte_t, pte_high); 1051 pte_off_odd += offsetof(pte_t, pte_high); 1052 #endif 1053 1054 if (IS_ENABLED(CONFIG_XPA)) { 1055 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */ 1056 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1057 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); 1058 1059 if (cpu_has_xpa && !mips_xpa_disabled) { 1060 uasm_i_lw(p, tmp, 0, ptep); 1061 uasm_i_ext(p, tmp, tmp, 0, 24); 1062 uasm_i_mthc0(p, tmp, C0_ENTRYLO0); 1063 } 1064 1065 uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */ 1066 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1067 UASM_i_MTC0(p, tmp, C0_ENTRYLO1); 1068 1069 if (cpu_has_xpa && !mips_xpa_disabled) { 1070 uasm_i_lw(p, tmp, sizeof(pte_t), ptep); 1071 uasm_i_ext(p, tmp, tmp, 0, 24); 1072 uasm_i_mthc0(p, tmp, C0_ENTRYLO1); 1073 } 1074 return; 1075 } 1076 1077 UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */ 1078 UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */ 1079 if (r45k_bvahwbug()) 1080 build_tlb_probe_entry(p); 1081 build_convert_pte_to_entrylo(p, tmp); 1082 if (r4k_250MHZhwbug()) 1083 UASM_i_MTC0(p, 0, C0_ENTRYLO0); 1084 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ 1085 build_convert_pte_to_entrylo(p, ptep); 1086 if (r45k_bvahwbug()) 1087 uasm_i_mfc0(p, tmp, C0_INDEX); 1088 if (r4k_250MHZhwbug()) 1089 UASM_i_MTC0(p, 0, C0_ENTRYLO1); 1090 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ 1091 } 1092 EXPORT_SYMBOL_GPL(build_update_entries); 1093 1094 struct mips_huge_tlb_info { 1095 int huge_pte; 1096 int restore_scratch; 1097 bool need_reload_pte; 1098 }; 1099 1100 static struct mips_huge_tlb_info 1101 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, 1102 struct uasm_reloc **r, unsigned int tmp, 1103 unsigned int ptr, int c0_scratch_reg) 1104 { 1105 struct mips_huge_tlb_info rv; 1106 unsigned int even, odd; 1107 int vmalloc_branch_delay_filled = 0; 1108 const int scratch = 1; /* Our extra working register */ 1109 1110 rv.huge_pte = scratch; 1111 rv.restore_scratch = 0; 1112 rv.need_reload_pte = false; 1113 1114 if (check_for_high_segbits) { 1115 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1116 1117 if (pgd_reg != -1) 1118 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1119 else 1120 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1121 1122 if (c0_scratch_reg >= 0) 1123 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1124 else 1125 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1126 1127 uasm_i_dsrl_safe(p, scratch, tmp, 1128 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1129 uasm_il_bnez(p, r, scratch, label_vmalloc); 1130 1131 if (pgd_reg == -1) { 1132 vmalloc_branch_delay_filled = 1; 1133 /* Clear lower 23 bits of context. */ 1134 uasm_i_dins(p, ptr, 0, 0, 23); 1135 } 1136 } else { 1137 if (pgd_reg != -1) 1138 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1139 else 1140 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1141 1142 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1143 1144 if (c0_scratch_reg >= 0) 1145 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1146 else 1147 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1148 1149 if (pgd_reg == -1) 1150 /* Clear lower 23 bits of context. */ 1151 uasm_i_dins(p, ptr, 0, 0, 23); 1152 1153 uasm_il_bltz(p, r, tmp, label_vmalloc); 1154 } 1155 1156 if (pgd_reg == -1) { 1157 vmalloc_branch_delay_filled = 1; 1158 /* 1 0 1 0 1 << 6 xkphys cached */ 1159 uasm_i_ori(p, ptr, ptr, 0x540); 1160 uasm_i_drotr(p, ptr, ptr, 11); 1161 } 1162 1163 #ifdef __PAGETABLE_PMD_FOLDED 1164 #define LOC_PTEP scratch 1165 #else 1166 #define LOC_PTEP ptr 1167 #endif 1168 1169 if (!vmalloc_branch_delay_filled) 1170 /* get pgd offset in bytes */ 1171 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1172 1173 uasm_l_vmalloc_done(l, *p); 1174 1175 /* 1176 * tmp ptr 1177 * fall-through case = badvaddr *pgd_current 1178 * vmalloc case = badvaddr swapper_pg_dir 1179 */ 1180 1181 if (vmalloc_branch_delay_filled) 1182 /* get pgd offset in bytes */ 1183 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1184 1185 #ifdef __PAGETABLE_PMD_FOLDED 1186 GET_CONTEXT(p, tmp); /* get context reg */ 1187 #endif 1188 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); 1189 1190 if (use_lwx_insns()) { 1191 UASM_i_LWX(p, LOC_PTEP, scratch, ptr); 1192 } else { 1193 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ 1194 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ 1195 } 1196 1197 #ifndef __PAGETABLE_PUD_FOLDED 1198 /* get pud offset in bytes */ 1199 uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3); 1200 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3); 1201 1202 if (use_lwx_insns()) { 1203 UASM_i_LWX(p, ptr, scratch, ptr); 1204 } else { 1205 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1206 UASM_i_LW(p, ptr, 0, ptr); 1207 } 1208 /* ptr contains a pointer to PMD entry */ 1209 /* tmp contains the address */ 1210 #endif 1211 1212 #ifndef __PAGETABLE_PMD_FOLDED 1213 /* get pmd offset in bytes */ 1214 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); 1215 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); 1216 GET_CONTEXT(p, tmp); /* get context reg */ 1217 1218 if (use_lwx_insns()) { 1219 UASM_i_LWX(p, scratch, scratch, ptr); 1220 } else { 1221 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1222 UASM_i_LW(p, scratch, 0, ptr); 1223 } 1224 #endif 1225 /* Adjust the context during the load latency. */ 1226 build_adjust_context(p, tmp); 1227 1228 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1229 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); 1230 /* 1231 * The in the LWX case we don't want to do the load in the 1232 * delay slot. It cannot issue in the same cycle and may be 1233 * speculative and unneeded. 1234 */ 1235 if (use_lwx_insns()) 1236 uasm_i_nop(p); 1237 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 1238 1239 1240 /* build_update_entries */ 1241 if (use_lwx_insns()) { 1242 even = ptr; 1243 odd = tmp; 1244 UASM_i_LWX(p, even, scratch, tmp); 1245 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); 1246 UASM_i_LWX(p, odd, scratch, tmp); 1247 } else { 1248 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ 1249 even = tmp; 1250 odd = ptr; 1251 UASM_i_LW(p, even, 0, ptr); /* get even pte */ 1252 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ 1253 } 1254 if (cpu_has_rixi) { 1255 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); 1256 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1257 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1258 } else { 1259 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); 1260 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1261 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1262 } 1263 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ 1264 1265 if (c0_scratch_reg >= 0) { 1266 uasm_i_ehb(p); 1267 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1268 build_tlb_write_entry(p, l, r, tlb_random); 1269 uasm_l_leave(l, *p); 1270 rv.restore_scratch = 1; 1271 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { 1272 build_tlb_write_entry(p, l, r, tlb_random); 1273 uasm_l_leave(l, *p); 1274 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1275 } else { 1276 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1277 build_tlb_write_entry(p, l, r, tlb_random); 1278 uasm_l_leave(l, *p); 1279 rv.restore_scratch = 1; 1280 } 1281 1282 uasm_i_eret(p); /* return from trap */ 1283 1284 return rv; 1285 } 1286 1287 /* 1288 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception 1289 * because EXL == 0. If we wrap, we can also use the 32 instruction 1290 * slots before the XTLB refill exception handler which belong to the 1291 * unused TLB refill exception. 1292 */ 1293 #define MIPS64_REFILL_INSNS 32 1294 1295 static void build_r4000_tlb_refill_handler(void) 1296 { 1297 u32 *p = tlb_handler; 1298 struct uasm_label *l = labels; 1299 struct uasm_reloc *r = relocs; 1300 u32 *f; 1301 unsigned int final_len; 1302 struct mips_huge_tlb_info htlb_info __maybe_unused; 1303 enum vmalloc64_mode vmalloc_mode __maybe_unused; 1304 1305 memset(tlb_handler, 0, sizeof(tlb_handler)); 1306 memset(labels, 0, sizeof(labels)); 1307 memset(relocs, 0, sizeof(relocs)); 1308 memset(final_handler, 0, sizeof(final_handler)); 1309 1310 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { 1311 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, 1312 scratch_reg); 1313 vmalloc_mode = refill_scratch; 1314 } else { 1315 htlb_info.huge_pte = K0; 1316 htlb_info.restore_scratch = 0; 1317 htlb_info.need_reload_pte = true; 1318 vmalloc_mode = refill_noscratch; 1319 /* 1320 * create the plain linear handler 1321 */ 1322 if (bcm1250_m3_war()) { 1323 unsigned int segbits = 44; 1324 1325 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1326 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 1327 uasm_i_xor(&p, K0, K0, K1); 1328 uasm_i_dsrl_safe(&p, K1, K0, 62); 1329 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 1330 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 1331 uasm_i_or(&p, K0, K0, K1); 1332 uasm_il_bnez(&p, &r, K0, label_leave); 1333 /* No need for uasm_i_nop */ 1334 } 1335 1336 #ifdef CONFIG_64BIT 1337 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1338 #else 1339 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1340 #endif 1341 1342 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1343 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); 1344 #endif 1345 1346 build_get_ptep(&p, K0, K1); 1347 build_update_entries(&p, K0, K1); 1348 build_tlb_write_entry(&p, &l, &r, tlb_random); 1349 uasm_l_leave(&l, p); 1350 uasm_i_eret(&p); /* return from trap */ 1351 } 1352 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1353 uasm_l_tlb_huge_update(&l, p); 1354 if (htlb_info.need_reload_pte) 1355 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1); 1356 build_huge_update_entries(&p, htlb_info.huge_pte, K1); 1357 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, 1358 htlb_info.restore_scratch); 1359 #endif 1360 1361 #ifdef CONFIG_64BIT 1362 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); 1363 #endif 1364 1365 /* 1366 * Overflow check: For the 64bit handler, we need at least one 1367 * free instruction slot for the wrap-around branch. In worst 1368 * case, if the intended insertion point is a delay slot, we 1369 * need three, with the second nop'ed and the third being 1370 * unused. 1371 */ 1372 switch (boot_cpu_type()) { 1373 default: 1374 if (sizeof(long) == 4) { 1375 case CPU_LOONGSON2: 1376 /* Loongson2 ebase is different than r4k, we have more space */ 1377 if ((p - tlb_handler) > 64) 1378 panic("TLB refill handler space exceeded"); 1379 /* 1380 * Now fold the handler in the TLB refill handler space. 1381 */ 1382 f = final_handler; 1383 /* Simplest case, just copy the handler. */ 1384 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1385 final_len = p - tlb_handler; 1386 break; 1387 } else { 1388 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) 1389 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) 1390 && uasm_insn_has_bdelay(relocs, 1391 tlb_handler + MIPS64_REFILL_INSNS - 3))) 1392 panic("TLB refill handler space exceeded"); 1393 /* 1394 * Now fold the handler in the TLB refill handler space. 1395 */ 1396 f = final_handler + MIPS64_REFILL_INSNS; 1397 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { 1398 /* Just copy the handler. */ 1399 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1400 final_len = p - tlb_handler; 1401 } else { 1402 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1403 const enum label_id ls = label_tlb_huge_update; 1404 #else 1405 const enum label_id ls = label_vmalloc; 1406 #endif 1407 u32 *split; 1408 int ov = 0; 1409 int i; 1410 1411 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) 1412 ; 1413 BUG_ON(i == ARRAY_SIZE(labels)); 1414 split = labels[i].addr; 1415 1416 /* 1417 * See if we have overflown one way or the other. 1418 */ 1419 if (split > tlb_handler + MIPS64_REFILL_INSNS || 1420 split < p - MIPS64_REFILL_INSNS) 1421 ov = 1; 1422 1423 if (ov) { 1424 /* 1425 * Split two instructions before the end. One 1426 * for the branch and one for the instruction 1427 * in the delay slot. 1428 */ 1429 split = tlb_handler + MIPS64_REFILL_INSNS - 2; 1430 1431 /* 1432 * If the branch would fall in a delay slot, 1433 * we must back up an additional instruction 1434 * so that it is no longer in a delay slot. 1435 */ 1436 if (uasm_insn_has_bdelay(relocs, split - 1)) 1437 split--; 1438 } 1439 /* Copy first part of the handler. */ 1440 uasm_copy_handler(relocs, labels, tlb_handler, split, f); 1441 f += split - tlb_handler; 1442 1443 if (ov) { 1444 /* Insert branch. */ 1445 uasm_l_split(&l, final_handler); 1446 uasm_il_b(&f, &r, label_split); 1447 if (uasm_insn_has_bdelay(relocs, split)) 1448 uasm_i_nop(&f); 1449 else { 1450 uasm_copy_handler(relocs, labels, 1451 split, split + 1, f); 1452 uasm_move_labels(labels, f, f + 1, -1); 1453 f++; 1454 split++; 1455 } 1456 } 1457 1458 /* Copy the rest of the handler. */ 1459 uasm_copy_handler(relocs, labels, split, p, final_handler); 1460 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + 1461 (p - split); 1462 } 1463 } 1464 break; 1465 } 1466 1467 uasm_resolve_relocs(relocs, labels); 1468 pr_debug("Wrote TLB refill handler (%u instructions).\n", 1469 final_len); 1470 1471 memcpy((void *)ebase, final_handler, 0x100); 1472 local_flush_icache_range(ebase, ebase + 0x100); 1473 dump_handler("r4000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x100)); 1474 } 1475 1476 static void setup_pw(void) 1477 { 1478 unsigned long pgd_i, pgd_w; 1479 #ifndef __PAGETABLE_PMD_FOLDED 1480 unsigned long pmd_i, pmd_w; 1481 #endif 1482 unsigned long pt_i, pt_w; 1483 unsigned long pte_i, pte_w; 1484 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1485 unsigned long psn; 1486 1487 psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */ 1488 #endif 1489 pgd_i = PGDIR_SHIFT; /* 1st level PGD */ 1490 #ifndef __PAGETABLE_PMD_FOLDED 1491 pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER; 1492 1493 pmd_i = PMD_SHIFT; /* 2nd level PMD */ 1494 pmd_w = PMD_SHIFT - PAGE_SHIFT; 1495 #else 1496 pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER; 1497 #endif 1498 1499 pt_i = PAGE_SHIFT; /* 3rd level PTE */ 1500 pt_w = PAGE_SHIFT - 3; 1501 1502 pte_i = ilog2(_PAGE_GLOBAL); 1503 pte_w = 0; 1504 1505 #ifndef __PAGETABLE_PMD_FOLDED 1506 write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i); 1507 write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w); 1508 #else 1509 write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i); 1510 write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w); 1511 #endif 1512 1513 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1514 write_c0_pwctl(1 << 6 | psn); 1515 #endif 1516 write_c0_kpgd((long)swapper_pg_dir); 1517 kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */ 1518 } 1519 1520 static void build_loongson3_tlb_refill_handler(void) 1521 { 1522 u32 *p = tlb_handler; 1523 struct uasm_label *l = labels; 1524 struct uasm_reloc *r = relocs; 1525 1526 memset(labels, 0, sizeof(labels)); 1527 memset(relocs, 0, sizeof(relocs)); 1528 memset(tlb_handler, 0, sizeof(tlb_handler)); 1529 1530 if (check_for_high_segbits) { 1531 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1532 uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1533 uasm_il_beqz(&p, &r, K1, label_vmalloc); 1534 uasm_i_nop(&p); 1535 1536 uasm_il_bgez(&p, &r, K0, label_large_segbits_fault); 1537 uasm_i_nop(&p); 1538 uasm_l_vmalloc(&l, p); 1539 } 1540 1541 uasm_i_dmfc0(&p, K1, C0_PGD); 1542 1543 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */ 1544 #ifndef __PAGETABLE_PMD_FOLDED 1545 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */ 1546 #endif 1547 uasm_i_ldpte(&p, K1, 0); /* even */ 1548 uasm_i_ldpte(&p, K1, 1); /* odd */ 1549 uasm_i_tlbwr(&p); 1550 1551 /* restore page mask */ 1552 if (PM_DEFAULT_MASK >> 16) { 1553 uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16); 1554 uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff); 1555 uasm_i_mtc0(&p, K0, C0_PAGEMASK); 1556 } else if (PM_DEFAULT_MASK) { 1557 uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK); 1558 uasm_i_mtc0(&p, K0, C0_PAGEMASK); 1559 } else { 1560 uasm_i_mtc0(&p, 0, C0_PAGEMASK); 1561 } 1562 1563 uasm_i_eret(&p); 1564 1565 if (check_for_high_segbits) { 1566 uasm_l_large_segbits_fault(&l, p); 1567 UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0); 1568 uasm_i_jr(&p, K1); 1569 uasm_i_nop(&p); 1570 } 1571 1572 uasm_resolve_relocs(relocs, labels); 1573 memcpy((void *)(ebase + 0x80), tlb_handler, 0x80); 1574 local_flush_icache_range(ebase + 0x80, ebase + 0x100); 1575 dump_handler("loongson3_tlb_refill", 1576 (u32 *)(ebase + 0x80), (u32 *)(ebase + 0x100)); 1577 } 1578 1579 static void build_setup_pgd(void) 1580 { 1581 const int a0 = 4; 1582 const int __maybe_unused a1 = 5; 1583 const int __maybe_unused a2 = 6; 1584 u32 *p = (u32 *)msk_isa16_mode((ulong)tlbmiss_handler_setup_pgd); 1585 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1586 long pgdc = (long)pgd_current; 1587 #endif 1588 1589 memset(p, 0, tlbmiss_handler_setup_pgd_end - (char *)p); 1590 memset(labels, 0, sizeof(labels)); 1591 memset(relocs, 0, sizeof(relocs)); 1592 pgd_reg = allocate_kscratch(); 1593 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 1594 if (pgd_reg == -1) { 1595 struct uasm_label *l = labels; 1596 struct uasm_reloc *r = relocs; 1597 1598 /* PGD << 11 in c0_Context */ 1599 /* 1600 * If it is a ckseg0 address, convert to a physical 1601 * address. Shifting right by 29 and adding 4 will 1602 * result in zero for these addresses. 1603 * 1604 */ 1605 UASM_i_SRA(&p, a1, a0, 29); 1606 UASM_i_ADDIU(&p, a1, a1, 4); 1607 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); 1608 uasm_i_nop(&p); 1609 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); 1610 uasm_l_tlbl_goaround1(&l, p); 1611 UASM_i_SLL(&p, a0, a0, 11); 1612 UASM_i_MTC0(&p, a0, C0_CONTEXT); 1613 uasm_i_jr(&p, 31); 1614 uasm_i_ehb(&p); 1615 } else { 1616 /* PGD in c0_KScratch */ 1617 if (cpu_has_ldpte) 1618 UASM_i_MTC0(&p, a0, C0_PWBASE); 1619 else 1620 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1621 uasm_i_jr(&p, 31); 1622 uasm_i_ehb(&p); 1623 } 1624 #else 1625 #ifdef CONFIG_SMP 1626 /* Save PGD to pgd_current[smp_processor_id()] */ 1627 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); 1628 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); 1629 UASM_i_LA_mostly(&p, a2, pgdc); 1630 UASM_i_ADDU(&p, a2, a2, a1); 1631 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1632 #else 1633 UASM_i_LA_mostly(&p, a2, pgdc); 1634 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1635 #endif /* SMP */ 1636 1637 /* if pgd_reg is allocated, save PGD also to scratch register */ 1638 if (pgd_reg != -1) { 1639 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1640 uasm_i_jr(&p, 31); 1641 uasm_i_ehb(&p); 1642 } else { 1643 uasm_i_jr(&p, 31); 1644 uasm_i_nop(&p); 1645 } 1646 #endif 1647 if (p >= (u32 *)tlbmiss_handler_setup_pgd_end) 1648 panic("tlbmiss_handler_setup_pgd space exceeded"); 1649 1650 uasm_resolve_relocs(relocs, labels); 1651 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", 1652 (unsigned int)(p - (u32 *)tlbmiss_handler_setup_pgd)); 1653 1654 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, 1655 tlbmiss_handler_setup_pgd_end); 1656 } 1657 1658 static void 1659 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) 1660 { 1661 #ifdef CONFIG_SMP 1662 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 1663 uasm_i_sync(p, 0); 1664 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1665 if (cpu_has_64bits) 1666 uasm_i_lld(p, pte, 0, ptr); 1667 else 1668 # endif 1669 UASM_i_LL(p, pte, 0, ptr); 1670 #else 1671 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1672 if (cpu_has_64bits) 1673 uasm_i_ld(p, pte, 0, ptr); 1674 else 1675 # endif 1676 UASM_i_LW(p, pte, 0, ptr); 1677 #endif 1678 } 1679 1680 static void 1681 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, 1682 unsigned int mode, unsigned int scratch) 1683 { 1684 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1685 unsigned int swmode = mode & ~hwmode; 1686 1687 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) { 1688 uasm_i_lui(p, scratch, swmode >> 16); 1689 uasm_i_or(p, pte, pte, scratch); 1690 BUG_ON(swmode & 0xffff); 1691 } else { 1692 uasm_i_ori(p, pte, pte, mode); 1693 } 1694 1695 #ifdef CONFIG_SMP 1696 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1697 if (cpu_has_64bits) 1698 uasm_i_scd(p, pte, 0, ptr); 1699 else 1700 # endif 1701 UASM_i_SC(p, pte, 0, ptr); 1702 1703 if (r10000_llsc_war()) 1704 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); 1705 else 1706 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1707 1708 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1709 if (!cpu_has_64bits) { 1710 /* no uasm_i_nop needed */ 1711 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1712 uasm_i_ori(p, pte, pte, hwmode); 1713 BUG_ON(hwmode & ~0xffff); 1714 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1715 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1716 /* no uasm_i_nop needed */ 1717 uasm_i_lw(p, pte, 0, ptr); 1718 } else 1719 uasm_i_nop(p); 1720 # else 1721 uasm_i_nop(p); 1722 # endif 1723 #else 1724 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1725 if (cpu_has_64bits) 1726 uasm_i_sd(p, pte, 0, ptr); 1727 else 1728 # endif 1729 UASM_i_SW(p, pte, 0, ptr); 1730 1731 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1732 if (!cpu_has_64bits) { 1733 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1734 uasm_i_ori(p, pte, pte, hwmode); 1735 BUG_ON(hwmode & ~0xffff); 1736 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1737 uasm_i_lw(p, pte, 0, ptr); 1738 } 1739 # endif 1740 #endif 1741 } 1742 1743 /* 1744 * Check if PTE is present, if not then jump to LABEL. PTR points to 1745 * the page table where this PTE is located, PTE will be re-loaded 1746 * with it's original value. 1747 */ 1748 static void 1749 build_pte_present(u32 **p, struct uasm_reloc **r, 1750 int pte, int ptr, int scratch, enum label_id lid) 1751 { 1752 int t = scratch >= 0 ? scratch : pte; 1753 int cur = pte; 1754 1755 if (cpu_has_rixi) { 1756 if (use_bbit_insns()) { 1757 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); 1758 uasm_i_nop(p); 1759 } else { 1760 if (_PAGE_PRESENT_SHIFT) { 1761 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1762 cur = t; 1763 } 1764 uasm_i_andi(p, t, cur, 1); 1765 uasm_il_beqz(p, r, t, lid); 1766 if (pte == t) 1767 /* You lose the SMP race :-(*/ 1768 iPTE_LW(p, pte, ptr); 1769 } 1770 } else { 1771 if (_PAGE_PRESENT_SHIFT) { 1772 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1773 cur = t; 1774 } 1775 uasm_i_andi(p, t, cur, 1776 (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT); 1777 uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT); 1778 uasm_il_bnez(p, r, t, lid); 1779 if (pte == t) 1780 /* You lose the SMP race :-(*/ 1781 iPTE_LW(p, pte, ptr); 1782 } 1783 } 1784 1785 /* Make PTE valid, store result in PTR. */ 1786 static void 1787 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, 1788 unsigned int ptr, unsigned int scratch) 1789 { 1790 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 1791 1792 iPTE_SW(p, r, pte, ptr, mode, scratch); 1793 } 1794 1795 /* 1796 * Check if PTE can be written to, if not branch to LABEL. Regardless 1797 * restore PTE with value from PTR when done. 1798 */ 1799 static void 1800 build_pte_writable(u32 **p, struct uasm_reloc **r, 1801 unsigned int pte, unsigned int ptr, int scratch, 1802 enum label_id lid) 1803 { 1804 int t = scratch >= 0 ? scratch : pte; 1805 int cur = pte; 1806 1807 if (_PAGE_PRESENT_SHIFT) { 1808 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1809 cur = t; 1810 } 1811 uasm_i_andi(p, t, cur, 1812 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1813 uasm_i_xori(p, t, t, 1814 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1815 uasm_il_bnez(p, r, t, lid); 1816 if (pte == t) 1817 /* You lose the SMP race :-(*/ 1818 iPTE_LW(p, pte, ptr); 1819 else 1820 uasm_i_nop(p); 1821 } 1822 1823 /* Make PTE writable, update software status bits as well, then store 1824 * at PTR. 1825 */ 1826 static void 1827 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, 1828 unsigned int ptr, unsigned int scratch) 1829 { 1830 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 1831 | _PAGE_DIRTY); 1832 1833 iPTE_SW(p, r, pte, ptr, mode, scratch); 1834 } 1835 1836 /* 1837 * Check if PTE can be modified, if not branch to LABEL. Regardless 1838 * restore PTE with value from PTR when done. 1839 */ 1840 static void 1841 build_pte_modifiable(u32 **p, struct uasm_reloc **r, 1842 unsigned int pte, unsigned int ptr, int scratch, 1843 enum label_id lid) 1844 { 1845 if (use_bbit_insns()) { 1846 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); 1847 uasm_i_nop(p); 1848 } else { 1849 int t = scratch >= 0 ? scratch : pte; 1850 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT); 1851 uasm_i_andi(p, t, t, 1); 1852 uasm_il_beqz(p, r, t, lid); 1853 if (pte == t) 1854 /* You lose the SMP race :-(*/ 1855 iPTE_LW(p, pte, ptr); 1856 } 1857 } 1858 1859 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1860 1861 1862 /* 1863 * R3000 style TLB load/store/modify handlers. 1864 */ 1865 1866 /* 1867 * This places the pte into ENTRYLO0 and writes it with tlbwi. 1868 * Then it returns. 1869 */ 1870 static void 1871 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 1872 { 1873 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1874 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 1875 uasm_i_tlbwi(p); 1876 uasm_i_jr(p, tmp); 1877 uasm_i_rfe(p); /* branch delay */ 1878 } 1879 1880 /* 1881 * This places the pte into ENTRYLO0 and writes it with tlbwi 1882 * or tlbwr as appropriate. This is because the index register 1883 * may have the probe fail bit set as a result of a trap on a 1884 * kseg2 access, i.e. without refill. Then it returns. 1885 */ 1886 static void 1887 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, 1888 struct uasm_reloc **r, unsigned int pte, 1889 unsigned int tmp) 1890 { 1891 uasm_i_mfc0(p, tmp, C0_INDEX); 1892 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1893 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 1894 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ 1895 uasm_i_tlbwi(p); /* cp0 delay */ 1896 uasm_i_jr(p, tmp); 1897 uasm_i_rfe(p); /* branch delay */ 1898 uasm_l_r3000_write_probe_fail(l, *p); 1899 uasm_i_tlbwr(p); /* cp0 delay */ 1900 uasm_i_jr(p, tmp); 1901 uasm_i_rfe(p); /* branch delay */ 1902 } 1903 1904 static void 1905 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1906 unsigned int ptr) 1907 { 1908 long pgdc = (long)pgd_current; 1909 1910 uasm_i_mfc0(p, pte, C0_BADVADDR); 1911 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ 1912 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 1913 uasm_i_srl(p, pte, pte, 22); /* load delay */ 1914 uasm_i_sll(p, pte, pte, 2); 1915 uasm_i_addu(p, ptr, ptr, pte); 1916 uasm_i_mfc0(p, pte, C0_CONTEXT); 1917 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ 1918 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ 1919 uasm_i_addu(p, ptr, ptr, pte); 1920 uasm_i_lw(p, pte, 0, ptr); 1921 uasm_i_tlbp(p); /* load delay */ 1922 } 1923 1924 static void build_r3000_tlb_load_handler(void) 1925 { 1926 u32 *p = (u32 *)handle_tlbl; 1927 struct uasm_label *l = labels; 1928 struct uasm_reloc *r = relocs; 1929 1930 memset(p, 0, handle_tlbl_end - (char *)p); 1931 memset(labels, 0, sizeof(labels)); 1932 memset(relocs, 0, sizeof(relocs)); 1933 1934 build_r3000_tlbchange_handler_head(&p, K0, K1); 1935 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); 1936 uasm_i_nop(&p); /* load delay */ 1937 build_make_valid(&p, &r, K0, K1, -1); 1938 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1939 1940 uasm_l_nopage_tlbl(&l, p); 1941 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1942 uasm_i_nop(&p); 1943 1944 if (p >= (u32 *)handle_tlbl_end) 1945 panic("TLB load handler fastpath space exceeded"); 1946 1947 uasm_resolve_relocs(relocs, labels); 1948 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1949 (unsigned int)(p - (u32 *)handle_tlbl)); 1950 1951 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_end); 1952 } 1953 1954 static void build_r3000_tlb_store_handler(void) 1955 { 1956 u32 *p = (u32 *)handle_tlbs; 1957 struct uasm_label *l = labels; 1958 struct uasm_reloc *r = relocs; 1959 1960 memset(p, 0, handle_tlbs_end - (char *)p); 1961 memset(labels, 0, sizeof(labels)); 1962 memset(relocs, 0, sizeof(relocs)); 1963 1964 build_r3000_tlbchange_handler_head(&p, K0, K1); 1965 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); 1966 uasm_i_nop(&p); /* load delay */ 1967 build_make_write(&p, &r, K0, K1, -1); 1968 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1969 1970 uasm_l_nopage_tlbs(&l, p); 1971 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1972 uasm_i_nop(&p); 1973 1974 if (p >= (u32 *)handle_tlbs_end) 1975 panic("TLB store handler fastpath space exceeded"); 1976 1977 uasm_resolve_relocs(relocs, labels); 1978 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1979 (unsigned int)(p - (u32 *)handle_tlbs)); 1980 1981 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_end); 1982 } 1983 1984 static void build_r3000_tlb_modify_handler(void) 1985 { 1986 u32 *p = (u32 *)handle_tlbm; 1987 struct uasm_label *l = labels; 1988 struct uasm_reloc *r = relocs; 1989 1990 memset(p, 0, handle_tlbm_end - (char *)p); 1991 memset(labels, 0, sizeof(labels)); 1992 memset(relocs, 0, sizeof(relocs)); 1993 1994 build_r3000_tlbchange_handler_head(&p, K0, K1); 1995 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); 1996 uasm_i_nop(&p); /* load delay */ 1997 build_make_write(&p, &r, K0, K1, -1); 1998 build_r3000_pte_reload_tlbwi(&p, K0, K1); 1999 2000 uasm_l_nopage_tlbm(&l, p); 2001 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2002 uasm_i_nop(&p); 2003 2004 if (p >= (u32 *)handle_tlbm_end) 2005 panic("TLB modify handler fastpath space exceeded"); 2006 2007 uasm_resolve_relocs(relocs, labels); 2008 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2009 (unsigned int)(p - (u32 *)handle_tlbm)); 2010 2011 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_end); 2012 } 2013 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 2014 2015 static bool cpu_has_tlbex_tlbp_race(void) 2016 { 2017 /* 2018 * When a Hardware Table Walker is running it can replace TLB entries 2019 * at any time, leading to a race between it & the CPU. 2020 */ 2021 if (cpu_has_htw) 2022 return true; 2023 2024 /* 2025 * If the CPU shares FTLB RAM with its siblings then our entry may be 2026 * replaced at any time by a sibling performing a write to the FTLB. 2027 */ 2028 if (cpu_has_shared_ftlb_ram) 2029 return true; 2030 2031 /* In all other cases there ought to be no race condition to handle */ 2032 return false; 2033 } 2034 2035 /* 2036 * R4000 style TLB load/store/modify handlers. 2037 */ 2038 static struct work_registers 2039 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, 2040 struct uasm_reloc **r) 2041 { 2042 struct work_registers wr = build_get_work_registers(p); 2043 2044 #ifdef CONFIG_64BIT 2045 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ 2046 #else 2047 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ 2048 #endif 2049 2050 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2051 /* 2052 * For huge tlb entries, pmd doesn't contain an address but 2053 * instead contains the tlb pte. Check the PAGE_HUGE bit and 2054 * see if we need to jump to huge tlb processing. 2055 */ 2056 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); 2057 #endif 2058 2059 UASM_i_MFC0(p, wr.r1, C0_BADVADDR); 2060 UASM_i_LW(p, wr.r2, 0, wr.r2); 2061 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 2062 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 2063 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); 2064 2065 #ifdef CONFIG_SMP 2066 uasm_l_smp_pgtable_change(l, *p); 2067 #endif 2068 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ 2069 if (!m4kc_tlbp_war()) { 2070 build_tlb_probe_entry(p); 2071 if (cpu_has_tlbex_tlbp_race()) { 2072 /* race condition happens, leaving */ 2073 uasm_i_ehb(p); 2074 uasm_i_mfc0(p, wr.r3, C0_INDEX); 2075 uasm_il_bltz(p, r, wr.r3, label_leave); 2076 uasm_i_nop(p); 2077 } 2078 } 2079 return wr; 2080 } 2081 2082 static void 2083 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, 2084 struct uasm_reloc **r, unsigned int tmp, 2085 unsigned int ptr) 2086 { 2087 uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); 2088 uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); 2089 build_update_entries(p, tmp, ptr); 2090 build_tlb_write_entry(p, l, r, tlb_indexed); 2091 uasm_l_leave(l, *p); 2092 build_restore_work_registers(p); 2093 uasm_i_eret(p); /* return from trap */ 2094 2095 #ifdef CONFIG_64BIT 2096 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); 2097 #endif 2098 } 2099 2100 static void build_r4000_tlb_load_handler(void) 2101 { 2102 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl); 2103 struct uasm_label *l = labels; 2104 struct uasm_reloc *r = relocs; 2105 struct work_registers wr; 2106 2107 memset(p, 0, handle_tlbl_end - (char *)p); 2108 memset(labels, 0, sizeof(labels)); 2109 memset(relocs, 0, sizeof(relocs)); 2110 2111 if (bcm1250_m3_war()) { 2112 unsigned int segbits = 44; 2113 2114 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 2115 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 2116 uasm_i_xor(&p, K0, K0, K1); 2117 uasm_i_dsrl_safe(&p, K1, K0, 62); 2118 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 2119 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 2120 uasm_i_or(&p, K0, K0, K1); 2121 uasm_il_bnez(&p, &r, K0, label_leave); 2122 /* No need for uasm_i_nop */ 2123 } 2124 2125 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2126 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2127 if (m4kc_tlbp_war()) 2128 build_tlb_probe_entry(&p); 2129 2130 if (cpu_has_rixi && !cpu_has_rixiex) { 2131 /* 2132 * If the page is not _PAGE_VALID, RI or XI could not 2133 * have triggered it. Skip the expensive test.. 2134 */ 2135 if (use_bbit_insns()) { 2136 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2137 label_tlbl_goaround1); 2138 } else { 2139 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2140 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); 2141 } 2142 uasm_i_nop(&p); 2143 2144 /* 2145 * Warn if something may race with us & replace the TLB entry 2146 * before we read it here. Everything with such races should 2147 * also have dedicated RiXi exception handlers, so this 2148 * shouldn't be hit. 2149 */ 2150 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path"); 2151 2152 uasm_i_tlbr(&p); 2153 2154 switch (current_cpu_type()) { 2155 default: 2156 if (cpu_has_mips_r2_exec_hazard) { 2157 uasm_i_ehb(&p); 2158 2159 case CPU_CAVIUM_OCTEON: 2160 case CPU_CAVIUM_OCTEON_PLUS: 2161 case CPU_CAVIUM_OCTEON2: 2162 break; 2163 } 2164 } 2165 2166 /* Examine entrylo 0 or 1 based on ptr. */ 2167 if (use_bbit_insns()) { 2168 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2169 } else { 2170 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2171 uasm_i_beqz(&p, wr.r3, 8); 2172 } 2173 /* load it in the delay slot*/ 2174 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2175 /* load it if ptr is odd */ 2176 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2177 /* 2178 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2179 * XI must have triggered it. 2180 */ 2181 if (use_bbit_insns()) { 2182 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); 2183 uasm_i_nop(&p); 2184 uasm_l_tlbl_goaround1(&l, p); 2185 } else { 2186 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2187 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); 2188 uasm_i_nop(&p); 2189 } 2190 uasm_l_tlbl_goaround1(&l, p); 2191 } 2192 build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3); 2193 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2194 2195 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2196 /* 2197 * This is the entry point when build_r4000_tlbchange_handler_head 2198 * spots a huge page. 2199 */ 2200 uasm_l_tlb_huge_update(&l, p); 2201 iPTE_LW(&p, wr.r1, wr.r2); 2202 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2203 build_tlb_probe_entry(&p); 2204 2205 if (cpu_has_rixi && !cpu_has_rixiex) { 2206 /* 2207 * If the page is not _PAGE_VALID, RI or XI could not 2208 * have triggered it. Skip the expensive test.. 2209 */ 2210 if (use_bbit_insns()) { 2211 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2212 label_tlbl_goaround2); 2213 } else { 2214 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2215 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2216 } 2217 uasm_i_nop(&p); 2218 2219 /* 2220 * Warn if something may race with us & replace the TLB entry 2221 * before we read it here. Everything with such races should 2222 * also have dedicated RiXi exception handlers, so this 2223 * shouldn't be hit. 2224 */ 2225 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path"); 2226 2227 uasm_i_tlbr(&p); 2228 2229 switch (current_cpu_type()) { 2230 default: 2231 if (cpu_has_mips_r2_exec_hazard) { 2232 uasm_i_ehb(&p); 2233 2234 case CPU_CAVIUM_OCTEON: 2235 case CPU_CAVIUM_OCTEON_PLUS: 2236 case CPU_CAVIUM_OCTEON2: 2237 break; 2238 } 2239 } 2240 2241 /* Examine entrylo 0 or 1 based on ptr. */ 2242 if (use_bbit_insns()) { 2243 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2244 } else { 2245 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2246 uasm_i_beqz(&p, wr.r3, 8); 2247 } 2248 /* load it in the delay slot*/ 2249 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2250 /* load it if ptr is odd */ 2251 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2252 /* 2253 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2254 * XI must have triggered it. 2255 */ 2256 if (use_bbit_insns()) { 2257 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); 2258 } else { 2259 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2260 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2261 } 2262 if (PM_DEFAULT_MASK == 0) 2263 uasm_i_nop(&p); 2264 /* 2265 * We clobbered C0_PAGEMASK, restore it. On the other branch 2266 * it is restored in build_huge_tlb_write_entry. 2267 */ 2268 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); 2269 2270 uasm_l_tlbl_goaround2(&l, p); 2271 } 2272 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); 2273 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); 2274 #endif 2275 2276 uasm_l_nopage_tlbl(&l, p); 2277 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2278 uasm_i_sync(&p, 0); 2279 build_restore_work_registers(&p); 2280 #ifdef CONFIG_CPU_MICROMIPS 2281 if ((unsigned long)tlb_do_page_fault_0 & 1) { 2282 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); 2283 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); 2284 uasm_i_jr(&p, K0); 2285 } else 2286 #endif 2287 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 2288 uasm_i_nop(&p); 2289 2290 if (p >= (u32 *)handle_tlbl_end) 2291 panic("TLB load handler fastpath space exceeded"); 2292 2293 uasm_resolve_relocs(relocs, labels); 2294 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 2295 (unsigned int)(p - (u32 *)handle_tlbl)); 2296 2297 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_end); 2298 } 2299 2300 static void build_r4000_tlb_store_handler(void) 2301 { 2302 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs); 2303 struct uasm_label *l = labels; 2304 struct uasm_reloc *r = relocs; 2305 struct work_registers wr; 2306 2307 memset(p, 0, handle_tlbs_end - (char *)p); 2308 memset(labels, 0, sizeof(labels)); 2309 memset(relocs, 0, sizeof(relocs)); 2310 2311 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2312 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2313 if (m4kc_tlbp_war()) 2314 build_tlb_probe_entry(&p); 2315 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); 2316 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2317 2318 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2319 /* 2320 * This is the entry point when 2321 * build_r4000_tlbchange_handler_head spots a huge page. 2322 */ 2323 uasm_l_tlb_huge_update(&l, p); 2324 iPTE_LW(&p, wr.r1, wr.r2); 2325 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2326 build_tlb_probe_entry(&p); 2327 uasm_i_ori(&p, wr.r1, wr.r1, 2328 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2329 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); 2330 #endif 2331 2332 uasm_l_nopage_tlbs(&l, p); 2333 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2334 uasm_i_sync(&p, 0); 2335 build_restore_work_registers(&p); 2336 #ifdef CONFIG_CPU_MICROMIPS 2337 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2338 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2339 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2340 uasm_i_jr(&p, K0); 2341 } else 2342 #endif 2343 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2344 uasm_i_nop(&p); 2345 2346 if (p >= (u32 *)handle_tlbs_end) 2347 panic("TLB store handler fastpath space exceeded"); 2348 2349 uasm_resolve_relocs(relocs, labels); 2350 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 2351 (unsigned int)(p - (u32 *)handle_tlbs)); 2352 2353 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_end); 2354 } 2355 2356 static void build_r4000_tlb_modify_handler(void) 2357 { 2358 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm); 2359 struct uasm_label *l = labels; 2360 struct uasm_reloc *r = relocs; 2361 struct work_registers wr; 2362 2363 memset(p, 0, handle_tlbm_end - (char *)p); 2364 memset(labels, 0, sizeof(labels)); 2365 memset(relocs, 0, sizeof(relocs)); 2366 2367 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2368 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2369 if (m4kc_tlbp_war()) 2370 build_tlb_probe_entry(&p); 2371 /* Present and writable bits set, set accessed and dirty bits. */ 2372 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); 2373 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2374 2375 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2376 /* 2377 * This is the entry point when 2378 * build_r4000_tlbchange_handler_head spots a huge page. 2379 */ 2380 uasm_l_tlb_huge_update(&l, p); 2381 iPTE_LW(&p, wr.r1, wr.r2); 2382 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2383 build_tlb_probe_entry(&p); 2384 uasm_i_ori(&p, wr.r1, wr.r1, 2385 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2386 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0); 2387 #endif 2388 2389 uasm_l_nopage_tlbm(&l, p); 2390 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2391 uasm_i_sync(&p, 0); 2392 build_restore_work_registers(&p); 2393 #ifdef CONFIG_CPU_MICROMIPS 2394 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2395 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2396 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2397 uasm_i_jr(&p, K0); 2398 } else 2399 #endif 2400 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2401 uasm_i_nop(&p); 2402 2403 if (p >= (u32 *)handle_tlbm_end) 2404 panic("TLB modify handler fastpath space exceeded"); 2405 2406 uasm_resolve_relocs(relocs, labels); 2407 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2408 (unsigned int)(p - (u32 *)handle_tlbm)); 2409 2410 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_end); 2411 } 2412 2413 static void flush_tlb_handlers(void) 2414 { 2415 local_flush_icache_range((unsigned long)handle_tlbl, 2416 (unsigned long)handle_tlbl_end); 2417 local_flush_icache_range((unsigned long)handle_tlbs, 2418 (unsigned long)handle_tlbs_end); 2419 local_flush_icache_range((unsigned long)handle_tlbm, 2420 (unsigned long)handle_tlbm_end); 2421 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, 2422 (unsigned long)tlbmiss_handler_setup_pgd_end); 2423 } 2424 2425 static void print_htw_config(void) 2426 { 2427 unsigned long config; 2428 unsigned int pwctl; 2429 const int field = 2 * sizeof(unsigned long); 2430 2431 config = read_c0_pwfield(); 2432 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n", 2433 field, config, 2434 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT, 2435 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT, 2436 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT, 2437 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT, 2438 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); 2439 2440 config = read_c0_pwsize(); 2441 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", 2442 field, config, 2443 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT, 2444 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, 2445 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, 2446 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, 2447 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT, 2448 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); 2449 2450 pwctl = read_c0_pwctl(); 2451 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", 2452 pwctl, 2453 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, 2454 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT, 2455 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT, 2456 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT, 2457 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, 2458 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, 2459 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); 2460 } 2461 2462 static void config_htw_params(void) 2463 { 2464 unsigned long pwfield, pwsize, ptei; 2465 unsigned int config; 2466 2467 /* 2468 * We are using 2-level page tables, so we only need to 2469 * setup GDW and PTW appropriately. UDW and MDW will remain 0. 2470 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to 2471 * write values less than 0xc in these fields because the entire 2472 * write will be dropped. As a result of which, we must preserve 2473 * the original reset values and overwrite only what we really want. 2474 */ 2475 2476 pwfield = read_c0_pwfield(); 2477 /* re-initialize the GDI field */ 2478 pwfield &= ~MIPS_PWFIELD_GDI_MASK; 2479 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT; 2480 /* re-initialize the PTI field including the even/odd bit */ 2481 pwfield &= ~MIPS_PWFIELD_PTI_MASK; 2482 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT; 2483 if (CONFIG_PGTABLE_LEVELS >= 3) { 2484 pwfield &= ~MIPS_PWFIELD_MDI_MASK; 2485 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT; 2486 } 2487 /* Set the PTEI right shift */ 2488 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT; 2489 pwfield |= ptei; 2490 write_c0_pwfield(pwfield); 2491 /* Check whether the PTEI value is supported */ 2492 back_to_back_c0_hazard(); 2493 pwfield = read_c0_pwfield(); 2494 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT) 2495 != ptei) { 2496 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled", 2497 ptei); 2498 /* 2499 * Drop option to avoid HTW being enabled via another path 2500 * (eg htw_reset()) 2501 */ 2502 current_cpu_data.options &= ~MIPS_CPU_HTW; 2503 return; 2504 } 2505 2506 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; 2507 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; 2508 if (CONFIG_PGTABLE_LEVELS >= 3) 2509 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; 2510 2511 /* Set pointer size to size of directory pointers */ 2512 if (IS_ENABLED(CONFIG_64BIT)) 2513 pwsize |= MIPS_PWSIZE_PS_MASK; 2514 /* PTEs may be multiple pointers long (e.g. with XPA) */ 2515 pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT) 2516 & MIPS_PWSIZE_PTEW_MASK; 2517 2518 write_c0_pwsize(pwsize); 2519 2520 /* Make sure everything is set before we enable the HTW */ 2521 back_to_back_c0_hazard(); 2522 2523 /* 2524 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of 2525 * the pwctl fields. 2526 */ 2527 config = 1 << MIPS_PWCTL_PWEN_SHIFT; 2528 if (IS_ENABLED(CONFIG_64BIT)) 2529 config |= MIPS_PWCTL_XU_MASK; 2530 write_c0_pwctl(config); 2531 pr_info("Hardware Page Table Walker enabled\n"); 2532 2533 print_htw_config(); 2534 } 2535 2536 static void config_xpa_params(void) 2537 { 2538 #ifdef CONFIG_XPA 2539 unsigned int pagegrain; 2540 2541 if (mips_xpa_disabled) { 2542 pr_info("Extended Physical Addressing (XPA) disabled\n"); 2543 return; 2544 } 2545 2546 pagegrain = read_c0_pagegrain(); 2547 write_c0_pagegrain(pagegrain | PG_ELPA); 2548 back_to_back_c0_hazard(); 2549 pagegrain = read_c0_pagegrain(); 2550 2551 if (pagegrain & PG_ELPA) 2552 pr_info("Extended Physical Addressing (XPA) enabled\n"); 2553 else 2554 panic("Extended Physical Addressing (XPA) disabled"); 2555 #endif 2556 } 2557 2558 static void check_pabits(void) 2559 { 2560 unsigned long entry; 2561 unsigned pabits, fillbits; 2562 2563 if (!cpu_has_rixi || !_PAGE_NO_EXEC) { 2564 /* 2565 * We'll only be making use of the fact that we can rotate bits 2566 * into the fill if the CPU supports RIXI, so don't bother 2567 * probing this for CPUs which don't. 2568 */ 2569 return; 2570 } 2571 2572 write_c0_entrylo0(~0ul); 2573 back_to_back_c0_hazard(); 2574 entry = read_c0_entrylo0(); 2575 2576 /* clear all non-PFN bits */ 2577 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1); 2578 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); 2579 2580 /* find a lower bound on PABITS, and upper bound on fill bits */ 2581 pabits = fls_long(entry) + 6; 2582 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0); 2583 2584 /* minus the RI & XI bits */ 2585 fillbits -= min_t(unsigned, fillbits, 2); 2586 2587 if (fillbits >= ilog2(_PAGE_NO_EXEC)) 2588 fill_includes_sw_bits = true; 2589 2590 pr_debug("Entry* registers contain %u fill bits\n", fillbits); 2591 } 2592 2593 void build_tlb_refill_handler(void) 2594 { 2595 /* 2596 * The refill handler is generated per-CPU, multi-node systems 2597 * may have local storage for it. The other handlers are only 2598 * needed once. 2599 */ 2600 static int run_once = 0; 2601 2602 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi) 2603 panic("Kernels supporting XPA currently require CPUs with RIXI"); 2604 2605 output_pgtable_bits_defines(); 2606 check_pabits(); 2607 2608 #ifdef CONFIG_64BIT 2609 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 2610 #endif 2611 2612 switch (current_cpu_type()) { 2613 case CPU_R2000: 2614 case CPU_R3000: 2615 case CPU_R3000A: 2616 case CPU_R3081E: 2617 case CPU_TX3912: 2618 case CPU_TX3922: 2619 case CPU_TX3927: 2620 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 2621 if (cpu_has_local_ebase) 2622 build_r3000_tlb_refill_handler(); 2623 if (!run_once) { 2624 if (!cpu_has_local_ebase) 2625 build_r3000_tlb_refill_handler(); 2626 build_setup_pgd(); 2627 build_r3000_tlb_load_handler(); 2628 build_r3000_tlb_store_handler(); 2629 build_r3000_tlb_modify_handler(); 2630 flush_tlb_handlers(); 2631 run_once++; 2632 } 2633 #else 2634 panic("No R3000 TLB refill handler"); 2635 #endif 2636 break; 2637 2638 case CPU_R8000: 2639 panic("No R8000 TLB refill handler yet"); 2640 break; 2641 2642 default: 2643 if (cpu_has_ldpte) 2644 setup_pw(); 2645 2646 if (!run_once) { 2647 scratch_reg = allocate_kscratch(); 2648 build_setup_pgd(); 2649 build_r4000_tlb_load_handler(); 2650 build_r4000_tlb_store_handler(); 2651 build_r4000_tlb_modify_handler(); 2652 if (cpu_has_ldpte) 2653 build_loongson3_tlb_refill_handler(); 2654 else if (!cpu_has_local_ebase) 2655 build_r4000_tlb_refill_handler(); 2656 flush_tlb_handlers(); 2657 run_once++; 2658 } 2659 if (cpu_has_local_ebase) 2660 build_r4000_tlb_refill_handler(); 2661 if (cpu_has_xpa) 2662 config_xpa_params(); 2663 if (cpu_has_htw) 2664 config_htw_params(); 2665 } 2666 } 2667