1 /* 2 * Copyright (C) 2006 Chris Dearman (chris@mips.com), 3 */ 4 #include <linux/init.h> 5 #include <linux/kernel.h> 6 #include <linux/sched.h> 7 #include <linux/mm.h> 8 9 #include <asm/mipsregs.h> 10 #include <asm/bcache.h> 11 #include <asm/cacheops.h> 12 #include <asm/page.h> 13 #include <asm/pgtable.h> 14 #include <asm/system.h> 15 #include <asm/mmu_context.h> 16 #include <asm/r4kcache.h> 17 18 /* 19 * MIPS32/MIPS64 L2 cache handling 20 */ 21 22 /* 23 * Writeback and invalidate the secondary cache before DMA. 24 */ 25 static void mips_sc_wback_inv(unsigned long addr, unsigned long size) 26 { 27 blast_scache_range(addr, addr + size); 28 } 29 30 /* 31 * Invalidate the secondary cache before DMA. 32 */ 33 static void mips_sc_inv(unsigned long addr, unsigned long size) 34 { 35 unsigned long lsize = cpu_scache_line_size(); 36 unsigned long almask = ~(lsize - 1); 37 38 cache_op(Hit_Writeback_Inv_SD, addr & almask); 39 cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask); 40 blast_inv_scache_range(addr, addr + size); 41 } 42 43 static void mips_sc_enable(void) 44 { 45 /* L2 cache is permanently enabled */ 46 } 47 48 static void mips_sc_disable(void) 49 { 50 /* L2 cache is permanently enabled */ 51 } 52 53 static struct bcache_ops mips_sc_ops = { 54 .bc_enable = mips_sc_enable, 55 .bc_disable = mips_sc_disable, 56 .bc_wback_inv = mips_sc_wback_inv, 57 .bc_inv = mips_sc_inv 58 }; 59 60 static inline int __init mips_sc_probe(void) 61 { 62 struct cpuinfo_mips *c = ¤t_cpu_data; 63 unsigned int config1, config2; 64 unsigned int tmp; 65 66 /* Mark as not present until probe completed */ 67 c->scache.flags |= MIPS_CACHE_NOT_PRESENT; 68 69 /* Ignore anything but MIPSxx processors */ 70 if (c->isa_level != MIPS_CPU_ISA_M32R1 && 71 c->isa_level != MIPS_CPU_ISA_M32R2 && 72 c->isa_level != MIPS_CPU_ISA_M64R1 && 73 c->isa_level != MIPS_CPU_ISA_M64R2) 74 return 0; 75 76 /* Does this MIPS32/MIPS64 CPU have a config2 register? */ 77 config1 = read_c0_config1(); 78 if (!(config1 & MIPS_CONF_M)) 79 return 0; 80 81 config2 = read_c0_config2(); 82 tmp = (config2 >> 4) & 0x0f; 83 if (0 < tmp && tmp <= 7) 84 c->scache.linesz = 2 << tmp; 85 else 86 return 0; 87 88 tmp = (config2 >> 8) & 0x0f; 89 if (0 <= tmp && tmp <= 7) 90 c->scache.sets = 64 << tmp; 91 else 92 return 0; 93 94 tmp = (config2 >> 0) & 0x0f; 95 if (0 <= tmp && tmp <= 7) 96 c->scache.ways = tmp + 1; 97 else 98 return 0; 99 100 c->scache.waysize = c->scache.sets * c->scache.linesz; 101 c->scache.waybit = __ffs(c->scache.waysize); 102 103 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 104 105 return 1; 106 } 107 108 int __cpuinit mips_sc_init(void) 109 { 110 int found = mips_sc_probe(); 111 if (found) { 112 mips_sc_enable(); 113 bcops = &mips_sc_ops; 114 } 115 return found; 116 } 117