1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 */ 10 #include <linux/cpu_pm.h> 11 #include <linux/hardirq.h> 12 #include <linux/init.h> 13 #include <linux/highmem.h> 14 #include <linux/kernel.h> 15 #include <linux/linkage.h> 16 #include <linux/preempt.h> 17 #include <linux/sched.h> 18 #include <linux/smp.h> 19 #include <linux/mm.h> 20 #include <linux/module.h> 21 #include <linux/bitops.h> 22 23 #include <asm/bcache.h> 24 #include <asm/bootinfo.h> 25 #include <asm/cache.h> 26 #include <asm/cacheops.h> 27 #include <asm/cpu.h> 28 #include <asm/cpu-features.h> 29 #include <asm/cpu-type.h> 30 #include <asm/io.h> 31 #include <asm/page.h> 32 #include <asm/pgtable.h> 33 #include <asm/r4kcache.h> 34 #include <asm/sections.h> 35 #include <asm/mmu_context.h> 36 #include <asm/war.h> 37 #include <asm/cacheflush.h> /* for run_uncached() */ 38 #include <asm/traps.h> 39 #include <asm/dma-coherence.h> 40 #include <asm/mips-cm.h> 41 42 /* 43 * Special Variant of smp_call_function for use by cache functions: 44 * 45 * o No return value 46 * o collapses to normal function call on UP kernels 47 * o collapses to normal function call on systems with a single shared 48 * primary cache. 49 * o doesn't disable interrupts on the local CPU 50 */ 51 static inline void r4k_on_each_cpu(void (*func) (void *info), void *info) 52 { 53 preempt_disable(); 54 55 /* 56 * The Coherent Manager propagates address-based cache ops to other 57 * cores but not index-based ops. However, r4k_on_each_cpu is used 58 * in both cases so there is no easy way to tell what kind of op is 59 * executed to the other cores. The best we can probably do is 60 * to restrict that call when a CM is not present because both 61 * CM-based SMP protocols (CMP & CPS) restrict index-based cache ops. 62 */ 63 if (!mips_cm_present()) 64 smp_call_function_many(&cpu_foreign_map, func, info, 1); 65 func(info); 66 preempt_enable(); 67 } 68 69 #if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS) 70 #define cpu_has_safe_index_cacheops 0 71 #else 72 #define cpu_has_safe_index_cacheops 1 73 #endif 74 75 /* 76 * Must die. 77 */ 78 static unsigned long icache_size __read_mostly; 79 static unsigned long dcache_size __read_mostly; 80 static unsigned long scache_size __read_mostly; 81 82 /* 83 * Dummy cache handling routines for machines without boardcaches 84 */ 85 static void cache_noop(void) {} 86 87 static struct bcache_ops no_sc_ops = { 88 .bc_enable = (void *)cache_noop, 89 .bc_disable = (void *)cache_noop, 90 .bc_wback_inv = (void *)cache_noop, 91 .bc_inv = (void *)cache_noop 92 }; 93 94 struct bcache_ops *bcops = &no_sc_ops; 95 96 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) 97 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) 98 99 #define R4600_HIT_CACHEOP_WAR_IMPL \ 100 do { \ 101 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ 102 *(volatile unsigned long *)CKSEG1; \ 103 if (R4600_V1_HIT_CACHEOP_WAR) \ 104 __asm__ __volatile__("nop;nop;nop;nop"); \ 105 } while (0) 106 107 static void (*r4k_blast_dcache_page)(unsigned long addr); 108 109 static inline void r4k_blast_dcache_page_dc32(unsigned long addr) 110 { 111 R4600_HIT_CACHEOP_WAR_IMPL; 112 blast_dcache32_page(addr); 113 } 114 115 static inline void r4k_blast_dcache_page_dc64(unsigned long addr) 116 { 117 blast_dcache64_page(addr); 118 } 119 120 static inline void r4k_blast_dcache_page_dc128(unsigned long addr) 121 { 122 blast_dcache128_page(addr); 123 } 124 125 static void r4k_blast_dcache_page_setup(void) 126 { 127 unsigned long dc_lsize = cpu_dcache_line_size(); 128 129 switch (dc_lsize) { 130 case 0: 131 r4k_blast_dcache_page = (void *)cache_noop; 132 break; 133 case 16: 134 r4k_blast_dcache_page = blast_dcache16_page; 135 break; 136 case 32: 137 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; 138 break; 139 case 64: 140 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; 141 break; 142 case 128: 143 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128; 144 break; 145 default: 146 break; 147 } 148 } 149 150 #ifndef CONFIG_EVA 151 #define r4k_blast_dcache_user_page r4k_blast_dcache_page 152 #else 153 154 static void (*r4k_blast_dcache_user_page)(unsigned long addr); 155 156 static void r4k_blast_dcache_user_page_setup(void) 157 { 158 unsigned long dc_lsize = cpu_dcache_line_size(); 159 160 if (dc_lsize == 0) 161 r4k_blast_dcache_user_page = (void *)cache_noop; 162 else if (dc_lsize == 16) 163 r4k_blast_dcache_user_page = blast_dcache16_user_page; 164 else if (dc_lsize == 32) 165 r4k_blast_dcache_user_page = blast_dcache32_user_page; 166 else if (dc_lsize == 64) 167 r4k_blast_dcache_user_page = blast_dcache64_user_page; 168 } 169 170 #endif 171 172 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); 173 174 static void r4k_blast_dcache_page_indexed_setup(void) 175 { 176 unsigned long dc_lsize = cpu_dcache_line_size(); 177 178 if (dc_lsize == 0) 179 r4k_blast_dcache_page_indexed = (void *)cache_noop; 180 else if (dc_lsize == 16) 181 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; 182 else if (dc_lsize == 32) 183 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; 184 else if (dc_lsize == 64) 185 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; 186 else if (dc_lsize == 128) 187 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed; 188 } 189 190 void (* r4k_blast_dcache)(void); 191 EXPORT_SYMBOL(r4k_blast_dcache); 192 193 static void r4k_blast_dcache_setup(void) 194 { 195 unsigned long dc_lsize = cpu_dcache_line_size(); 196 197 if (dc_lsize == 0) 198 r4k_blast_dcache = (void *)cache_noop; 199 else if (dc_lsize == 16) 200 r4k_blast_dcache = blast_dcache16; 201 else if (dc_lsize == 32) 202 r4k_blast_dcache = blast_dcache32; 203 else if (dc_lsize == 64) 204 r4k_blast_dcache = blast_dcache64; 205 else if (dc_lsize == 128) 206 r4k_blast_dcache = blast_dcache128; 207 } 208 209 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ 210 #define JUMP_TO_ALIGN(order) \ 211 __asm__ __volatile__( \ 212 "b\t1f\n\t" \ 213 ".align\t" #order "\n\t" \ 214 "1:\n\t" \ 215 ) 216 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ 217 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) 218 219 static inline void blast_r4600_v1_icache32(void) 220 { 221 unsigned long flags; 222 223 local_irq_save(flags); 224 blast_icache32(); 225 local_irq_restore(flags); 226 } 227 228 static inline void tx49_blast_icache32(void) 229 { 230 unsigned long start = INDEX_BASE; 231 unsigned long end = start + current_cpu_data.icache.waysize; 232 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; 233 unsigned long ws_end = current_cpu_data.icache.ways << 234 current_cpu_data.icache.waybit; 235 unsigned long ws, addr; 236 237 CACHE32_UNROLL32_ALIGN2; 238 /* I'm in even chunk. blast odd chunks */ 239 for (ws = 0; ws < ws_end; ws += ws_inc) 240 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 241 cache32_unroll32(addr|ws, Index_Invalidate_I); 242 CACHE32_UNROLL32_ALIGN; 243 /* I'm in odd chunk. blast even chunks */ 244 for (ws = 0; ws < ws_end; ws += ws_inc) 245 for (addr = start; addr < end; addr += 0x400 * 2) 246 cache32_unroll32(addr|ws, Index_Invalidate_I); 247 } 248 249 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) 250 { 251 unsigned long flags; 252 253 local_irq_save(flags); 254 blast_icache32_page_indexed(page); 255 local_irq_restore(flags); 256 } 257 258 static inline void tx49_blast_icache32_page_indexed(unsigned long page) 259 { 260 unsigned long indexmask = current_cpu_data.icache.waysize - 1; 261 unsigned long start = INDEX_BASE + (page & indexmask); 262 unsigned long end = start + PAGE_SIZE; 263 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; 264 unsigned long ws_end = current_cpu_data.icache.ways << 265 current_cpu_data.icache.waybit; 266 unsigned long ws, addr; 267 268 CACHE32_UNROLL32_ALIGN2; 269 /* I'm in even chunk. blast odd chunks */ 270 for (ws = 0; ws < ws_end; ws += ws_inc) 271 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 272 cache32_unroll32(addr|ws, Index_Invalidate_I); 273 CACHE32_UNROLL32_ALIGN; 274 /* I'm in odd chunk. blast even chunks */ 275 for (ws = 0; ws < ws_end; ws += ws_inc) 276 for (addr = start; addr < end; addr += 0x400 * 2) 277 cache32_unroll32(addr|ws, Index_Invalidate_I); 278 } 279 280 static void (* r4k_blast_icache_page)(unsigned long addr); 281 282 static void r4k_blast_icache_page_setup(void) 283 { 284 unsigned long ic_lsize = cpu_icache_line_size(); 285 286 if (ic_lsize == 0) 287 r4k_blast_icache_page = (void *)cache_noop; 288 else if (ic_lsize == 16) 289 r4k_blast_icache_page = blast_icache16_page; 290 else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2) 291 r4k_blast_icache_page = loongson2_blast_icache32_page; 292 else if (ic_lsize == 32) 293 r4k_blast_icache_page = blast_icache32_page; 294 else if (ic_lsize == 64) 295 r4k_blast_icache_page = blast_icache64_page; 296 else if (ic_lsize == 128) 297 r4k_blast_icache_page = blast_icache128_page; 298 } 299 300 #ifndef CONFIG_EVA 301 #define r4k_blast_icache_user_page r4k_blast_icache_page 302 #else 303 304 static void (*r4k_blast_icache_user_page)(unsigned long addr); 305 306 static void r4k_blast_icache_user_page_setup(void) 307 { 308 unsigned long ic_lsize = cpu_icache_line_size(); 309 310 if (ic_lsize == 0) 311 r4k_blast_icache_user_page = (void *)cache_noop; 312 else if (ic_lsize == 16) 313 r4k_blast_icache_user_page = blast_icache16_user_page; 314 else if (ic_lsize == 32) 315 r4k_blast_icache_user_page = blast_icache32_user_page; 316 else if (ic_lsize == 64) 317 r4k_blast_icache_user_page = blast_icache64_user_page; 318 } 319 320 #endif 321 322 static void (* r4k_blast_icache_page_indexed)(unsigned long addr); 323 324 static void r4k_blast_icache_page_indexed_setup(void) 325 { 326 unsigned long ic_lsize = cpu_icache_line_size(); 327 328 if (ic_lsize == 0) 329 r4k_blast_icache_page_indexed = (void *)cache_noop; 330 else if (ic_lsize == 16) 331 r4k_blast_icache_page_indexed = blast_icache16_page_indexed; 332 else if (ic_lsize == 32) { 333 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) 334 r4k_blast_icache_page_indexed = 335 blast_icache32_r4600_v1_page_indexed; 336 else if (TX49XX_ICACHE_INDEX_INV_WAR) 337 r4k_blast_icache_page_indexed = 338 tx49_blast_icache32_page_indexed; 339 else if (current_cpu_type() == CPU_LOONGSON2) 340 r4k_blast_icache_page_indexed = 341 loongson2_blast_icache32_page_indexed; 342 else 343 r4k_blast_icache_page_indexed = 344 blast_icache32_page_indexed; 345 } else if (ic_lsize == 64) 346 r4k_blast_icache_page_indexed = blast_icache64_page_indexed; 347 } 348 349 void (* r4k_blast_icache)(void); 350 EXPORT_SYMBOL(r4k_blast_icache); 351 352 static void r4k_blast_icache_setup(void) 353 { 354 unsigned long ic_lsize = cpu_icache_line_size(); 355 356 if (ic_lsize == 0) 357 r4k_blast_icache = (void *)cache_noop; 358 else if (ic_lsize == 16) 359 r4k_blast_icache = blast_icache16; 360 else if (ic_lsize == 32) { 361 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) 362 r4k_blast_icache = blast_r4600_v1_icache32; 363 else if (TX49XX_ICACHE_INDEX_INV_WAR) 364 r4k_blast_icache = tx49_blast_icache32; 365 else if (current_cpu_type() == CPU_LOONGSON2) 366 r4k_blast_icache = loongson2_blast_icache32; 367 else 368 r4k_blast_icache = blast_icache32; 369 } else if (ic_lsize == 64) 370 r4k_blast_icache = blast_icache64; 371 else if (ic_lsize == 128) 372 r4k_blast_icache = blast_icache128; 373 } 374 375 static void (* r4k_blast_scache_page)(unsigned long addr); 376 377 static void r4k_blast_scache_page_setup(void) 378 { 379 unsigned long sc_lsize = cpu_scache_line_size(); 380 381 if (scache_size == 0) 382 r4k_blast_scache_page = (void *)cache_noop; 383 else if (sc_lsize == 16) 384 r4k_blast_scache_page = blast_scache16_page; 385 else if (sc_lsize == 32) 386 r4k_blast_scache_page = blast_scache32_page; 387 else if (sc_lsize == 64) 388 r4k_blast_scache_page = blast_scache64_page; 389 else if (sc_lsize == 128) 390 r4k_blast_scache_page = blast_scache128_page; 391 } 392 393 static void (* r4k_blast_scache_page_indexed)(unsigned long addr); 394 395 static void r4k_blast_scache_page_indexed_setup(void) 396 { 397 unsigned long sc_lsize = cpu_scache_line_size(); 398 399 if (scache_size == 0) 400 r4k_blast_scache_page_indexed = (void *)cache_noop; 401 else if (sc_lsize == 16) 402 r4k_blast_scache_page_indexed = blast_scache16_page_indexed; 403 else if (sc_lsize == 32) 404 r4k_blast_scache_page_indexed = blast_scache32_page_indexed; 405 else if (sc_lsize == 64) 406 r4k_blast_scache_page_indexed = blast_scache64_page_indexed; 407 else if (sc_lsize == 128) 408 r4k_blast_scache_page_indexed = blast_scache128_page_indexed; 409 } 410 411 static void (* r4k_blast_scache)(void); 412 413 static void r4k_blast_scache_setup(void) 414 { 415 unsigned long sc_lsize = cpu_scache_line_size(); 416 417 if (scache_size == 0) 418 r4k_blast_scache = (void *)cache_noop; 419 else if (sc_lsize == 16) 420 r4k_blast_scache = blast_scache16; 421 else if (sc_lsize == 32) 422 r4k_blast_scache = blast_scache32; 423 else if (sc_lsize == 64) 424 r4k_blast_scache = blast_scache64; 425 else if (sc_lsize == 128) 426 r4k_blast_scache = blast_scache128; 427 } 428 429 static inline void local_r4k___flush_cache_all(void * args) 430 { 431 switch (current_cpu_type()) { 432 case CPU_LOONGSON2: 433 case CPU_LOONGSON3: 434 case CPU_R4000SC: 435 case CPU_R4000MC: 436 case CPU_R4400SC: 437 case CPU_R4400MC: 438 case CPU_R10000: 439 case CPU_R12000: 440 case CPU_R14000: 441 case CPU_R16000: 442 /* 443 * These caches are inclusive caches, that is, if something 444 * is not cached in the S-cache, we know it also won't be 445 * in one of the primary caches. 446 */ 447 r4k_blast_scache(); 448 break; 449 450 default: 451 r4k_blast_dcache(); 452 r4k_blast_icache(); 453 break; 454 } 455 } 456 457 static void r4k___flush_cache_all(void) 458 { 459 r4k_on_each_cpu(local_r4k___flush_cache_all, NULL); 460 } 461 462 static inline int has_valid_asid(const struct mm_struct *mm) 463 { 464 #ifdef CONFIG_MIPS_MT_SMP 465 int i; 466 467 for_each_online_cpu(i) 468 if (cpu_context(i, mm)) 469 return 1; 470 471 return 0; 472 #else 473 return cpu_context(smp_processor_id(), mm); 474 #endif 475 } 476 477 static void r4k__flush_cache_vmap(void) 478 { 479 r4k_blast_dcache(); 480 } 481 482 static void r4k__flush_cache_vunmap(void) 483 { 484 r4k_blast_dcache(); 485 } 486 487 static inline void local_r4k_flush_cache_range(void * args) 488 { 489 struct vm_area_struct *vma = args; 490 int exec = vma->vm_flags & VM_EXEC; 491 492 if (!(has_valid_asid(vma->vm_mm))) 493 return; 494 495 /* 496 * If dcache can alias, we must blast it since mapping is changing. 497 * If executable, we must ensure any dirty lines are written back far 498 * enough to be visible to icache. 499 */ 500 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) 501 r4k_blast_dcache(); 502 /* If executable, blast stale lines from icache */ 503 if (exec) 504 r4k_blast_icache(); 505 } 506 507 static void r4k_flush_cache_range(struct vm_area_struct *vma, 508 unsigned long start, unsigned long end) 509 { 510 int exec = vma->vm_flags & VM_EXEC; 511 512 if (cpu_has_dc_aliases || exec) 513 r4k_on_each_cpu(local_r4k_flush_cache_range, vma); 514 } 515 516 static inline void local_r4k_flush_cache_mm(void * args) 517 { 518 struct mm_struct *mm = args; 519 520 if (!has_valid_asid(mm)) 521 return; 522 523 /* 524 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we 525 * only flush the primary caches but R1x000 behave sane ... 526 * R4000SC and R4400SC indexed S-cache ops also invalidate primary 527 * caches, so we can bail out early. 528 */ 529 if (current_cpu_type() == CPU_R4000SC || 530 current_cpu_type() == CPU_R4000MC || 531 current_cpu_type() == CPU_R4400SC || 532 current_cpu_type() == CPU_R4400MC) { 533 r4k_blast_scache(); 534 return; 535 } 536 537 r4k_blast_dcache(); 538 } 539 540 static void r4k_flush_cache_mm(struct mm_struct *mm) 541 { 542 if (!cpu_has_dc_aliases) 543 return; 544 545 r4k_on_each_cpu(local_r4k_flush_cache_mm, mm); 546 } 547 548 struct flush_cache_page_args { 549 struct vm_area_struct *vma; 550 unsigned long addr; 551 unsigned long pfn; 552 }; 553 554 static inline void local_r4k_flush_cache_page(void *args) 555 { 556 struct flush_cache_page_args *fcp_args = args; 557 struct vm_area_struct *vma = fcp_args->vma; 558 unsigned long addr = fcp_args->addr; 559 struct page *page = pfn_to_page(fcp_args->pfn); 560 int exec = vma->vm_flags & VM_EXEC; 561 struct mm_struct *mm = vma->vm_mm; 562 int map_coherent = 0; 563 pgd_t *pgdp; 564 pud_t *pudp; 565 pmd_t *pmdp; 566 pte_t *ptep; 567 void *vaddr; 568 569 /* 570 * If ownes no valid ASID yet, cannot possibly have gotten 571 * this page into the cache. 572 */ 573 if (!has_valid_asid(mm)) 574 return; 575 576 addr &= PAGE_MASK; 577 pgdp = pgd_offset(mm, addr); 578 pudp = pud_offset(pgdp, addr); 579 pmdp = pmd_offset(pudp, addr); 580 ptep = pte_offset(pmdp, addr); 581 582 /* 583 * If the page isn't marked valid, the page cannot possibly be 584 * in the cache. 585 */ 586 if (!(pte_present(*ptep))) 587 return; 588 589 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) 590 vaddr = NULL; 591 else { 592 /* 593 * Use kmap_coherent or kmap_atomic to do flushes for 594 * another ASID than the current one. 595 */ 596 map_coherent = (cpu_has_dc_aliases && 597 page_mapcount(page) && 598 !Page_dcache_dirty(page)); 599 if (map_coherent) 600 vaddr = kmap_coherent(page, addr); 601 else 602 vaddr = kmap_atomic(page); 603 addr = (unsigned long)vaddr; 604 } 605 606 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 607 vaddr ? r4k_blast_dcache_page(addr) : 608 r4k_blast_dcache_user_page(addr); 609 if (exec && !cpu_icache_snoops_remote_store) 610 r4k_blast_scache_page(addr); 611 } 612 if (exec) { 613 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { 614 int cpu = smp_processor_id(); 615 616 if (cpu_context(cpu, mm) != 0) 617 drop_mmu_context(mm, cpu); 618 } else 619 vaddr ? r4k_blast_icache_page(addr) : 620 r4k_blast_icache_user_page(addr); 621 } 622 623 if (vaddr) { 624 if (map_coherent) 625 kunmap_coherent(); 626 else 627 kunmap_atomic(vaddr); 628 } 629 } 630 631 static void r4k_flush_cache_page(struct vm_area_struct *vma, 632 unsigned long addr, unsigned long pfn) 633 { 634 struct flush_cache_page_args args; 635 636 args.vma = vma; 637 args.addr = addr; 638 args.pfn = pfn; 639 640 r4k_on_each_cpu(local_r4k_flush_cache_page, &args); 641 } 642 643 static inline void local_r4k_flush_data_cache_page(void * addr) 644 { 645 r4k_blast_dcache_page((unsigned long) addr); 646 } 647 648 static void r4k_flush_data_cache_page(unsigned long addr) 649 { 650 if (in_atomic()) 651 local_r4k_flush_data_cache_page((void *)addr); 652 else 653 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr); 654 } 655 656 struct flush_icache_range_args { 657 unsigned long start; 658 unsigned long end; 659 }; 660 661 static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end) 662 { 663 if (!cpu_has_ic_fills_f_dc) { 664 if (end - start >= dcache_size) { 665 r4k_blast_dcache(); 666 } else { 667 R4600_HIT_CACHEOP_WAR_IMPL; 668 protected_blast_dcache_range(start, end); 669 } 670 } 671 672 if (end - start > icache_size) 673 r4k_blast_icache(); 674 else { 675 switch (boot_cpu_type()) { 676 case CPU_LOONGSON2: 677 protected_loongson2_blast_icache_range(start, end); 678 break; 679 680 default: 681 protected_blast_icache_range(start, end); 682 break; 683 } 684 } 685 #ifdef CONFIG_EVA 686 /* 687 * Due to all possible segment mappings, there might cache aliases 688 * caused by the bootloader being in non-EVA mode, and the CPU switching 689 * to EVA during early kernel init. It's best to flush the scache 690 * to avoid having secondary cores fetching stale data and lead to 691 * kernel crashes. 692 */ 693 bc_wback_inv(start, (end - start)); 694 __sync(); 695 #endif 696 } 697 698 static inline void local_r4k_flush_icache_range_ipi(void *args) 699 { 700 struct flush_icache_range_args *fir_args = args; 701 unsigned long start = fir_args->start; 702 unsigned long end = fir_args->end; 703 704 local_r4k_flush_icache_range(start, end); 705 } 706 707 static void r4k_flush_icache_range(unsigned long start, unsigned long end) 708 { 709 struct flush_icache_range_args args; 710 711 args.start = start; 712 args.end = end; 713 714 r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args); 715 instruction_hazard(); 716 } 717 718 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) 719 720 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) 721 { 722 /* Catch bad driver code */ 723 BUG_ON(size == 0); 724 725 preempt_disable(); 726 if (cpu_has_inclusive_pcaches) { 727 if (size >= scache_size) 728 r4k_blast_scache(); 729 else 730 blast_scache_range(addr, addr + size); 731 preempt_enable(); 732 __sync(); 733 return; 734 } 735 736 /* 737 * Either no secondary cache or the available caches don't have the 738 * subset property so we have to flush the primary caches 739 * explicitly 740 */ 741 if (cpu_has_safe_index_cacheops && size >= dcache_size) { 742 r4k_blast_dcache(); 743 } else { 744 R4600_HIT_CACHEOP_WAR_IMPL; 745 blast_dcache_range(addr, addr + size); 746 } 747 preempt_enable(); 748 749 bc_wback_inv(addr, size); 750 __sync(); 751 } 752 753 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) 754 { 755 /* Catch bad driver code */ 756 BUG_ON(size == 0); 757 758 preempt_disable(); 759 if (cpu_has_inclusive_pcaches) { 760 if (size >= scache_size) 761 r4k_blast_scache(); 762 else { 763 /* 764 * There is no clearly documented alignment requirement 765 * for the cache instruction on MIPS processors and 766 * some processors, among them the RM5200 and RM7000 767 * QED processors will throw an address error for cache 768 * hit ops with insufficient alignment. Solved by 769 * aligning the address to cache line size. 770 */ 771 blast_inv_scache_range(addr, addr + size); 772 } 773 preempt_enable(); 774 __sync(); 775 return; 776 } 777 778 if (cpu_has_safe_index_cacheops && size >= dcache_size) { 779 r4k_blast_dcache(); 780 } else { 781 R4600_HIT_CACHEOP_WAR_IMPL; 782 blast_inv_dcache_range(addr, addr + size); 783 } 784 preempt_enable(); 785 786 bc_inv(addr, size); 787 __sync(); 788 } 789 #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ 790 791 /* 792 * While we're protected against bad userland addresses we don't care 793 * very much about what happens in that case. Usually a segmentation 794 * fault will dump the process later on anyway ... 795 */ 796 static void local_r4k_flush_cache_sigtramp(void * arg) 797 { 798 unsigned long ic_lsize = cpu_icache_line_size(); 799 unsigned long dc_lsize = cpu_dcache_line_size(); 800 unsigned long sc_lsize = cpu_scache_line_size(); 801 unsigned long addr = (unsigned long) arg; 802 803 R4600_HIT_CACHEOP_WAR_IMPL; 804 if (dc_lsize) 805 protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); 806 if (!cpu_icache_snoops_remote_store && scache_size) 807 protected_writeback_scache_line(addr & ~(sc_lsize - 1)); 808 if (ic_lsize) 809 protected_flush_icache_line(addr & ~(ic_lsize - 1)); 810 if (MIPS4K_ICACHE_REFILL_WAR) { 811 __asm__ __volatile__ ( 812 ".set push\n\t" 813 ".set noat\n\t" 814 ".set "MIPS_ISA_LEVEL"\n\t" 815 #ifdef CONFIG_32BIT 816 "la $at,1f\n\t" 817 #endif 818 #ifdef CONFIG_64BIT 819 "dla $at,1f\n\t" 820 #endif 821 "cache %0,($at)\n\t" 822 "nop; nop; nop\n" 823 "1:\n\t" 824 ".set pop" 825 : 826 : "i" (Hit_Invalidate_I)); 827 } 828 if (MIPS_CACHE_SYNC_WAR) 829 __asm__ __volatile__ ("sync"); 830 } 831 832 static void r4k_flush_cache_sigtramp(unsigned long addr) 833 { 834 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr); 835 } 836 837 static void r4k_flush_icache_all(void) 838 { 839 if (cpu_has_vtag_icache) 840 r4k_blast_icache(); 841 } 842 843 struct flush_kernel_vmap_range_args { 844 unsigned long vaddr; 845 int size; 846 }; 847 848 static inline void local_r4k_flush_kernel_vmap_range(void *args) 849 { 850 struct flush_kernel_vmap_range_args *vmra = args; 851 unsigned long vaddr = vmra->vaddr; 852 int size = vmra->size; 853 854 /* 855 * Aliases only affect the primary caches so don't bother with 856 * S-caches or T-caches. 857 */ 858 if (cpu_has_safe_index_cacheops && size >= dcache_size) 859 r4k_blast_dcache(); 860 else { 861 R4600_HIT_CACHEOP_WAR_IMPL; 862 blast_dcache_range(vaddr, vaddr + size); 863 } 864 } 865 866 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) 867 { 868 struct flush_kernel_vmap_range_args args; 869 870 args.vaddr = (unsigned long) vaddr; 871 args.size = size; 872 873 r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args); 874 } 875 876 static inline void rm7k_erratum31(void) 877 { 878 const unsigned long ic_lsize = 32; 879 unsigned long addr; 880 881 /* RM7000 erratum #31. The icache is screwed at startup. */ 882 write_c0_taglo(0); 883 write_c0_taghi(0); 884 885 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { 886 __asm__ __volatile__ ( 887 ".set push\n\t" 888 ".set noreorder\n\t" 889 ".set mips3\n\t" 890 "cache\t%1, 0(%0)\n\t" 891 "cache\t%1, 0x1000(%0)\n\t" 892 "cache\t%1, 0x2000(%0)\n\t" 893 "cache\t%1, 0x3000(%0)\n\t" 894 "cache\t%2, 0(%0)\n\t" 895 "cache\t%2, 0x1000(%0)\n\t" 896 "cache\t%2, 0x2000(%0)\n\t" 897 "cache\t%2, 0x3000(%0)\n\t" 898 "cache\t%1, 0(%0)\n\t" 899 "cache\t%1, 0x1000(%0)\n\t" 900 "cache\t%1, 0x2000(%0)\n\t" 901 "cache\t%1, 0x3000(%0)\n\t" 902 ".set pop\n" 903 : 904 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); 905 } 906 } 907 908 static inline int alias_74k_erratum(struct cpuinfo_mips *c) 909 { 910 unsigned int imp = c->processor_id & PRID_IMP_MASK; 911 unsigned int rev = c->processor_id & PRID_REV_MASK; 912 int present = 0; 913 914 /* 915 * Early versions of the 74K do not update the cache tags on a 916 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG 917 * aliases. In this case it is better to treat the cache as always 918 * having aliases. Also disable the synonym tag update feature 919 * where available. In this case no opportunistic tag update will 920 * happen where a load causes a virtual address miss but a physical 921 * address hit during a D-cache look-up. 922 */ 923 switch (imp) { 924 case PRID_IMP_74K: 925 if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) 926 present = 1; 927 if (rev == PRID_REV_ENCODE_332(2, 4, 0)) 928 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 929 break; 930 case PRID_IMP_1074K: 931 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { 932 present = 1; 933 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 934 } 935 break; 936 default: 937 BUG(); 938 } 939 940 return present; 941 } 942 943 static void b5k_instruction_hazard(void) 944 { 945 __sync(); 946 __sync(); 947 __asm__ __volatile__( 948 " nop; nop; nop; nop; nop; nop; nop; nop\n" 949 " nop; nop; nop; nop; nop; nop; nop; nop\n" 950 " nop; nop; nop; nop; nop; nop; nop; nop\n" 951 " nop; nop; nop; nop; nop; nop; nop; nop\n" 952 : : : "memory"); 953 } 954 955 static char *way_string[] = { NULL, "direct mapped", "2-way", 956 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way", 957 "9-way", "10-way", "11-way", "12-way", 958 "13-way", "14-way", "15-way", "16-way", 959 }; 960 961 static void probe_pcache(void) 962 { 963 struct cpuinfo_mips *c = ¤t_cpu_data; 964 unsigned int config = read_c0_config(); 965 unsigned int prid = read_c0_prid(); 966 int has_74k_erratum = 0; 967 unsigned long config1; 968 unsigned int lsize; 969 970 switch (current_cpu_type()) { 971 case CPU_R4600: /* QED style two way caches? */ 972 case CPU_R4700: 973 case CPU_R5000: 974 case CPU_NEVADA: 975 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 976 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 977 c->icache.ways = 2; 978 c->icache.waybit = __ffs(icache_size/2); 979 980 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 981 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 982 c->dcache.ways = 2; 983 c->dcache.waybit= __ffs(dcache_size/2); 984 985 c->options |= MIPS_CPU_CACHE_CDEX_P; 986 break; 987 988 case CPU_R5432: 989 case CPU_R5500: 990 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 991 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 992 c->icache.ways = 2; 993 c->icache.waybit= 0; 994 995 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 996 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 997 c->dcache.ways = 2; 998 c->dcache.waybit = 0; 999 1000 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; 1001 break; 1002 1003 case CPU_TX49XX: 1004 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1005 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1006 c->icache.ways = 4; 1007 c->icache.waybit= 0; 1008 1009 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1010 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1011 c->dcache.ways = 4; 1012 c->dcache.waybit = 0; 1013 1014 c->options |= MIPS_CPU_CACHE_CDEX_P; 1015 c->options |= MIPS_CPU_PREFETCH; 1016 break; 1017 1018 case CPU_R4000PC: 1019 case CPU_R4000SC: 1020 case CPU_R4000MC: 1021 case CPU_R4400PC: 1022 case CPU_R4400SC: 1023 case CPU_R4400MC: 1024 case CPU_R4300: 1025 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1026 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1027 c->icache.ways = 1; 1028 c->icache.waybit = 0; /* doesn't matter */ 1029 1030 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1031 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1032 c->dcache.ways = 1; 1033 c->dcache.waybit = 0; /* does not matter */ 1034 1035 c->options |= MIPS_CPU_CACHE_CDEX_P; 1036 break; 1037 1038 case CPU_R10000: 1039 case CPU_R12000: 1040 case CPU_R14000: 1041 case CPU_R16000: 1042 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); 1043 c->icache.linesz = 64; 1044 c->icache.ways = 2; 1045 c->icache.waybit = 0; 1046 1047 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); 1048 c->dcache.linesz = 32; 1049 c->dcache.ways = 2; 1050 c->dcache.waybit = 0; 1051 1052 c->options |= MIPS_CPU_PREFETCH; 1053 break; 1054 1055 case CPU_VR4133: 1056 write_c0_config(config & ~VR41_CONF_P4K); 1057 case CPU_VR4131: 1058 /* Workaround for cache instruction bug of VR4131 */ 1059 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || 1060 c->processor_id == 0x0c82U) { 1061 config |= 0x00400000U; 1062 if (c->processor_id == 0x0c80U) 1063 config |= VR41_CONF_BP; 1064 write_c0_config(config); 1065 } else 1066 c->options |= MIPS_CPU_CACHE_CDEX_P; 1067 1068 icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); 1069 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1070 c->icache.ways = 2; 1071 c->icache.waybit = __ffs(icache_size/2); 1072 1073 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); 1074 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1075 c->dcache.ways = 2; 1076 c->dcache.waybit = __ffs(dcache_size/2); 1077 break; 1078 1079 case CPU_VR41XX: 1080 case CPU_VR4111: 1081 case CPU_VR4121: 1082 case CPU_VR4122: 1083 case CPU_VR4181: 1084 case CPU_VR4181A: 1085 icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); 1086 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1087 c->icache.ways = 1; 1088 c->icache.waybit = 0; /* doesn't matter */ 1089 1090 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); 1091 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1092 c->dcache.ways = 1; 1093 c->dcache.waybit = 0; /* does not matter */ 1094 1095 c->options |= MIPS_CPU_CACHE_CDEX_P; 1096 break; 1097 1098 case CPU_RM7000: 1099 rm7k_erratum31(); 1100 1101 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1102 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1103 c->icache.ways = 4; 1104 c->icache.waybit = __ffs(icache_size / c->icache.ways); 1105 1106 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1107 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1108 c->dcache.ways = 4; 1109 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); 1110 1111 c->options |= MIPS_CPU_CACHE_CDEX_P; 1112 c->options |= MIPS_CPU_PREFETCH; 1113 break; 1114 1115 case CPU_LOONGSON2: 1116 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1117 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1118 if (prid & 0x3) 1119 c->icache.ways = 4; 1120 else 1121 c->icache.ways = 2; 1122 c->icache.waybit = 0; 1123 1124 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1125 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1126 if (prid & 0x3) 1127 c->dcache.ways = 4; 1128 else 1129 c->dcache.ways = 2; 1130 c->dcache.waybit = 0; 1131 break; 1132 1133 case CPU_LOONGSON3: 1134 config1 = read_c0_config1(); 1135 lsize = (config1 >> 19) & 7; 1136 if (lsize) 1137 c->icache.linesz = 2 << lsize; 1138 else 1139 c->icache.linesz = 0; 1140 c->icache.sets = 64 << ((config1 >> 22) & 7); 1141 c->icache.ways = 1 + ((config1 >> 16) & 7); 1142 icache_size = c->icache.sets * 1143 c->icache.ways * 1144 c->icache.linesz; 1145 c->icache.waybit = 0; 1146 1147 lsize = (config1 >> 10) & 7; 1148 if (lsize) 1149 c->dcache.linesz = 2 << lsize; 1150 else 1151 c->dcache.linesz = 0; 1152 c->dcache.sets = 64 << ((config1 >> 13) & 7); 1153 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1154 dcache_size = c->dcache.sets * 1155 c->dcache.ways * 1156 c->dcache.linesz; 1157 c->dcache.waybit = 0; 1158 break; 1159 1160 case CPU_CAVIUM_OCTEON3: 1161 /* For now lie about the number of ways. */ 1162 c->icache.linesz = 128; 1163 c->icache.sets = 16; 1164 c->icache.ways = 8; 1165 c->icache.flags |= MIPS_CACHE_VTAG; 1166 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; 1167 1168 c->dcache.linesz = 128; 1169 c->dcache.ways = 8; 1170 c->dcache.sets = 8; 1171 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; 1172 c->options |= MIPS_CPU_PREFETCH; 1173 break; 1174 1175 default: 1176 if (!(config & MIPS_CONF_M)) 1177 panic("Don't know how to probe P-caches on this cpu."); 1178 1179 /* 1180 * So we seem to be a MIPS32 or MIPS64 CPU 1181 * So let's probe the I-cache ... 1182 */ 1183 config1 = read_c0_config1(); 1184 1185 lsize = (config1 >> 19) & 7; 1186 1187 /* IL == 7 is reserved */ 1188 if (lsize == 7) 1189 panic("Invalid icache line size"); 1190 1191 c->icache.linesz = lsize ? 2 << lsize : 0; 1192 1193 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); 1194 c->icache.ways = 1 + ((config1 >> 16) & 7); 1195 1196 icache_size = c->icache.sets * 1197 c->icache.ways * 1198 c->icache.linesz; 1199 c->icache.waybit = __ffs(icache_size/c->icache.ways); 1200 1201 if (config & 0x8) /* VI bit */ 1202 c->icache.flags |= MIPS_CACHE_VTAG; 1203 1204 /* 1205 * Now probe the MIPS32 / MIPS64 data cache. 1206 */ 1207 c->dcache.flags = 0; 1208 1209 lsize = (config1 >> 10) & 7; 1210 1211 /* DL == 7 is reserved */ 1212 if (lsize == 7) 1213 panic("Invalid dcache line size"); 1214 1215 c->dcache.linesz = lsize ? 2 << lsize : 0; 1216 1217 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); 1218 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1219 1220 dcache_size = c->dcache.sets * 1221 c->dcache.ways * 1222 c->dcache.linesz; 1223 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); 1224 1225 c->options |= MIPS_CPU_PREFETCH; 1226 break; 1227 } 1228 1229 /* 1230 * Processor configuration sanity check for the R4000SC erratum 1231 * #5. With page sizes larger than 32kB there is no possibility 1232 * to get a VCE exception anymore so we don't care about this 1233 * misconfiguration. The case is rather theoretical anyway; 1234 * presumably no vendor is shipping his hardware in the "bad" 1235 * configuration. 1236 */ 1237 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 && 1238 (prid & PRID_REV_MASK) < PRID_REV_R4400 && 1239 !(config & CONF_SC) && c->icache.linesz != 16 && 1240 PAGE_SIZE <= 0x8000) 1241 panic("Improper R4000SC processor configuration detected"); 1242 1243 /* compute a couple of other cache variables */ 1244 c->icache.waysize = icache_size / c->icache.ways; 1245 c->dcache.waysize = dcache_size / c->dcache.ways; 1246 1247 c->icache.sets = c->icache.linesz ? 1248 icache_size / (c->icache.linesz * c->icache.ways) : 0; 1249 c->dcache.sets = c->dcache.linesz ? 1250 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; 1251 1252 /* 1253 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way 1254 * virtually indexed so normally would suffer from aliases. So 1255 * normally they'd suffer from aliases but magic in the hardware deals 1256 * with that for us so we don't need to take care ourselves. 1257 */ 1258 switch (current_cpu_type()) { 1259 case CPU_20KC: 1260 case CPU_25KF: 1261 case CPU_SB1: 1262 case CPU_SB1A: 1263 case CPU_XLR: 1264 c->dcache.flags |= MIPS_CACHE_PINDEX; 1265 break; 1266 1267 case CPU_R10000: 1268 case CPU_R12000: 1269 case CPU_R14000: 1270 case CPU_R16000: 1271 break; 1272 1273 case CPU_74K: 1274 case CPU_1074K: 1275 has_74k_erratum = alias_74k_erratum(c); 1276 /* Fall through. */ 1277 case CPU_M14KC: 1278 case CPU_M14KEC: 1279 case CPU_24K: 1280 case CPU_34K: 1281 case CPU_1004K: 1282 case CPU_INTERAPTIV: 1283 case CPU_P5600: 1284 case CPU_PROAPTIV: 1285 case CPU_M5150: 1286 case CPU_QEMU_GENERIC: 1287 case CPU_I6400: 1288 case CPU_P6600: 1289 case CPU_M6250: 1290 if (!(read_c0_config7() & MIPS_CONF7_IAR) && 1291 (c->icache.waysize > PAGE_SIZE)) 1292 c->icache.flags |= MIPS_CACHE_ALIASES; 1293 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) { 1294 /* 1295 * Effectively physically indexed dcache, 1296 * thus no virtual aliases. 1297 */ 1298 c->dcache.flags |= MIPS_CACHE_PINDEX; 1299 break; 1300 } 1301 default: 1302 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) 1303 c->dcache.flags |= MIPS_CACHE_ALIASES; 1304 } 1305 1306 switch (current_cpu_type()) { 1307 case CPU_20KC: 1308 /* 1309 * Some older 20Kc chips doesn't have the 'VI' bit in 1310 * the config register. 1311 */ 1312 c->icache.flags |= MIPS_CACHE_VTAG; 1313 break; 1314 1315 case CPU_ALCHEMY: 1316 case CPU_I6400: 1317 c->icache.flags |= MIPS_CACHE_IC_F_DC; 1318 break; 1319 1320 case CPU_LOONGSON2: 1321 /* 1322 * LOONGSON2 has 4 way icache, but when using indexed cache op, 1323 * one op will act on all 4 ways 1324 */ 1325 c->icache.ways = 1; 1326 } 1327 1328 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", 1329 icache_size >> 10, 1330 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", 1331 way_string[c->icache.ways], c->icache.linesz); 1332 1333 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", 1334 dcache_size >> 10, way_string[c->dcache.ways], 1335 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", 1336 (c->dcache.flags & MIPS_CACHE_ALIASES) ? 1337 "cache aliases" : "no aliases", 1338 c->dcache.linesz); 1339 } 1340 1341 /* 1342 * If you even _breathe_ on this function, look at the gcc output and make sure 1343 * it does not pop things on and off the stack for the cache sizing loop that 1344 * executes in KSEG1 space or else you will crash and burn badly. You have 1345 * been warned. 1346 */ 1347 static int probe_scache(void) 1348 { 1349 unsigned long flags, addr, begin, end, pow2; 1350 unsigned int config = read_c0_config(); 1351 struct cpuinfo_mips *c = ¤t_cpu_data; 1352 1353 if (config & CONF_SC) 1354 return 0; 1355 1356 begin = (unsigned long) &_stext; 1357 begin &= ~((4 * 1024 * 1024) - 1); 1358 end = begin + (4 * 1024 * 1024); 1359 1360 /* 1361 * This is such a bitch, you'd think they would make it easy to do 1362 * this. Away you daemons of stupidity! 1363 */ 1364 local_irq_save(flags); 1365 1366 /* Fill each size-multiple cache line with a valid tag. */ 1367 pow2 = (64 * 1024); 1368 for (addr = begin; addr < end; addr = (begin + pow2)) { 1369 unsigned long *p = (unsigned long *) addr; 1370 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ 1371 pow2 <<= 1; 1372 } 1373 1374 /* Load first line with zero (therefore invalid) tag. */ 1375 write_c0_taglo(0); 1376 write_c0_taghi(0); 1377 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ 1378 cache_op(Index_Store_Tag_I, begin); 1379 cache_op(Index_Store_Tag_D, begin); 1380 cache_op(Index_Store_Tag_SD, begin); 1381 1382 /* Now search for the wrap around point. */ 1383 pow2 = (128 * 1024); 1384 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { 1385 cache_op(Index_Load_Tag_SD, addr); 1386 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ 1387 if (!read_c0_taglo()) 1388 break; 1389 pow2 <<= 1; 1390 } 1391 local_irq_restore(flags); 1392 addr -= begin; 1393 1394 scache_size = addr; 1395 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); 1396 c->scache.ways = 1; 1397 c->scache.waybit = 0; /* does not matter */ 1398 1399 return 1; 1400 } 1401 1402 static void __init loongson2_sc_init(void) 1403 { 1404 struct cpuinfo_mips *c = ¤t_cpu_data; 1405 1406 scache_size = 512*1024; 1407 c->scache.linesz = 32; 1408 c->scache.ways = 4; 1409 c->scache.waybit = 0; 1410 c->scache.waysize = scache_size / (c->scache.ways); 1411 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 1412 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1413 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1414 1415 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1416 } 1417 1418 static void __init loongson3_sc_init(void) 1419 { 1420 struct cpuinfo_mips *c = ¤t_cpu_data; 1421 unsigned int config2, lsize; 1422 1423 config2 = read_c0_config2(); 1424 lsize = (config2 >> 4) & 15; 1425 if (lsize) 1426 c->scache.linesz = 2 << lsize; 1427 else 1428 c->scache.linesz = 0; 1429 c->scache.sets = 64 << ((config2 >> 8) & 15); 1430 c->scache.ways = 1 + (config2 & 15); 1431 1432 scache_size = c->scache.sets * 1433 c->scache.ways * 1434 c->scache.linesz; 1435 /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */ 1436 scache_size *= 4; 1437 c->scache.waybit = 0; 1438 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1439 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1440 if (scache_size) 1441 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1442 return; 1443 } 1444 1445 extern int r5k_sc_init(void); 1446 extern int rm7k_sc_init(void); 1447 extern int mips_sc_init(void); 1448 1449 static void setup_scache(void) 1450 { 1451 struct cpuinfo_mips *c = ¤t_cpu_data; 1452 unsigned int config = read_c0_config(); 1453 int sc_present = 0; 1454 1455 /* 1456 * Do the probing thing on R4000SC and R4400SC processors. Other 1457 * processors don't have a S-cache that would be relevant to the 1458 * Linux memory management. 1459 */ 1460 switch (current_cpu_type()) { 1461 case CPU_R4000SC: 1462 case CPU_R4000MC: 1463 case CPU_R4400SC: 1464 case CPU_R4400MC: 1465 sc_present = run_uncached(probe_scache); 1466 if (sc_present) 1467 c->options |= MIPS_CPU_CACHE_CDEX_S; 1468 break; 1469 1470 case CPU_R10000: 1471 case CPU_R12000: 1472 case CPU_R14000: 1473 case CPU_R16000: 1474 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); 1475 c->scache.linesz = 64 << ((config >> 13) & 1); 1476 c->scache.ways = 2; 1477 c->scache.waybit= 0; 1478 sc_present = 1; 1479 break; 1480 1481 case CPU_R5000: 1482 case CPU_NEVADA: 1483 #ifdef CONFIG_R5000_CPU_SCACHE 1484 r5k_sc_init(); 1485 #endif 1486 return; 1487 1488 case CPU_RM7000: 1489 #ifdef CONFIG_RM7000_CPU_SCACHE 1490 rm7k_sc_init(); 1491 #endif 1492 return; 1493 1494 case CPU_LOONGSON2: 1495 loongson2_sc_init(); 1496 return; 1497 1498 case CPU_LOONGSON3: 1499 loongson3_sc_init(); 1500 return; 1501 1502 case CPU_CAVIUM_OCTEON3: 1503 case CPU_XLP: 1504 /* don't need to worry about L2, fully coherent */ 1505 return; 1506 1507 default: 1508 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | 1509 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 | 1510 MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) { 1511 #ifdef CONFIG_MIPS_CPU_SCACHE 1512 if (mips_sc_init ()) { 1513 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; 1514 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", 1515 scache_size >> 10, 1516 way_string[c->scache.ways], c->scache.linesz); 1517 } 1518 #else 1519 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) 1520 panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); 1521 #endif 1522 return; 1523 } 1524 sc_present = 0; 1525 } 1526 1527 if (!sc_present) 1528 return; 1529 1530 /* compute a couple of other cache variables */ 1531 c->scache.waysize = scache_size / c->scache.ways; 1532 1533 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 1534 1535 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1536 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1537 1538 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1539 } 1540 1541 void au1x00_fixup_config_od(void) 1542 { 1543 /* 1544 * c0_config.od (bit 19) was write only (and read as 0) 1545 * on the early revisions of Alchemy SOCs. It disables the bus 1546 * transaction overlapping and needs to be set to fix various errata. 1547 */ 1548 switch (read_c0_prid()) { 1549 case 0x00030100: /* Au1000 DA */ 1550 case 0x00030201: /* Au1000 HA */ 1551 case 0x00030202: /* Au1000 HB */ 1552 case 0x01030200: /* Au1500 AB */ 1553 /* 1554 * Au1100 errata actually keeps silence about this bit, so we set it 1555 * just in case for those revisions that require it to be set according 1556 * to the (now gone) cpu table. 1557 */ 1558 case 0x02030200: /* Au1100 AB */ 1559 case 0x02030201: /* Au1100 BA */ 1560 case 0x02030202: /* Au1100 BC */ 1561 set_c0_config(1 << 19); 1562 break; 1563 } 1564 } 1565 1566 /* CP0 hazard avoidance. */ 1567 #define NXP_BARRIER() \ 1568 __asm__ __volatile__( \ 1569 ".set noreorder\n\t" \ 1570 "nop; nop; nop; nop; nop; nop;\n\t" \ 1571 ".set reorder\n\t") 1572 1573 static void nxp_pr4450_fixup_config(void) 1574 { 1575 unsigned long config0; 1576 1577 config0 = read_c0_config(); 1578 1579 /* clear all three cache coherency fields */ 1580 config0 &= ~(0x7 | (7 << 25) | (7 << 28)); 1581 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | 1582 ((_page_cachable_default >> _CACHE_SHIFT) << 25) | 1583 ((_page_cachable_default >> _CACHE_SHIFT) << 28)); 1584 write_c0_config(config0); 1585 NXP_BARRIER(); 1586 } 1587 1588 static int cca = -1; 1589 1590 static int __init cca_setup(char *str) 1591 { 1592 get_option(&str, &cca); 1593 1594 return 0; 1595 } 1596 1597 early_param("cca", cca_setup); 1598 1599 static void coherency_setup(void) 1600 { 1601 if (cca < 0 || cca > 7) 1602 cca = read_c0_config() & CONF_CM_CMASK; 1603 _page_cachable_default = cca << _CACHE_SHIFT; 1604 1605 pr_debug("Using cache attribute %d\n", cca); 1606 change_c0_config(CONF_CM_CMASK, cca); 1607 1608 /* 1609 * c0_status.cu=0 specifies that updates by the sc instruction use 1610 * the coherency mode specified by the TLB; 1 means cachable 1611 * coherent update on write will be used. Not all processors have 1612 * this bit and; some wire it to zero, others like Toshiba had the 1613 * silly idea of putting something else there ... 1614 */ 1615 switch (current_cpu_type()) { 1616 case CPU_R4000PC: 1617 case CPU_R4000SC: 1618 case CPU_R4000MC: 1619 case CPU_R4400PC: 1620 case CPU_R4400SC: 1621 case CPU_R4400MC: 1622 clear_c0_config(CONF_CU); 1623 break; 1624 /* 1625 * We need to catch the early Alchemy SOCs with 1626 * the write-only co_config.od bit and set it back to one on: 1627 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB 1628 */ 1629 case CPU_ALCHEMY: 1630 au1x00_fixup_config_od(); 1631 break; 1632 1633 case PRID_IMP_PR4450: 1634 nxp_pr4450_fixup_config(); 1635 break; 1636 } 1637 } 1638 1639 static void r4k_cache_error_setup(void) 1640 { 1641 extern char __weak except_vec2_generic; 1642 extern char __weak except_vec2_sb1; 1643 1644 switch (current_cpu_type()) { 1645 case CPU_SB1: 1646 case CPU_SB1A: 1647 set_uncached_handler(0x100, &except_vec2_sb1, 0x80); 1648 break; 1649 1650 default: 1651 set_uncached_handler(0x100, &except_vec2_generic, 0x80); 1652 break; 1653 } 1654 } 1655 1656 void r4k_cache_init(void) 1657 { 1658 extern void build_clear_page(void); 1659 extern void build_copy_page(void); 1660 struct cpuinfo_mips *c = ¤t_cpu_data; 1661 1662 probe_pcache(); 1663 setup_scache(); 1664 1665 r4k_blast_dcache_page_setup(); 1666 r4k_blast_dcache_page_indexed_setup(); 1667 r4k_blast_dcache_setup(); 1668 r4k_blast_icache_page_setup(); 1669 r4k_blast_icache_page_indexed_setup(); 1670 r4k_blast_icache_setup(); 1671 r4k_blast_scache_page_setup(); 1672 r4k_blast_scache_page_indexed_setup(); 1673 r4k_blast_scache_setup(); 1674 #ifdef CONFIG_EVA 1675 r4k_blast_dcache_user_page_setup(); 1676 r4k_blast_icache_user_page_setup(); 1677 #endif 1678 1679 /* 1680 * Some MIPS32 and MIPS64 processors have physically indexed caches. 1681 * This code supports virtually indexed processors and will be 1682 * unnecessarily inefficient on physically indexed processors. 1683 */ 1684 if (c->dcache.linesz) 1685 shm_align_mask = max_t( unsigned long, 1686 c->dcache.sets * c->dcache.linesz - 1, 1687 PAGE_SIZE - 1); 1688 else 1689 shm_align_mask = PAGE_SIZE-1; 1690 1691 __flush_cache_vmap = r4k__flush_cache_vmap; 1692 __flush_cache_vunmap = r4k__flush_cache_vunmap; 1693 1694 flush_cache_all = cache_noop; 1695 __flush_cache_all = r4k___flush_cache_all; 1696 flush_cache_mm = r4k_flush_cache_mm; 1697 flush_cache_page = r4k_flush_cache_page; 1698 flush_cache_range = r4k_flush_cache_range; 1699 1700 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; 1701 1702 flush_cache_sigtramp = r4k_flush_cache_sigtramp; 1703 flush_icache_all = r4k_flush_icache_all; 1704 local_flush_data_cache_page = local_r4k_flush_data_cache_page; 1705 flush_data_cache_page = r4k_flush_data_cache_page; 1706 flush_icache_range = r4k_flush_icache_range; 1707 local_flush_icache_range = local_r4k_flush_icache_range; 1708 1709 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) 1710 if (coherentio) { 1711 _dma_cache_wback_inv = (void *)cache_noop; 1712 _dma_cache_wback = (void *)cache_noop; 1713 _dma_cache_inv = (void *)cache_noop; 1714 } else { 1715 _dma_cache_wback_inv = r4k_dma_cache_wback_inv; 1716 _dma_cache_wback = r4k_dma_cache_wback_inv; 1717 _dma_cache_inv = r4k_dma_cache_inv; 1718 } 1719 #endif 1720 1721 build_clear_page(); 1722 build_copy_page(); 1723 1724 /* 1725 * We want to run CMP kernels on core with and without coherent 1726 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether 1727 * or not to flush caches. 1728 */ 1729 local_r4k___flush_cache_all(NULL); 1730 1731 coherency_setup(); 1732 board_cache_error_setup = r4k_cache_error_setup; 1733 1734 /* 1735 * Per-CPU overrides 1736 */ 1737 switch (current_cpu_type()) { 1738 case CPU_BMIPS4350: 1739 case CPU_BMIPS4380: 1740 /* No IPI is needed because all CPUs share the same D$ */ 1741 flush_data_cache_page = r4k_blast_dcache_page; 1742 break; 1743 case CPU_BMIPS5000: 1744 /* We lose our superpowers if L2 is disabled */ 1745 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT) 1746 break; 1747 1748 /* I$ fills from D$ just by emptying the write buffers */ 1749 flush_cache_page = (void *)b5k_instruction_hazard; 1750 flush_cache_range = (void *)b5k_instruction_hazard; 1751 flush_cache_sigtramp = (void *)b5k_instruction_hazard; 1752 local_flush_data_cache_page = (void *)b5k_instruction_hazard; 1753 flush_data_cache_page = (void *)b5k_instruction_hazard; 1754 flush_icache_range = (void *)b5k_instruction_hazard; 1755 local_flush_icache_range = (void *)b5k_instruction_hazard; 1756 1757 /* Cache aliases are handled in hardware; allow HIGHMEM */ 1758 current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES; 1759 1760 /* Optimization: an L2 flush implicitly flushes the L1 */ 1761 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES; 1762 break; 1763 } 1764 } 1765 1766 static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd, 1767 void *v) 1768 { 1769 switch (cmd) { 1770 case CPU_PM_ENTER_FAILED: 1771 case CPU_PM_EXIT: 1772 coherency_setup(); 1773 break; 1774 } 1775 1776 return NOTIFY_OK; 1777 } 1778 1779 static struct notifier_block r4k_cache_pm_notifier_block = { 1780 .notifier_call = r4k_cache_pm_notifier, 1781 }; 1782 1783 int __init r4k_cache_init_pm(void) 1784 { 1785 return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block); 1786 } 1787 arch_initcall(r4k_cache_init_pm); 1788