1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) 7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 */ 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/sched.h> 13 #include <linux/mm.h> 14 #include <linux/bitops.h> 15 16 #include <asm/bcache.h> 17 #include <asm/bootinfo.h> 18 #include <asm/cache.h> 19 #include <asm/cacheops.h> 20 #include <asm/cpu.h> 21 #include <asm/cpu-features.h> 22 #include <asm/io.h> 23 #include <asm/page.h> 24 #include <asm/pgtable.h> 25 #include <asm/r4kcache.h> 26 #include <asm/system.h> 27 #include <asm/mmu_context.h> 28 #include <asm/war.h> 29 #include <asm/cacheflush.h> /* for run_uncached() */ 30 31 32 /* 33 * Special Variant of smp_call_function for use by cache functions: 34 * 35 * o No return value 36 * o collapses to normal function call on UP kernels 37 * o collapses to normal function call on systems with a single shared 38 * primary cache. 39 */ 40 static inline void r4k_on_each_cpu(void (*func) (void *info), void *info, 41 int retry, int wait) 42 { 43 preempt_disable(); 44 45 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) 46 smp_call_function(func, info, retry, wait); 47 #endif 48 func(info); 49 preempt_enable(); 50 } 51 52 /* 53 * Must die. 54 */ 55 static unsigned long icache_size __read_mostly; 56 static unsigned long dcache_size __read_mostly; 57 static unsigned long scache_size __read_mostly; 58 59 /* 60 * Dummy cache handling routines for machines without boardcaches 61 */ 62 static void cache_noop(void) {} 63 64 static struct bcache_ops no_sc_ops = { 65 .bc_enable = (void *)cache_noop, 66 .bc_disable = (void *)cache_noop, 67 .bc_wback_inv = (void *)cache_noop, 68 .bc_inv = (void *)cache_noop 69 }; 70 71 struct bcache_ops *bcops = &no_sc_ops; 72 73 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) 74 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) 75 76 #define R4600_HIT_CACHEOP_WAR_IMPL \ 77 do { \ 78 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ 79 *(volatile unsigned long *)CKSEG1; \ 80 if (R4600_V1_HIT_CACHEOP_WAR) \ 81 __asm__ __volatile__("nop;nop;nop;nop"); \ 82 } while (0) 83 84 static void (*r4k_blast_dcache_page)(unsigned long addr); 85 86 static inline void r4k_blast_dcache_page_dc32(unsigned long addr) 87 { 88 R4600_HIT_CACHEOP_WAR_IMPL; 89 blast_dcache32_page(addr); 90 } 91 92 static void __init r4k_blast_dcache_page_setup(void) 93 { 94 unsigned long dc_lsize = cpu_dcache_line_size(); 95 96 if (dc_lsize == 0) 97 r4k_blast_dcache_page = (void *)cache_noop; 98 else if (dc_lsize == 16) 99 r4k_blast_dcache_page = blast_dcache16_page; 100 else if (dc_lsize == 32) 101 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; 102 } 103 104 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); 105 106 static void __init r4k_blast_dcache_page_indexed_setup(void) 107 { 108 unsigned long dc_lsize = cpu_dcache_line_size(); 109 110 if (dc_lsize == 0) 111 r4k_blast_dcache_page_indexed = (void *)cache_noop; 112 else if (dc_lsize == 16) 113 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; 114 else if (dc_lsize == 32) 115 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; 116 } 117 118 static void (* r4k_blast_dcache)(void); 119 120 static void __init r4k_blast_dcache_setup(void) 121 { 122 unsigned long dc_lsize = cpu_dcache_line_size(); 123 124 if (dc_lsize == 0) 125 r4k_blast_dcache = (void *)cache_noop; 126 else if (dc_lsize == 16) 127 r4k_blast_dcache = blast_dcache16; 128 else if (dc_lsize == 32) 129 r4k_blast_dcache = blast_dcache32; 130 } 131 132 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ 133 #define JUMP_TO_ALIGN(order) \ 134 __asm__ __volatile__( \ 135 "b\t1f\n\t" \ 136 ".align\t" #order "\n\t" \ 137 "1:\n\t" \ 138 ) 139 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ 140 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) 141 142 static inline void blast_r4600_v1_icache32(void) 143 { 144 unsigned long flags; 145 146 local_irq_save(flags); 147 blast_icache32(); 148 local_irq_restore(flags); 149 } 150 151 static inline void tx49_blast_icache32(void) 152 { 153 unsigned long start = INDEX_BASE; 154 unsigned long end = start + current_cpu_data.icache.waysize; 155 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; 156 unsigned long ws_end = current_cpu_data.icache.ways << 157 current_cpu_data.icache.waybit; 158 unsigned long ws, addr; 159 160 CACHE32_UNROLL32_ALIGN2; 161 /* I'm in even chunk. blast odd chunks */ 162 for (ws = 0; ws < ws_end; ws += ws_inc) 163 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 164 cache32_unroll32(addr|ws,Index_Invalidate_I); 165 CACHE32_UNROLL32_ALIGN; 166 /* I'm in odd chunk. blast even chunks */ 167 for (ws = 0; ws < ws_end; ws += ws_inc) 168 for (addr = start; addr < end; addr += 0x400 * 2) 169 cache32_unroll32(addr|ws,Index_Invalidate_I); 170 } 171 172 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) 173 { 174 unsigned long flags; 175 176 local_irq_save(flags); 177 blast_icache32_page_indexed(page); 178 local_irq_restore(flags); 179 } 180 181 static inline void tx49_blast_icache32_page_indexed(unsigned long page) 182 { 183 unsigned long indexmask = current_cpu_data.icache.waysize - 1; 184 unsigned long start = INDEX_BASE + (page & indexmask); 185 unsigned long end = start + PAGE_SIZE; 186 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; 187 unsigned long ws_end = current_cpu_data.icache.ways << 188 current_cpu_data.icache.waybit; 189 unsigned long ws, addr; 190 191 CACHE32_UNROLL32_ALIGN2; 192 /* I'm in even chunk. blast odd chunks */ 193 for (ws = 0; ws < ws_end; ws += ws_inc) 194 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 195 cache32_unroll32(addr|ws,Index_Invalidate_I); 196 CACHE32_UNROLL32_ALIGN; 197 /* I'm in odd chunk. blast even chunks */ 198 for (ws = 0; ws < ws_end; ws += ws_inc) 199 for (addr = start; addr < end; addr += 0x400 * 2) 200 cache32_unroll32(addr|ws,Index_Invalidate_I); 201 } 202 203 static void (* r4k_blast_icache_page)(unsigned long addr); 204 205 static void __init r4k_blast_icache_page_setup(void) 206 { 207 unsigned long ic_lsize = cpu_icache_line_size(); 208 209 if (ic_lsize == 0) 210 r4k_blast_icache_page = (void *)cache_noop; 211 else if (ic_lsize == 16) 212 r4k_blast_icache_page = blast_icache16_page; 213 else if (ic_lsize == 32) 214 r4k_blast_icache_page = blast_icache32_page; 215 else if (ic_lsize == 64) 216 r4k_blast_icache_page = blast_icache64_page; 217 } 218 219 220 static void (* r4k_blast_icache_page_indexed)(unsigned long addr); 221 222 static void __init r4k_blast_icache_page_indexed_setup(void) 223 { 224 unsigned long ic_lsize = cpu_icache_line_size(); 225 226 if (ic_lsize == 0) 227 r4k_blast_icache_page_indexed = (void *)cache_noop; 228 else if (ic_lsize == 16) 229 r4k_blast_icache_page_indexed = blast_icache16_page_indexed; 230 else if (ic_lsize == 32) { 231 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) 232 r4k_blast_icache_page_indexed = 233 blast_icache32_r4600_v1_page_indexed; 234 else if (TX49XX_ICACHE_INDEX_INV_WAR) 235 r4k_blast_icache_page_indexed = 236 tx49_blast_icache32_page_indexed; 237 else 238 r4k_blast_icache_page_indexed = 239 blast_icache32_page_indexed; 240 } else if (ic_lsize == 64) 241 r4k_blast_icache_page_indexed = blast_icache64_page_indexed; 242 } 243 244 static void (* r4k_blast_icache)(void); 245 246 static void __init r4k_blast_icache_setup(void) 247 { 248 unsigned long ic_lsize = cpu_icache_line_size(); 249 250 if (ic_lsize == 0) 251 r4k_blast_icache = (void *)cache_noop; 252 else if (ic_lsize == 16) 253 r4k_blast_icache = blast_icache16; 254 else if (ic_lsize == 32) { 255 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) 256 r4k_blast_icache = blast_r4600_v1_icache32; 257 else if (TX49XX_ICACHE_INDEX_INV_WAR) 258 r4k_blast_icache = tx49_blast_icache32; 259 else 260 r4k_blast_icache = blast_icache32; 261 } else if (ic_lsize == 64) 262 r4k_blast_icache = blast_icache64; 263 } 264 265 static void (* r4k_blast_scache_page)(unsigned long addr); 266 267 static void __init r4k_blast_scache_page_setup(void) 268 { 269 unsigned long sc_lsize = cpu_scache_line_size(); 270 271 if (scache_size == 0) 272 r4k_blast_scache_page = (void *)cache_noop; 273 else if (sc_lsize == 16) 274 r4k_blast_scache_page = blast_scache16_page; 275 else if (sc_lsize == 32) 276 r4k_blast_scache_page = blast_scache32_page; 277 else if (sc_lsize == 64) 278 r4k_blast_scache_page = blast_scache64_page; 279 else if (sc_lsize == 128) 280 r4k_blast_scache_page = blast_scache128_page; 281 } 282 283 static void (* r4k_blast_scache_page_indexed)(unsigned long addr); 284 285 static void __init r4k_blast_scache_page_indexed_setup(void) 286 { 287 unsigned long sc_lsize = cpu_scache_line_size(); 288 289 if (scache_size == 0) 290 r4k_blast_scache_page_indexed = (void *)cache_noop; 291 else if (sc_lsize == 16) 292 r4k_blast_scache_page_indexed = blast_scache16_page_indexed; 293 else if (sc_lsize == 32) 294 r4k_blast_scache_page_indexed = blast_scache32_page_indexed; 295 else if (sc_lsize == 64) 296 r4k_blast_scache_page_indexed = blast_scache64_page_indexed; 297 else if (sc_lsize == 128) 298 r4k_blast_scache_page_indexed = blast_scache128_page_indexed; 299 } 300 301 static void (* r4k_blast_scache)(void); 302 303 static void __init r4k_blast_scache_setup(void) 304 { 305 unsigned long sc_lsize = cpu_scache_line_size(); 306 307 if (scache_size == 0) 308 r4k_blast_scache = (void *)cache_noop; 309 else if (sc_lsize == 16) 310 r4k_blast_scache = blast_scache16; 311 else if (sc_lsize == 32) 312 r4k_blast_scache = blast_scache32; 313 else if (sc_lsize == 64) 314 r4k_blast_scache = blast_scache64; 315 else if (sc_lsize == 128) 316 r4k_blast_scache = blast_scache128; 317 } 318 319 /* 320 * This is former mm's flush_cache_all() which really should be 321 * flush_cache_vunmap these days ... 322 */ 323 static inline void local_r4k_flush_cache_all(void * args) 324 { 325 r4k_blast_dcache(); 326 } 327 328 static void r4k_flush_cache_all(void) 329 { 330 if (!cpu_has_dc_aliases) 331 return; 332 333 r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1); 334 } 335 336 static inline void local_r4k___flush_cache_all(void * args) 337 { 338 #if defined(CONFIG_CPU_LOONGSON2) 339 r4k_blast_scache(); 340 return; 341 #endif 342 r4k_blast_dcache(); 343 r4k_blast_icache(); 344 345 switch (current_cpu_data.cputype) { 346 case CPU_R4000SC: 347 case CPU_R4000MC: 348 case CPU_R4400SC: 349 case CPU_R4400MC: 350 case CPU_R10000: 351 case CPU_R12000: 352 case CPU_R14000: 353 r4k_blast_scache(); 354 } 355 } 356 357 static void r4k___flush_cache_all(void) 358 { 359 r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1); 360 } 361 362 static inline void local_r4k_flush_cache_range(void * args) 363 { 364 struct vm_area_struct *vma = args; 365 366 if (!(cpu_context(smp_processor_id(), vma->vm_mm))) 367 return; 368 369 r4k_blast_dcache(); 370 } 371 372 static void r4k_flush_cache_range(struct vm_area_struct *vma, 373 unsigned long start, unsigned long end) 374 { 375 if (!cpu_has_dc_aliases) 376 return; 377 378 r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1); 379 } 380 381 static inline void local_r4k_flush_cache_mm(void * args) 382 { 383 struct mm_struct *mm = args; 384 385 if (!cpu_context(smp_processor_id(), mm)) 386 return; 387 388 /* 389 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we 390 * only flush the primary caches but R10000 and R12000 behave sane ... 391 * R4000SC and R4400SC indexed S-cache ops also invalidate primary 392 * caches, so we can bail out early. 393 */ 394 if (current_cpu_data.cputype == CPU_R4000SC || 395 current_cpu_data.cputype == CPU_R4000MC || 396 current_cpu_data.cputype == CPU_R4400SC || 397 current_cpu_data.cputype == CPU_R4400MC) { 398 r4k_blast_scache(); 399 return; 400 } 401 402 r4k_blast_dcache(); 403 } 404 405 static void r4k_flush_cache_mm(struct mm_struct *mm) 406 { 407 if (!cpu_has_dc_aliases) 408 return; 409 410 r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1); 411 } 412 413 struct flush_cache_page_args { 414 struct vm_area_struct *vma; 415 unsigned long addr; 416 unsigned long pfn; 417 }; 418 419 static inline void local_r4k_flush_cache_page(void *args) 420 { 421 struct flush_cache_page_args *fcp_args = args; 422 struct vm_area_struct *vma = fcp_args->vma; 423 unsigned long addr = fcp_args->addr; 424 unsigned long paddr = fcp_args->pfn << PAGE_SHIFT; 425 int exec = vma->vm_flags & VM_EXEC; 426 struct mm_struct *mm = vma->vm_mm; 427 pgd_t *pgdp; 428 pud_t *pudp; 429 pmd_t *pmdp; 430 pte_t *ptep; 431 432 /* 433 * If ownes no valid ASID yet, cannot possibly have gotten 434 * this page into the cache. 435 */ 436 if (cpu_context(smp_processor_id(), mm) == 0) 437 return; 438 439 addr &= PAGE_MASK; 440 pgdp = pgd_offset(mm, addr); 441 pudp = pud_offset(pgdp, addr); 442 pmdp = pmd_offset(pudp, addr); 443 ptep = pte_offset(pmdp, addr); 444 445 /* 446 * If the page isn't marked valid, the page cannot possibly be 447 * in the cache. 448 */ 449 if (!(pte_val(*ptep) & _PAGE_PRESENT)) 450 return; 451 452 /* 453 * Doing flushes for another ASID than the current one is 454 * too difficult since stupid R4k caches do a TLB translation 455 * for every cache flush operation. So we do indexed flushes 456 * in that case, which doesn't overly flush the cache too much. 457 */ 458 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { 459 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 460 r4k_blast_dcache_page(addr); 461 if (exec && !cpu_icache_snoops_remote_store) 462 r4k_blast_scache_page(addr); 463 } 464 if (exec) 465 r4k_blast_icache_page(addr); 466 467 return; 468 } 469 470 /* 471 * Do indexed flush, too much work to get the (possible) TLB refills 472 * to work correctly. 473 */ 474 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 475 r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ? 476 paddr : addr); 477 if (exec && !cpu_icache_snoops_remote_store) { 478 r4k_blast_scache_page_indexed(paddr); 479 } 480 } 481 if (exec) { 482 if (cpu_has_vtag_icache && mm == current->active_mm) { 483 int cpu = smp_processor_id(); 484 485 if (cpu_context(cpu, mm) != 0) 486 drop_mmu_context(mm, cpu); 487 } else 488 r4k_blast_icache_page_indexed(addr); 489 } 490 } 491 492 static void r4k_flush_cache_page(struct vm_area_struct *vma, 493 unsigned long addr, unsigned long pfn) 494 { 495 struct flush_cache_page_args args; 496 497 args.vma = vma; 498 args.addr = addr; 499 args.pfn = pfn; 500 501 r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1); 502 } 503 504 static inline void local_r4k_flush_data_cache_page(void * addr) 505 { 506 r4k_blast_dcache_page((unsigned long) addr); 507 } 508 509 static void r4k_flush_data_cache_page(unsigned long addr) 510 { 511 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1); 512 } 513 514 struct flush_icache_range_args { 515 unsigned long start; 516 unsigned long end; 517 }; 518 519 static inline void local_r4k_flush_icache_range(void *args) 520 { 521 struct flush_icache_range_args *fir_args = args; 522 unsigned long start = fir_args->start; 523 unsigned long end = fir_args->end; 524 525 if (!cpu_has_ic_fills_f_dc) { 526 if (end - start >= dcache_size) { 527 r4k_blast_dcache(); 528 } else { 529 R4600_HIT_CACHEOP_WAR_IMPL; 530 protected_blast_dcache_range(start, end); 531 } 532 533 if (!cpu_icache_snoops_remote_store && scache_size) { 534 if (end - start > scache_size) 535 r4k_blast_scache(); 536 else 537 protected_blast_scache_range(start, end); 538 } 539 } 540 541 if (end - start > icache_size) 542 r4k_blast_icache(); 543 else 544 protected_blast_icache_range(start, end); 545 } 546 547 static void r4k_flush_icache_range(unsigned long start, unsigned long end) 548 { 549 struct flush_icache_range_args args; 550 551 args.start = start; 552 args.end = end; 553 554 r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1); 555 instruction_hazard(); 556 } 557 558 #ifdef CONFIG_DMA_NONCOHERENT 559 560 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) 561 { 562 /* Catch bad driver code */ 563 BUG_ON(size == 0); 564 565 if (cpu_has_inclusive_pcaches) { 566 if (size >= scache_size) 567 r4k_blast_scache(); 568 else 569 blast_scache_range(addr, addr + size); 570 return; 571 } 572 573 /* 574 * Either no secondary cache or the available caches don't have the 575 * subset property so we have to flush the primary caches 576 * explicitly 577 */ 578 if (size >= dcache_size) { 579 r4k_blast_dcache(); 580 } else { 581 R4600_HIT_CACHEOP_WAR_IMPL; 582 blast_dcache_range(addr, addr + size); 583 } 584 585 bc_wback_inv(addr, size); 586 } 587 588 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) 589 { 590 /* Catch bad driver code */ 591 BUG_ON(size == 0); 592 593 if (cpu_has_inclusive_pcaches) { 594 if (size >= scache_size) 595 r4k_blast_scache(); 596 else 597 blast_scache_range(addr, addr + size); 598 return; 599 } 600 601 if (size >= dcache_size) { 602 r4k_blast_dcache(); 603 } else { 604 R4600_HIT_CACHEOP_WAR_IMPL; 605 blast_dcache_range(addr, addr + size); 606 } 607 608 bc_inv(addr, size); 609 } 610 #endif /* CONFIG_DMA_NONCOHERENT */ 611 612 /* 613 * While we're protected against bad userland addresses we don't care 614 * very much about what happens in that case. Usually a segmentation 615 * fault will dump the process later on anyway ... 616 */ 617 static void local_r4k_flush_cache_sigtramp(void * arg) 618 { 619 unsigned long ic_lsize = cpu_icache_line_size(); 620 unsigned long dc_lsize = cpu_dcache_line_size(); 621 unsigned long sc_lsize = cpu_scache_line_size(); 622 unsigned long addr = (unsigned long) arg; 623 624 R4600_HIT_CACHEOP_WAR_IMPL; 625 if (dc_lsize) 626 protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); 627 if (!cpu_icache_snoops_remote_store && scache_size) 628 protected_writeback_scache_line(addr & ~(sc_lsize - 1)); 629 if (ic_lsize) 630 protected_flush_icache_line(addr & ~(ic_lsize - 1)); 631 if (MIPS4K_ICACHE_REFILL_WAR) { 632 __asm__ __volatile__ ( 633 ".set push\n\t" 634 ".set noat\n\t" 635 ".set mips3\n\t" 636 #ifdef CONFIG_32BIT 637 "la $at,1f\n\t" 638 #endif 639 #ifdef CONFIG_64BIT 640 "dla $at,1f\n\t" 641 #endif 642 "cache %0,($at)\n\t" 643 "nop; nop; nop\n" 644 "1:\n\t" 645 ".set pop" 646 : 647 : "i" (Hit_Invalidate_I)); 648 } 649 if (MIPS_CACHE_SYNC_WAR) 650 __asm__ __volatile__ ("sync"); 651 } 652 653 static void r4k_flush_cache_sigtramp(unsigned long addr) 654 { 655 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1); 656 } 657 658 static void r4k_flush_icache_all(void) 659 { 660 if (cpu_has_vtag_icache) 661 r4k_blast_icache(); 662 } 663 664 static inline void rm7k_erratum31(void) 665 { 666 const unsigned long ic_lsize = 32; 667 unsigned long addr; 668 669 /* RM7000 erratum #31. The icache is screwed at startup. */ 670 write_c0_taglo(0); 671 write_c0_taghi(0); 672 673 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { 674 __asm__ __volatile__ ( 675 ".set push\n\t" 676 ".set noreorder\n\t" 677 ".set mips3\n\t" 678 "cache\t%1, 0(%0)\n\t" 679 "cache\t%1, 0x1000(%0)\n\t" 680 "cache\t%1, 0x2000(%0)\n\t" 681 "cache\t%1, 0x3000(%0)\n\t" 682 "cache\t%2, 0(%0)\n\t" 683 "cache\t%2, 0x1000(%0)\n\t" 684 "cache\t%2, 0x2000(%0)\n\t" 685 "cache\t%2, 0x3000(%0)\n\t" 686 "cache\t%1, 0(%0)\n\t" 687 "cache\t%1, 0x1000(%0)\n\t" 688 "cache\t%1, 0x2000(%0)\n\t" 689 "cache\t%1, 0x3000(%0)\n\t" 690 ".set pop\n" 691 : 692 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); 693 } 694 } 695 696 static char *way_string[] __initdata = { NULL, "direct mapped", "2-way", 697 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" 698 }; 699 700 static void __init probe_pcache(void) 701 { 702 struct cpuinfo_mips *c = ¤t_cpu_data; 703 unsigned int config = read_c0_config(); 704 unsigned int prid = read_c0_prid(); 705 unsigned long config1; 706 unsigned int lsize; 707 708 switch (c->cputype) { 709 case CPU_R4600: /* QED style two way caches? */ 710 case CPU_R4700: 711 case CPU_R5000: 712 case CPU_NEVADA: 713 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 714 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 715 c->icache.ways = 2; 716 c->icache.waybit = __ffs(icache_size/2); 717 718 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 719 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 720 c->dcache.ways = 2; 721 c->dcache.waybit= __ffs(dcache_size/2); 722 723 c->options |= MIPS_CPU_CACHE_CDEX_P; 724 break; 725 726 case CPU_R5432: 727 case CPU_R5500: 728 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 729 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 730 c->icache.ways = 2; 731 c->icache.waybit= 0; 732 733 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 734 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 735 c->dcache.ways = 2; 736 c->dcache.waybit = 0; 737 738 c->options |= MIPS_CPU_CACHE_CDEX_P; 739 break; 740 741 case CPU_TX49XX: 742 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 743 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 744 c->icache.ways = 4; 745 c->icache.waybit= 0; 746 747 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 748 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 749 c->dcache.ways = 4; 750 c->dcache.waybit = 0; 751 752 c->options |= MIPS_CPU_CACHE_CDEX_P; 753 c->options |= MIPS_CPU_PREFETCH; 754 break; 755 756 case CPU_R4000PC: 757 case CPU_R4000SC: 758 case CPU_R4000MC: 759 case CPU_R4400PC: 760 case CPU_R4400SC: 761 case CPU_R4400MC: 762 case CPU_R4300: 763 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 764 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 765 c->icache.ways = 1; 766 c->icache.waybit = 0; /* doesn't matter */ 767 768 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 769 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 770 c->dcache.ways = 1; 771 c->dcache.waybit = 0; /* does not matter */ 772 773 c->options |= MIPS_CPU_CACHE_CDEX_P; 774 break; 775 776 case CPU_R10000: 777 case CPU_R12000: 778 case CPU_R14000: 779 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); 780 c->icache.linesz = 64; 781 c->icache.ways = 2; 782 c->icache.waybit = 0; 783 784 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); 785 c->dcache.linesz = 32; 786 c->dcache.ways = 2; 787 c->dcache.waybit = 0; 788 789 c->options |= MIPS_CPU_PREFETCH; 790 break; 791 792 case CPU_VR4133: 793 write_c0_config(config & ~VR41_CONF_P4K); 794 case CPU_VR4131: 795 /* Workaround for cache instruction bug of VR4131 */ 796 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || 797 c->processor_id == 0x0c82U) { 798 config |= 0x00400000U; 799 if (c->processor_id == 0x0c80U) 800 config |= VR41_CONF_BP; 801 write_c0_config(config); 802 } else 803 c->options |= MIPS_CPU_CACHE_CDEX_P; 804 805 icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); 806 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 807 c->icache.ways = 2; 808 c->icache.waybit = __ffs(icache_size/2); 809 810 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); 811 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 812 c->dcache.ways = 2; 813 c->dcache.waybit = __ffs(dcache_size/2); 814 break; 815 816 case CPU_VR41XX: 817 case CPU_VR4111: 818 case CPU_VR4121: 819 case CPU_VR4122: 820 case CPU_VR4181: 821 case CPU_VR4181A: 822 icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); 823 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 824 c->icache.ways = 1; 825 c->icache.waybit = 0; /* doesn't matter */ 826 827 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); 828 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 829 c->dcache.ways = 1; 830 c->dcache.waybit = 0; /* does not matter */ 831 832 c->options |= MIPS_CPU_CACHE_CDEX_P; 833 break; 834 835 case CPU_RM7000: 836 rm7k_erratum31(); 837 838 case CPU_RM9000: 839 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 840 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 841 c->icache.ways = 4; 842 c->icache.waybit = __ffs(icache_size / c->icache.ways); 843 844 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 845 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 846 c->dcache.ways = 4; 847 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); 848 849 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR) 850 c->options |= MIPS_CPU_CACHE_CDEX_P; 851 #endif 852 c->options |= MIPS_CPU_PREFETCH; 853 break; 854 855 case CPU_LOONGSON2: 856 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 857 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 858 if (prid & 0x3) 859 c->icache.ways = 4; 860 else 861 c->icache.ways = 2; 862 c->icache.waybit = 0; 863 864 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 865 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 866 if (prid & 0x3) 867 c->dcache.ways = 4; 868 else 869 c->dcache.ways = 2; 870 c->dcache.waybit = 0; 871 break; 872 873 default: 874 if (!(config & MIPS_CONF_M)) 875 panic("Don't know how to probe P-caches on this cpu."); 876 877 /* 878 * So we seem to be a MIPS32 or MIPS64 CPU 879 * So let's probe the I-cache ... 880 */ 881 config1 = read_c0_config1(); 882 883 if ((lsize = ((config1 >> 19) & 7))) 884 c->icache.linesz = 2 << lsize; 885 else 886 c->icache.linesz = lsize; 887 c->icache.sets = 64 << ((config1 >> 22) & 7); 888 c->icache.ways = 1 + ((config1 >> 16) & 7); 889 890 icache_size = c->icache.sets * 891 c->icache.ways * 892 c->icache.linesz; 893 c->icache.waybit = __ffs(icache_size/c->icache.ways); 894 895 if (config & 0x8) /* VI bit */ 896 c->icache.flags |= MIPS_CACHE_VTAG; 897 898 /* 899 * Now probe the MIPS32 / MIPS64 data cache. 900 */ 901 c->dcache.flags = 0; 902 903 if ((lsize = ((config1 >> 10) & 7))) 904 c->dcache.linesz = 2 << lsize; 905 else 906 c->dcache.linesz= lsize; 907 c->dcache.sets = 64 << ((config1 >> 13) & 7); 908 c->dcache.ways = 1 + ((config1 >> 7) & 7); 909 910 dcache_size = c->dcache.sets * 911 c->dcache.ways * 912 c->dcache.linesz; 913 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); 914 915 c->options |= MIPS_CPU_PREFETCH; 916 break; 917 } 918 919 /* 920 * Processor configuration sanity check for the R4000SC erratum 921 * #5. With page sizes larger than 32kB there is no possibility 922 * to get a VCE exception anymore so we don't care about this 923 * misconfiguration. The case is rather theoretical anyway; 924 * presumably no vendor is shipping his hardware in the "bad" 925 * configuration. 926 */ 927 if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 && 928 !(config & CONF_SC) && c->icache.linesz != 16 && 929 PAGE_SIZE <= 0x8000) 930 panic("Improper R4000SC processor configuration detected"); 931 932 /* compute a couple of other cache variables */ 933 c->icache.waysize = icache_size / c->icache.ways; 934 c->dcache.waysize = dcache_size / c->dcache.ways; 935 936 c->icache.sets = c->icache.linesz ? 937 icache_size / (c->icache.linesz * c->icache.ways) : 0; 938 c->dcache.sets = c->dcache.linesz ? 939 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; 940 941 /* 942 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB 943 * 2-way virtually indexed so normally would suffer from aliases. So 944 * normally they'd suffer from aliases but magic in the hardware deals 945 * with that for us so we don't need to take care ourselves. 946 */ 947 switch (c->cputype) { 948 case CPU_20KC: 949 case CPU_25KF: 950 c->dcache.flags |= MIPS_CACHE_PINDEX; 951 case CPU_R10000: 952 case CPU_R12000: 953 case CPU_R14000: 954 case CPU_SB1: 955 break; 956 case CPU_24K: 957 case CPU_34K: 958 case CPU_74K: 959 if ((read_c0_config7() & (1 << 16))) { 960 /* effectively physically indexed dcache, 961 thus no virtual aliases. */ 962 c->dcache.flags |= MIPS_CACHE_PINDEX; 963 break; 964 } 965 default: 966 if (c->dcache.waysize > PAGE_SIZE) 967 c->dcache.flags |= MIPS_CACHE_ALIASES; 968 } 969 970 switch (c->cputype) { 971 case CPU_20KC: 972 /* 973 * Some older 20Kc chips doesn't have the 'VI' bit in 974 * the config register. 975 */ 976 c->icache.flags |= MIPS_CACHE_VTAG; 977 break; 978 979 case CPU_AU1000: 980 case CPU_AU1500: 981 case CPU_AU1100: 982 case CPU_AU1550: 983 case CPU_AU1200: 984 c->icache.flags |= MIPS_CACHE_IC_F_DC; 985 break; 986 } 987 988 #ifdef CONFIG_CPU_LOONGSON2 989 /* 990 * LOONGSON2 has 4 way icache, but when using indexed cache op, 991 * one op will act on all 4 ways 992 */ 993 c->icache.ways = 1; 994 #endif 995 996 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", 997 icache_size >> 10, 998 cpu_has_vtag_icache ? "virtually tagged" : "physically tagged", 999 way_string[c->icache.ways], c->icache.linesz); 1000 1001 printk("Primary data cache %ldkB, %s, linesize %d bytes.\n", 1002 dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz); 1003 } 1004 1005 /* 1006 * If you even _breathe_ on this function, look at the gcc output and make sure 1007 * it does not pop things on and off the stack for the cache sizing loop that 1008 * executes in KSEG1 space or else you will crash and burn badly. You have 1009 * been warned. 1010 */ 1011 static int __init probe_scache(void) 1012 { 1013 extern unsigned long stext; 1014 unsigned long flags, addr, begin, end, pow2; 1015 unsigned int config = read_c0_config(); 1016 struct cpuinfo_mips *c = ¤t_cpu_data; 1017 int tmp; 1018 1019 if (config & CONF_SC) 1020 return 0; 1021 1022 begin = (unsigned long) &stext; 1023 begin &= ~((4 * 1024 * 1024) - 1); 1024 end = begin + (4 * 1024 * 1024); 1025 1026 /* 1027 * This is such a bitch, you'd think they would make it easy to do 1028 * this. Away you daemons of stupidity! 1029 */ 1030 local_irq_save(flags); 1031 1032 /* Fill each size-multiple cache line with a valid tag. */ 1033 pow2 = (64 * 1024); 1034 for (addr = begin; addr < end; addr = (begin + pow2)) { 1035 unsigned long *p = (unsigned long *) addr; 1036 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ 1037 pow2 <<= 1; 1038 } 1039 1040 /* Load first line with zero (therefore invalid) tag. */ 1041 write_c0_taglo(0); 1042 write_c0_taghi(0); 1043 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ 1044 cache_op(Index_Store_Tag_I, begin); 1045 cache_op(Index_Store_Tag_D, begin); 1046 cache_op(Index_Store_Tag_SD, begin); 1047 1048 /* Now search for the wrap around point. */ 1049 pow2 = (128 * 1024); 1050 tmp = 0; 1051 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { 1052 cache_op(Index_Load_Tag_SD, addr); 1053 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ 1054 if (!read_c0_taglo()) 1055 break; 1056 pow2 <<= 1; 1057 } 1058 local_irq_restore(flags); 1059 addr -= begin; 1060 1061 scache_size = addr; 1062 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); 1063 c->scache.ways = 1; 1064 c->dcache.waybit = 0; /* does not matter */ 1065 1066 return 1; 1067 } 1068 1069 #if defined(CONFIG_CPU_LOONGSON2) 1070 static void __init loongson2_sc_init(void) 1071 { 1072 struct cpuinfo_mips *c = ¤t_cpu_data; 1073 1074 scache_size = 512*1024; 1075 c->scache.linesz = 32; 1076 c->scache.ways = 4; 1077 c->scache.waybit = 0; 1078 c->scache.waysize = scache_size / (c->scache.ways); 1079 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 1080 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1081 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1082 1083 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1084 } 1085 #endif 1086 1087 extern int r5k_sc_init(void); 1088 extern int rm7k_sc_init(void); 1089 extern int mips_sc_init(void); 1090 1091 static void __init setup_scache(void) 1092 { 1093 struct cpuinfo_mips *c = ¤t_cpu_data; 1094 unsigned int config = read_c0_config(); 1095 int sc_present = 0; 1096 1097 /* 1098 * Do the probing thing on R4000SC and R4400SC processors. Other 1099 * processors don't have a S-cache that would be relevant to the 1100 * Linux memory managment. 1101 */ 1102 switch (c->cputype) { 1103 case CPU_R4000SC: 1104 case CPU_R4000MC: 1105 case CPU_R4400SC: 1106 case CPU_R4400MC: 1107 sc_present = run_uncached(probe_scache); 1108 if (sc_present) 1109 c->options |= MIPS_CPU_CACHE_CDEX_S; 1110 break; 1111 1112 case CPU_R10000: 1113 case CPU_R12000: 1114 case CPU_R14000: 1115 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); 1116 c->scache.linesz = 64 << ((config >> 13) & 1); 1117 c->scache.ways = 2; 1118 c->scache.waybit= 0; 1119 sc_present = 1; 1120 break; 1121 1122 case CPU_R5000: 1123 case CPU_NEVADA: 1124 #ifdef CONFIG_R5000_CPU_SCACHE 1125 r5k_sc_init(); 1126 #endif 1127 return; 1128 1129 case CPU_RM7000: 1130 case CPU_RM9000: 1131 #ifdef CONFIG_RM7000_CPU_SCACHE 1132 rm7k_sc_init(); 1133 #endif 1134 return; 1135 1136 #if defined(CONFIG_CPU_LOONGSON2) 1137 case CPU_LOONGSON2: 1138 loongson2_sc_init(); 1139 return; 1140 #endif 1141 1142 default: 1143 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 1144 c->isa_level == MIPS_CPU_ISA_M32R2 || 1145 c->isa_level == MIPS_CPU_ISA_M64R1 || 1146 c->isa_level == MIPS_CPU_ISA_M64R2) { 1147 #ifdef CONFIG_MIPS_CPU_SCACHE 1148 if (mips_sc_init ()) { 1149 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; 1150 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", 1151 scache_size >> 10, 1152 way_string[c->scache.ways], c->scache.linesz); 1153 } 1154 #else 1155 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) 1156 panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); 1157 #endif 1158 return; 1159 } 1160 sc_present = 0; 1161 } 1162 1163 if (!sc_present) 1164 return; 1165 1166 /* compute a couple of other cache variables */ 1167 c->scache.waysize = scache_size / c->scache.ways; 1168 1169 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 1170 1171 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1172 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1173 1174 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1175 } 1176 1177 void au1x00_fixup_config_od(void) 1178 { 1179 /* 1180 * c0_config.od (bit 19) was write only (and read as 0) 1181 * on the early revisions of Alchemy SOCs. It disables the bus 1182 * transaction overlapping and needs to be set to fix various errata. 1183 */ 1184 switch (read_c0_prid()) { 1185 case 0x00030100: /* Au1000 DA */ 1186 case 0x00030201: /* Au1000 HA */ 1187 case 0x00030202: /* Au1000 HB */ 1188 case 0x01030200: /* Au1500 AB */ 1189 /* 1190 * Au1100 errata actually keeps silence about this bit, so we set it 1191 * just in case for those revisions that require it to be set according 1192 * to arch/mips/au1000/common/cputable.c 1193 */ 1194 case 0x02030200: /* Au1100 AB */ 1195 case 0x02030201: /* Au1100 BA */ 1196 case 0x02030202: /* Au1100 BC */ 1197 set_c0_config(1 << 19); 1198 break; 1199 } 1200 } 1201 1202 static void __init coherency_setup(void) 1203 { 1204 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); 1205 1206 /* 1207 * c0_status.cu=0 specifies that updates by the sc instruction use 1208 * the coherency mode specified by the TLB; 1 means cachable 1209 * coherent update on write will be used. Not all processors have 1210 * this bit and; some wire it to zero, others like Toshiba had the 1211 * silly idea of putting something else there ... 1212 */ 1213 switch (current_cpu_data.cputype) { 1214 case CPU_R4000PC: 1215 case CPU_R4000SC: 1216 case CPU_R4000MC: 1217 case CPU_R4400PC: 1218 case CPU_R4400SC: 1219 case CPU_R4400MC: 1220 clear_c0_config(CONF_CU); 1221 break; 1222 /* 1223 * We need to catch the early Alchemy SOCs with 1224 * the write-only co_config.od bit and set it back to one... 1225 */ 1226 case CPU_AU1000: /* rev. DA, HA, HB */ 1227 case CPU_AU1100: /* rev. AB, BA, BC ?? */ 1228 case CPU_AU1500: /* rev. AB */ 1229 au1x00_fixup_config_od(); 1230 break; 1231 } 1232 } 1233 1234 void __init r4k_cache_init(void) 1235 { 1236 extern void build_clear_page(void); 1237 extern void build_copy_page(void); 1238 extern char except_vec2_generic; 1239 struct cpuinfo_mips *c = ¤t_cpu_data; 1240 1241 /* Default cache error handler for R4000 and R5000 family */ 1242 set_uncached_handler (0x100, &except_vec2_generic, 0x80); 1243 1244 probe_pcache(); 1245 setup_scache(); 1246 1247 r4k_blast_dcache_page_setup(); 1248 r4k_blast_dcache_page_indexed_setup(); 1249 r4k_blast_dcache_setup(); 1250 r4k_blast_icache_page_setup(); 1251 r4k_blast_icache_page_indexed_setup(); 1252 r4k_blast_icache_setup(); 1253 r4k_blast_scache_page_setup(); 1254 r4k_blast_scache_page_indexed_setup(); 1255 r4k_blast_scache_setup(); 1256 1257 /* 1258 * Some MIPS32 and MIPS64 processors have physically indexed caches. 1259 * This code supports virtually indexed processors and will be 1260 * unnecessarily inefficient on physically indexed processors. 1261 */ 1262 if (c->dcache.linesz) 1263 shm_align_mask = max_t( unsigned long, 1264 c->dcache.sets * c->dcache.linesz - 1, 1265 PAGE_SIZE - 1); 1266 else 1267 shm_align_mask = PAGE_SIZE-1; 1268 flush_cache_all = r4k_flush_cache_all; 1269 __flush_cache_all = r4k___flush_cache_all; 1270 flush_cache_mm = r4k_flush_cache_mm; 1271 flush_cache_page = r4k_flush_cache_page; 1272 flush_cache_range = r4k_flush_cache_range; 1273 1274 flush_cache_sigtramp = r4k_flush_cache_sigtramp; 1275 flush_icache_all = r4k_flush_icache_all; 1276 local_flush_data_cache_page = local_r4k_flush_data_cache_page; 1277 flush_data_cache_page = r4k_flush_data_cache_page; 1278 flush_icache_range = r4k_flush_icache_range; 1279 1280 #ifdef CONFIG_DMA_NONCOHERENT 1281 _dma_cache_wback_inv = r4k_dma_cache_wback_inv; 1282 _dma_cache_wback = r4k_dma_cache_wback_inv; 1283 _dma_cache_inv = r4k_dma_cache_inv; 1284 #endif 1285 1286 build_clear_page(); 1287 build_copy_page(); 1288 local_r4k___flush_cache_all(NULL); 1289 coherency_setup(); 1290 } 1291