1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 */ 10 #include <linux/cpu_pm.h> 11 #include <linux/hardirq.h> 12 #include <linux/init.h> 13 #include <linux/highmem.h> 14 #include <linux/kernel.h> 15 #include <linux/linkage.h> 16 #include <linux/preempt.h> 17 #include <linux/sched.h> 18 #include <linux/smp.h> 19 #include <linux/mm.h> 20 #include <linux/export.h> 21 #include <linux/bitops.h> 22 #include <linux/dma-map-ops.h> /* for dma_default_coherent */ 23 24 #include <asm/bcache.h> 25 #include <asm/bootinfo.h> 26 #include <asm/cache.h> 27 #include <asm/cacheops.h> 28 #include <asm/cpu.h> 29 #include <asm/cpu-features.h> 30 #include <asm/cpu-type.h> 31 #include <asm/io.h> 32 #include <asm/page.h> 33 #include <asm/r4kcache.h> 34 #include <asm/sections.h> 35 #include <asm/mmu_context.h> 36 #include <asm/cacheflush.h> /* for run_uncached() */ 37 #include <asm/traps.h> 38 #include <asm/mips-cps.h> 39 40 /* 41 * Bits describing what cache ops an SMP callback function may perform. 42 * 43 * R4K_HIT - Virtual user or kernel address based cache operations. The 44 * active_mm must be checked before using user addresses, falling 45 * back to kmap. 46 * R4K_INDEX - Index based cache operations. 47 */ 48 49 #define R4K_HIT BIT(0) 50 #define R4K_INDEX BIT(1) 51 52 /** 53 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core. 54 * @type: Type of cache operations (R4K_HIT or R4K_INDEX). 55 * 56 * Decides whether a cache op needs to be performed on every core in the system. 57 * This may change depending on the @type of cache operation, as well as the set 58 * of online CPUs, so preemption should be disabled by the caller to prevent CPU 59 * hotplug from changing the result. 60 * 61 * Returns: 1 if the cache operation @type should be done on every core in 62 * the system. 63 * 0 if the cache operation @type is globalized and only needs to 64 * be performed on a simple CPU. 65 */ 66 static inline bool r4k_op_needs_ipi(unsigned int type) 67 { 68 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */ 69 if (type == R4K_HIT && mips_cm_present()) 70 return false; 71 72 /* 73 * Hardware doesn't globalize the required cache ops, so SMP calls may 74 * be needed, but only if there are foreign CPUs (non-siblings with 75 * separate caches). 76 */ 77 /* cpu_foreign_map[] undeclared when !CONFIG_SMP */ 78 #ifdef CONFIG_SMP 79 return !cpumask_empty(&cpu_foreign_map[0]); 80 #else 81 return false; 82 #endif 83 } 84 85 /* 86 * Special Variant of smp_call_function for use by cache functions: 87 * 88 * o No return value 89 * o collapses to normal function call on UP kernels 90 * o collapses to normal function call on systems with a single shared 91 * primary cache. 92 * o doesn't disable interrupts on the local CPU 93 */ 94 static inline void r4k_on_each_cpu(unsigned int type, 95 void (*func)(void *info), void *info) 96 { 97 preempt_disable(); 98 if (r4k_op_needs_ipi(type)) 99 smp_call_function_many(&cpu_foreign_map[smp_processor_id()], 100 func, info, 1); 101 func(info); 102 preempt_enable(); 103 } 104 105 /* 106 * Must die. 107 */ 108 static unsigned long icache_size __read_mostly; 109 static unsigned long dcache_size __read_mostly; 110 static unsigned long vcache_size __read_mostly; 111 static unsigned long scache_size __read_mostly; 112 113 /* 114 * Dummy cache handling routines for machines without boardcaches 115 */ 116 static void cache_noop(void) {} 117 118 static struct bcache_ops no_sc_ops = { 119 .bc_enable = (void *)cache_noop, 120 .bc_disable = (void *)cache_noop, 121 .bc_wback_inv = (void *)cache_noop, 122 .bc_inv = (void *)cache_noop 123 }; 124 125 struct bcache_ops *bcops = &no_sc_ops; 126 127 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) 128 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) 129 130 #define R4600_HIT_CACHEOP_WAR_IMPL \ 131 do { \ 132 if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && \ 133 cpu_is_r4600_v2_x()) \ 134 *(volatile unsigned long *)CKSEG1; \ 135 if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP)) \ 136 __asm__ __volatile__("nop;nop;nop;nop"); \ 137 } while (0) 138 139 static void (*r4k_blast_dcache_page)(unsigned long addr); 140 141 static inline void r4k_blast_dcache_page_dc32(unsigned long addr) 142 { 143 R4600_HIT_CACHEOP_WAR_IMPL; 144 blast_dcache32_page(addr); 145 } 146 147 static inline void r4k_blast_dcache_page_dc64(unsigned long addr) 148 { 149 blast_dcache64_page(addr); 150 } 151 152 static inline void r4k_blast_dcache_page_dc128(unsigned long addr) 153 { 154 blast_dcache128_page(addr); 155 } 156 157 static void r4k_blast_dcache_page_setup(void) 158 { 159 unsigned long dc_lsize = cpu_dcache_line_size(); 160 161 switch (dc_lsize) { 162 case 0: 163 r4k_blast_dcache_page = (void *)cache_noop; 164 break; 165 case 16: 166 r4k_blast_dcache_page = blast_dcache16_page; 167 break; 168 case 32: 169 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; 170 break; 171 case 64: 172 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; 173 break; 174 case 128: 175 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128; 176 break; 177 default: 178 break; 179 } 180 } 181 182 #ifndef CONFIG_EVA 183 #define r4k_blast_dcache_user_page r4k_blast_dcache_page 184 #else 185 186 static void (*r4k_blast_dcache_user_page)(unsigned long addr); 187 188 static void r4k_blast_dcache_user_page_setup(void) 189 { 190 unsigned long dc_lsize = cpu_dcache_line_size(); 191 192 if (dc_lsize == 0) 193 r4k_blast_dcache_user_page = (void *)cache_noop; 194 else if (dc_lsize == 16) 195 r4k_blast_dcache_user_page = blast_dcache16_user_page; 196 else if (dc_lsize == 32) 197 r4k_blast_dcache_user_page = blast_dcache32_user_page; 198 else if (dc_lsize == 64) 199 r4k_blast_dcache_user_page = blast_dcache64_user_page; 200 } 201 202 #endif 203 204 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); 205 206 static void r4k_blast_dcache_page_indexed_setup(void) 207 { 208 unsigned long dc_lsize = cpu_dcache_line_size(); 209 210 if (dc_lsize == 0) 211 r4k_blast_dcache_page_indexed = (void *)cache_noop; 212 else if (dc_lsize == 16) 213 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; 214 else if (dc_lsize == 32) 215 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; 216 else if (dc_lsize == 64) 217 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; 218 else if (dc_lsize == 128) 219 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed; 220 } 221 222 void (* r4k_blast_dcache)(void); 223 EXPORT_SYMBOL(r4k_blast_dcache); 224 225 static void r4k_blast_dcache_setup(void) 226 { 227 unsigned long dc_lsize = cpu_dcache_line_size(); 228 229 if (dc_lsize == 0) 230 r4k_blast_dcache = (void *)cache_noop; 231 else if (dc_lsize == 16) 232 r4k_blast_dcache = blast_dcache16; 233 else if (dc_lsize == 32) 234 r4k_blast_dcache = blast_dcache32; 235 else if (dc_lsize == 64) 236 r4k_blast_dcache = blast_dcache64; 237 else if (dc_lsize == 128) 238 r4k_blast_dcache = blast_dcache128; 239 } 240 241 /* force code alignment (used for CONFIG_WAR_TX49XX_ICACHE_INDEX_INV) */ 242 #define JUMP_TO_ALIGN(order) \ 243 __asm__ __volatile__( \ 244 "b\t1f\n\t" \ 245 ".align\t" #order "\n\t" \ 246 "1:\n\t" \ 247 ) 248 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ 249 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) 250 251 static inline void blast_r4600_v1_icache32(void) 252 { 253 unsigned long flags; 254 255 local_irq_save(flags); 256 blast_icache32(); 257 local_irq_restore(flags); 258 } 259 260 static inline void tx49_blast_icache32(void) 261 { 262 unsigned long start = INDEX_BASE; 263 unsigned long end = start + current_cpu_data.icache.waysize; 264 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; 265 unsigned long ws_end = current_cpu_data.icache.ways << 266 current_cpu_data.icache.waybit; 267 unsigned long ws, addr; 268 269 CACHE32_UNROLL32_ALIGN2; 270 /* I'm in even chunk. blast odd chunks */ 271 for (ws = 0; ws < ws_end; ws += ws_inc) 272 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 273 cache_unroll(32, kernel_cache, Index_Invalidate_I, 274 addr | ws, 32); 275 CACHE32_UNROLL32_ALIGN; 276 /* I'm in odd chunk. blast even chunks */ 277 for (ws = 0; ws < ws_end; ws += ws_inc) 278 for (addr = start; addr < end; addr += 0x400 * 2) 279 cache_unroll(32, kernel_cache, Index_Invalidate_I, 280 addr | ws, 32); 281 } 282 283 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) 284 { 285 unsigned long flags; 286 287 local_irq_save(flags); 288 blast_icache32_page_indexed(page); 289 local_irq_restore(flags); 290 } 291 292 static inline void tx49_blast_icache32_page_indexed(unsigned long page) 293 { 294 unsigned long indexmask = current_cpu_data.icache.waysize - 1; 295 unsigned long start = INDEX_BASE + (page & indexmask); 296 unsigned long end = start + PAGE_SIZE; 297 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; 298 unsigned long ws_end = current_cpu_data.icache.ways << 299 current_cpu_data.icache.waybit; 300 unsigned long ws, addr; 301 302 CACHE32_UNROLL32_ALIGN2; 303 /* I'm in even chunk. blast odd chunks */ 304 for (ws = 0; ws < ws_end; ws += ws_inc) 305 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 306 cache_unroll(32, kernel_cache, Index_Invalidate_I, 307 addr | ws, 32); 308 CACHE32_UNROLL32_ALIGN; 309 /* I'm in odd chunk. blast even chunks */ 310 for (ws = 0; ws < ws_end; ws += ws_inc) 311 for (addr = start; addr < end; addr += 0x400 * 2) 312 cache_unroll(32, kernel_cache, Index_Invalidate_I, 313 addr | ws, 32); 314 } 315 316 static void (* r4k_blast_icache_page)(unsigned long addr); 317 318 static void r4k_blast_icache_page_setup(void) 319 { 320 unsigned long ic_lsize = cpu_icache_line_size(); 321 322 if (ic_lsize == 0) 323 r4k_blast_icache_page = (void *)cache_noop; 324 else if (ic_lsize == 16) 325 r4k_blast_icache_page = blast_icache16_page; 326 else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2EF) 327 r4k_blast_icache_page = loongson2_blast_icache32_page; 328 else if (ic_lsize == 32) 329 r4k_blast_icache_page = blast_icache32_page; 330 else if (ic_lsize == 64) 331 r4k_blast_icache_page = blast_icache64_page; 332 else if (ic_lsize == 128) 333 r4k_blast_icache_page = blast_icache128_page; 334 } 335 336 #ifndef CONFIG_EVA 337 #define r4k_blast_icache_user_page r4k_blast_icache_page 338 #else 339 340 static void (*r4k_blast_icache_user_page)(unsigned long addr); 341 342 static void r4k_blast_icache_user_page_setup(void) 343 { 344 unsigned long ic_lsize = cpu_icache_line_size(); 345 346 if (ic_lsize == 0) 347 r4k_blast_icache_user_page = (void *)cache_noop; 348 else if (ic_lsize == 16) 349 r4k_blast_icache_user_page = blast_icache16_user_page; 350 else if (ic_lsize == 32) 351 r4k_blast_icache_user_page = blast_icache32_user_page; 352 else if (ic_lsize == 64) 353 r4k_blast_icache_user_page = blast_icache64_user_page; 354 } 355 356 #endif 357 358 static void (* r4k_blast_icache_page_indexed)(unsigned long addr); 359 360 static void r4k_blast_icache_page_indexed_setup(void) 361 { 362 unsigned long ic_lsize = cpu_icache_line_size(); 363 364 if (ic_lsize == 0) 365 r4k_blast_icache_page_indexed = (void *)cache_noop; 366 else if (ic_lsize == 16) 367 r4k_blast_icache_page_indexed = blast_icache16_page_indexed; 368 else if (ic_lsize == 32) { 369 if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) && 370 cpu_is_r4600_v1_x()) 371 r4k_blast_icache_page_indexed = 372 blast_icache32_r4600_v1_page_indexed; 373 else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV)) 374 r4k_blast_icache_page_indexed = 375 tx49_blast_icache32_page_indexed; 376 else if (current_cpu_type() == CPU_LOONGSON2EF) 377 r4k_blast_icache_page_indexed = 378 loongson2_blast_icache32_page_indexed; 379 else 380 r4k_blast_icache_page_indexed = 381 blast_icache32_page_indexed; 382 } else if (ic_lsize == 64) 383 r4k_blast_icache_page_indexed = blast_icache64_page_indexed; 384 } 385 386 void (* r4k_blast_icache)(void); 387 EXPORT_SYMBOL(r4k_blast_icache); 388 389 static void r4k_blast_icache_setup(void) 390 { 391 unsigned long ic_lsize = cpu_icache_line_size(); 392 393 if (ic_lsize == 0) 394 r4k_blast_icache = (void *)cache_noop; 395 else if (ic_lsize == 16) 396 r4k_blast_icache = blast_icache16; 397 else if (ic_lsize == 32) { 398 if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) && 399 cpu_is_r4600_v1_x()) 400 r4k_blast_icache = blast_r4600_v1_icache32; 401 else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV)) 402 r4k_blast_icache = tx49_blast_icache32; 403 else if (current_cpu_type() == CPU_LOONGSON2EF) 404 r4k_blast_icache = loongson2_blast_icache32; 405 else 406 r4k_blast_icache = blast_icache32; 407 } else if (ic_lsize == 64) 408 r4k_blast_icache = blast_icache64; 409 else if (ic_lsize == 128) 410 r4k_blast_icache = blast_icache128; 411 } 412 413 static void (* r4k_blast_scache_page)(unsigned long addr); 414 415 static void r4k_blast_scache_page_setup(void) 416 { 417 unsigned long sc_lsize = cpu_scache_line_size(); 418 419 if (scache_size == 0) 420 r4k_blast_scache_page = (void *)cache_noop; 421 else if (sc_lsize == 16) 422 r4k_blast_scache_page = blast_scache16_page; 423 else if (sc_lsize == 32) 424 r4k_blast_scache_page = blast_scache32_page; 425 else if (sc_lsize == 64) 426 r4k_blast_scache_page = blast_scache64_page; 427 else if (sc_lsize == 128) 428 r4k_blast_scache_page = blast_scache128_page; 429 } 430 431 static void (* r4k_blast_scache_page_indexed)(unsigned long addr); 432 433 static void r4k_blast_scache_page_indexed_setup(void) 434 { 435 unsigned long sc_lsize = cpu_scache_line_size(); 436 437 if (scache_size == 0) 438 r4k_blast_scache_page_indexed = (void *)cache_noop; 439 else if (sc_lsize == 16) 440 r4k_blast_scache_page_indexed = blast_scache16_page_indexed; 441 else if (sc_lsize == 32) 442 r4k_blast_scache_page_indexed = blast_scache32_page_indexed; 443 else if (sc_lsize == 64) 444 r4k_blast_scache_page_indexed = blast_scache64_page_indexed; 445 else if (sc_lsize == 128) 446 r4k_blast_scache_page_indexed = blast_scache128_page_indexed; 447 } 448 449 static void (* r4k_blast_scache)(void); 450 451 static void r4k_blast_scache_setup(void) 452 { 453 unsigned long sc_lsize = cpu_scache_line_size(); 454 455 if (scache_size == 0) 456 r4k_blast_scache = (void *)cache_noop; 457 else if (sc_lsize == 16) 458 r4k_blast_scache = blast_scache16; 459 else if (sc_lsize == 32) 460 r4k_blast_scache = blast_scache32; 461 else if (sc_lsize == 64) 462 r4k_blast_scache = blast_scache64; 463 else if (sc_lsize == 128) 464 r4k_blast_scache = blast_scache128; 465 } 466 467 static void (*r4k_blast_scache_node)(long node); 468 469 static void r4k_blast_scache_node_setup(void) 470 { 471 unsigned long sc_lsize = cpu_scache_line_size(); 472 473 if (current_cpu_type() != CPU_LOONGSON64) 474 r4k_blast_scache_node = (void *)cache_noop; 475 else if (sc_lsize == 16) 476 r4k_blast_scache_node = blast_scache16_node; 477 else if (sc_lsize == 32) 478 r4k_blast_scache_node = blast_scache32_node; 479 else if (sc_lsize == 64) 480 r4k_blast_scache_node = blast_scache64_node; 481 else if (sc_lsize == 128) 482 r4k_blast_scache_node = blast_scache128_node; 483 } 484 485 static inline void local_r4k___flush_cache_all(void * args) 486 { 487 switch (current_cpu_type()) { 488 case CPU_LOONGSON2EF: 489 case CPU_R4000SC: 490 case CPU_R4000MC: 491 case CPU_R4400SC: 492 case CPU_R4400MC: 493 case CPU_R10000: 494 case CPU_R12000: 495 case CPU_R14000: 496 case CPU_R16000: 497 /* 498 * These caches are inclusive caches, that is, if something 499 * is not cached in the S-cache, we know it also won't be 500 * in one of the primary caches. 501 */ 502 r4k_blast_scache(); 503 break; 504 505 case CPU_LOONGSON64: 506 /* Use get_ebase_cpunum() for both NUMA=y/n */ 507 r4k_blast_scache_node(get_ebase_cpunum() >> 2); 508 break; 509 510 case CPU_BMIPS5000: 511 r4k_blast_scache(); 512 __sync(); 513 break; 514 515 default: 516 r4k_blast_dcache(); 517 r4k_blast_icache(); 518 break; 519 } 520 } 521 522 static void r4k___flush_cache_all(void) 523 { 524 r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL); 525 } 526 527 /** 528 * has_valid_asid() - Determine if an mm already has an ASID. 529 * @mm: Memory map. 530 * @type: R4K_HIT or R4K_INDEX, type of cache op. 531 * 532 * Determines whether @mm already has an ASID on any of the CPUs which cache ops 533 * of type @type within an r4k_on_each_cpu() call will affect. If 534 * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the 535 * scope of the operation is confined to sibling CPUs, otherwise all online CPUs 536 * will need to be checked. 537 * 538 * Must be called in non-preemptive context. 539 * 540 * Returns: 1 if the CPUs affected by @type cache ops have an ASID for @mm. 541 * 0 otherwise. 542 */ 543 static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type) 544 { 545 unsigned int i; 546 const cpumask_t *mask = cpu_present_mask; 547 548 if (cpu_has_mmid) 549 return cpu_context(0, mm) != 0; 550 551 /* cpu_sibling_map[] undeclared when !CONFIG_SMP */ 552 #ifdef CONFIG_SMP 553 /* 554 * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in 555 * each foreign core, so we only need to worry about siblings. 556 * Otherwise we need to worry about all present CPUs. 557 */ 558 if (r4k_op_needs_ipi(type)) 559 mask = &cpu_sibling_map[smp_processor_id()]; 560 #endif 561 for_each_cpu(i, mask) 562 if (cpu_context(i, mm)) 563 return 1; 564 return 0; 565 } 566 567 static void r4k__flush_cache_vmap(void) 568 { 569 r4k_blast_dcache(); 570 } 571 572 static void r4k__flush_cache_vunmap(void) 573 { 574 r4k_blast_dcache(); 575 } 576 577 /* 578 * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes 579 * whole caches when vma is executable. 580 */ 581 static inline void local_r4k_flush_cache_range(void * args) 582 { 583 struct vm_area_struct *vma = args; 584 int exec = vma->vm_flags & VM_EXEC; 585 586 if (!has_valid_asid(vma->vm_mm, R4K_INDEX)) 587 return; 588 589 /* 590 * If dcache can alias, we must blast it since mapping is changing. 591 * If executable, we must ensure any dirty lines are written back far 592 * enough to be visible to icache. 593 */ 594 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) 595 r4k_blast_dcache(); 596 /* If executable, blast stale lines from icache */ 597 if (exec) 598 r4k_blast_icache(); 599 } 600 601 static void r4k_flush_cache_range(struct vm_area_struct *vma, 602 unsigned long start, unsigned long end) 603 { 604 int exec = vma->vm_flags & VM_EXEC; 605 606 if (cpu_has_dc_aliases || exec) 607 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma); 608 } 609 610 static inline void local_r4k_flush_cache_mm(void * args) 611 { 612 struct mm_struct *mm = args; 613 614 if (!has_valid_asid(mm, R4K_INDEX)) 615 return; 616 617 /* 618 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we 619 * only flush the primary caches but R1x000 behave sane ... 620 * R4000SC and R4400SC indexed S-cache ops also invalidate primary 621 * caches, so we can bail out early. 622 */ 623 if (current_cpu_type() == CPU_R4000SC || 624 current_cpu_type() == CPU_R4000MC || 625 current_cpu_type() == CPU_R4400SC || 626 current_cpu_type() == CPU_R4400MC) { 627 r4k_blast_scache(); 628 return; 629 } 630 631 r4k_blast_dcache(); 632 } 633 634 static void r4k_flush_cache_mm(struct mm_struct *mm) 635 { 636 if (!cpu_has_dc_aliases) 637 return; 638 639 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm); 640 } 641 642 struct flush_cache_page_args { 643 struct vm_area_struct *vma; 644 unsigned long addr; 645 unsigned long pfn; 646 }; 647 648 static inline void local_r4k_flush_cache_page(void *args) 649 { 650 struct flush_cache_page_args *fcp_args = args; 651 struct vm_area_struct *vma = fcp_args->vma; 652 unsigned long addr = fcp_args->addr; 653 struct page *page = pfn_to_page(fcp_args->pfn); 654 int exec = vma->vm_flags & VM_EXEC; 655 struct mm_struct *mm = vma->vm_mm; 656 int map_coherent = 0; 657 pmd_t *pmdp; 658 pte_t *ptep; 659 void *vaddr; 660 661 /* 662 * If owns no valid ASID yet, cannot possibly have gotten 663 * this page into the cache. 664 */ 665 if (!has_valid_asid(mm, R4K_HIT)) 666 return; 667 668 addr &= PAGE_MASK; 669 pmdp = pmd_off(mm, addr); 670 ptep = pte_offset_kernel(pmdp, addr); 671 672 /* 673 * If the page isn't marked valid, the page cannot possibly be 674 * in the cache. 675 */ 676 if (!(pte_present(*ptep))) 677 return; 678 679 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) 680 vaddr = NULL; 681 else { 682 /* 683 * Use kmap_coherent or kmap_atomic to do flushes for 684 * another ASID than the current one. 685 */ 686 map_coherent = (cpu_has_dc_aliases && 687 page_mapcount(page) && 688 !Page_dcache_dirty(page)); 689 if (map_coherent) 690 vaddr = kmap_coherent(page, addr); 691 else 692 vaddr = kmap_atomic(page); 693 addr = (unsigned long)vaddr; 694 } 695 696 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 697 vaddr ? r4k_blast_dcache_page(addr) : 698 r4k_blast_dcache_user_page(addr); 699 if (exec && !cpu_icache_snoops_remote_store) 700 r4k_blast_scache_page(addr); 701 } 702 if (exec) { 703 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { 704 drop_mmu_context(mm); 705 } else 706 vaddr ? r4k_blast_icache_page(addr) : 707 r4k_blast_icache_user_page(addr); 708 } 709 710 if (vaddr) { 711 if (map_coherent) 712 kunmap_coherent(); 713 else 714 kunmap_atomic(vaddr); 715 } 716 } 717 718 static void r4k_flush_cache_page(struct vm_area_struct *vma, 719 unsigned long addr, unsigned long pfn) 720 { 721 struct flush_cache_page_args args; 722 723 args.vma = vma; 724 args.addr = addr; 725 args.pfn = pfn; 726 727 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args); 728 } 729 730 static inline void local_r4k_flush_data_cache_page(void * addr) 731 { 732 r4k_blast_dcache_page((unsigned long) addr); 733 } 734 735 static void r4k_flush_data_cache_page(unsigned long addr) 736 { 737 if (in_atomic()) 738 local_r4k_flush_data_cache_page((void *)addr); 739 else 740 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page, 741 (void *) addr); 742 } 743 744 struct flush_icache_range_args { 745 unsigned long start; 746 unsigned long end; 747 unsigned int type; 748 bool user; 749 }; 750 751 static inline void __local_r4k_flush_icache_range(unsigned long start, 752 unsigned long end, 753 unsigned int type, 754 bool user) 755 { 756 if (!cpu_has_ic_fills_f_dc) { 757 if (type == R4K_INDEX || 758 (type & R4K_INDEX && end - start >= dcache_size)) { 759 r4k_blast_dcache(); 760 } else { 761 R4600_HIT_CACHEOP_WAR_IMPL; 762 if (user) 763 protected_blast_dcache_range(start, end); 764 else 765 blast_dcache_range(start, end); 766 } 767 } 768 769 if (type == R4K_INDEX || 770 (type & R4K_INDEX && end - start > icache_size)) 771 r4k_blast_icache(); 772 else { 773 switch (boot_cpu_type()) { 774 case CPU_LOONGSON2EF: 775 protected_loongson2_blast_icache_range(start, end); 776 break; 777 778 default: 779 if (user) 780 protected_blast_icache_range(start, end); 781 else 782 blast_icache_range(start, end); 783 break; 784 } 785 } 786 } 787 788 static inline void local_r4k_flush_icache_range(unsigned long start, 789 unsigned long end) 790 { 791 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, false); 792 } 793 794 static inline void local_r4k_flush_icache_user_range(unsigned long start, 795 unsigned long end) 796 { 797 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, true); 798 } 799 800 static inline void local_r4k_flush_icache_range_ipi(void *args) 801 { 802 struct flush_icache_range_args *fir_args = args; 803 unsigned long start = fir_args->start; 804 unsigned long end = fir_args->end; 805 unsigned int type = fir_args->type; 806 bool user = fir_args->user; 807 808 __local_r4k_flush_icache_range(start, end, type, user); 809 } 810 811 static void __r4k_flush_icache_range(unsigned long start, unsigned long end, 812 bool user) 813 { 814 struct flush_icache_range_args args; 815 unsigned long size, cache_size; 816 817 args.start = start; 818 args.end = end; 819 args.type = R4K_HIT | R4K_INDEX; 820 args.user = user; 821 822 /* 823 * Indexed cache ops require an SMP call. 824 * Consider if that can or should be avoided. 825 */ 826 preempt_disable(); 827 if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) { 828 /* 829 * If address-based cache ops don't require an SMP call, then 830 * use them exclusively for small flushes. 831 */ 832 size = end - start; 833 cache_size = icache_size; 834 if (!cpu_has_ic_fills_f_dc) { 835 size *= 2; 836 cache_size += dcache_size; 837 } 838 if (size <= cache_size) 839 args.type &= ~R4K_INDEX; 840 } 841 r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args); 842 preempt_enable(); 843 instruction_hazard(); 844 } 845 846 static void r4k_flush_icache_range(unsigned long start, unsigned long end) 847 { 848 return __r4k_flush_icache_range(start, end, false); 849 } 850 851 static void r4k_flush_icache_user_range(unsigned long start, unsigned long end) 852 { 853 return __r4k_flush_icache_range(start, end, true); 854 } 855 856 #ifdef CONFIG_DMA_NONCOHERENT 857 858 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) 859 { 860 /* Catch bad driver code */ 861 if (WARN_ON(size == 0)) 862 return; 863 864 preempt_disable(); 865 if (cpu_has_inclusive_pcaches) { 866 if (size >= scache_size) { 867 if (current_cpu_type() != CPU_LOONGSON64) 868 r4k_blast_scache(); 869 else 870 r4k_blast_scache_node(pa_to_nid(addr)); 871 } else { 872 blast_scache_range(addr, addr + size); 873 } 874 preempt_enable(); 875 __sync(); 876 return; 877 } 878 879 /* 880 * Either no secondary cache or the available caches don't have the 881 * subset property so we have to flush the primary caches 882 * explicitly. 883 * If we would need IPI to perform an INDEX-type operation, then 884 * we have to use the HIT-type alternative as IPI cannot be used 885 * here due to interrupts possibly being disabled. 886 */ 887 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) { 888 r4k_blast_dcache(); 889 } else { 890 R4600_HIT_CACHEOP_WAR_IMPL; 891 blast_dcache_range(addr, addr + size); 892 } 893 preempt_enable(); 894 895 bc_wback_inv(addr, size); 896 __sync(); 897 } 898 899 static void prefetch_cache_inv(unsigned long addr, unsigned long size) 900 { 901 unsigned int linesz = cpu_scache_line_size(); 902 unsigned long addr0 = addr, addr1; 903 904 addr0 &= ~(linesz - 1); 905 addr1 = (addr0 + size - 1) & ~(linesz - 1); 906 907 protected_writeback_scache_line(addr0); 908 if (likely(addr1 != addr0)) 909 protected_writeback_scache_line(addr1); 910 else 911 return; 912 913 addr0 += linesz; 914 if (likely(addr1 != addr0)) 915 protected_writeback_scache_line(addr0); 916 else 917 return; 918 919 addr1 -= linesz; 920 if (likely(addr1 > addr0)) 921 protected_writeback_scache_line(addr0); 922 } 923 924 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) 925 { 926 /* Catch bad driver code */ 927 if (WARN_ON(size == 0)) 928 return; 929 930 preempt_disable(); 931 932 if (current_cpu_type() == CPU_BMIPS5000) 933 prefetch_cache_inv(addr, size); 934 935 if (cpu_has_inclusive_pcaches) { 936 if (size >= scache_size) { 937 if (current_cpu_type() != CPU_LOONGSON64) 938 r4k_blast_scache(); 939 else 940 r4k_blast_scache_node(pa_to_nid(addr)); 941 } else { 942 /* 943 * There is no clearly documented alignment requirement 944 * for the cache instruction on MIPS processors and 945 * some processors, among them the RM5200 and RM7000 946 * QED processors will throw an address error for cache 947 * hit ops with insufficient alignment. Solved by 948 * aligning the address to cache line size. 949 */ 950 blast_inv_scache_range(addr, addr + size); 951 } 952 preempt_enable(); 953 __sync(); 954 return; 955 } 956 957 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) { 958 r4k_blast_dcache(); 959 } else { 960 R4600_HIT_CACHEOP_WAR_IMPL; 961 blast_inv_dcache_range(addr, addr + size); 962 } 963 preempt_enable(); 964 965 bc_inv(addr, size); 966 __sync(); 967 } 968 #endif /* CONFIG_DMA_NONCOHERENT */ 969 970 static void r4k_flush_icache_all(void) 971 { 972 if (cpu_has_vtag_icache) 973 r4k_blast_icache(); 974 } 975 976 struct flush_kernel_vmap_range_args { 977 unsigned long vaddr; 978 int size; 979 }; 980 981 static inline void local_r4k_flush_kernel_vmap_range_index(void *args) 982 { 983 /* 984 * Aliases only affect the primary caches so don't bother with 985 * S-caches or T-caches. 986 */ 987 r4k_blast_dcache(); 988 } 989 990 static inline void local_r4k_flush_kernel_vmap_range(void *args) 991 { 992 struct flush_kernel_vmap_range_args *vmra = args; 993 unsigned long vaddr = vmra->vaddr; 994 int size = vmra->size; 995 996 /* 997 * Aliases only affect the primary caches so don't bother with 998 * S-caches or T-caches. 999 */ 1000 R4600_HIT_CACHEOP_WAR_IMPL; 1001 blast_dcache_range(vaddr, vaddr + size); 1002 } 1003 1004 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) 1005 { 1006 struct flush_kernel_vmap_range_args args; 1007 1008 args.vaddr = (unsigned long) vaddr; 1009 args.size = size; 1010 1011 if (size >= dcache_size) 1012 r4k_on_each_cpu(R4K_INDEX, 1013 local_r4k_flush_kernel_vmap_range_index, NULL); 1014 else 1015 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range, 1016 &args); 1017 } 1018 1019 static inline void rm7k_erratum31(void) 1020 { 1021 const unsigned long ic_lsize = 32; 1022 unsigned long addr; 1023 1024 /* RM7000 erratum #31. The icache is screwed at startup. */ 1025 write_c0_taglo(0); 1026 write_c0_taghi(0); 1027 1028 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { 1029 __asm__ __volatile__ ( 1030 ".set push\n\t" 1031 ".set noreorder\n\t" 1032 ".set mips3\n\t" 1033 "cache\t%1, 0(%0)\n\t" 1034 "cache\t%1, 0x1000(%0)\n\t" 1035 "cache\t%1, 0x2000(%0)\n\t" 1036 "cache\t%1, 0x3000(%0)\n\t" 1037 "cache\t%2, 0(%0)\n\t" 1038 "cache\t%2, 0x1000(%0)\n\t" 1039 "cache\t%2, 0x2000(%0)\n\t" 1040 "cache\t%2, 0x3000(%0)\n\t" 1041 "cache\t%1, 0(%0)\n\t" 1042 "cache\t%1, 0x1000(%0)\n\t" 1043 "cache\t%1, 0x2000(%0)\n\t" 1044 "cache\t%1, 0x3000(%0)\n\t" 1045 ".set pop\n" 1046 : 1047 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill_I)); 1048 } 1049 } 1050 1051 static inline int alias_74k_erratum(struct cpuinfo_mips *c) 1052 { 1053 unsigned int imp = c->processor_id & PRID_IMP_MASK; 1054 unsigned int rev = c->processor_id & PRID_REV_MASK; 1055 int present = 0; 1056 1057 /* 1058 * Early versions of the 74K do not update the cache tags on a 1059 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG 1060 * aliases. In this case it is better to treat the cache as always 1061 * having aliases. Also disable the synonym tag update feature 1062 * where available. In this case no opportunistic tag update will 1063 * happen where a load causes a virtual address miss but a physical 1064 * address hit during a D-cache look-up. 1065 */ 1066 switch (imp) { 1067 case PRID_IMP_74K: 1068 if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) 1069 present = 1; 1070 if (rev == PRID_REV_ENCODE_332(2, 4, 0)) 1071 write_c0_config6(read_c0_config6() | MTI_CONF6_SYND); 1072 break; 1073 case PRID_IMP_1074K: 1074 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { 1075 present = 1; 1076 write_c0_config6(read_c0_config6() | MTI_CONF6_SYND); 1077 } 1078 break; 1079 default: 1080 BUG(); 1081 } 1082 1083 return present; 1084 } 1085 1086 static void b5k_instruction_hazard(void) 1087 { 1088 __sync(); 1089 __sync(); 1090 __asm__ __volatile__( 1091 " nop; nop; nop; nop; nop; nop; nop; nop\n" 1092 " nop; nop; nop; nop; nop; nop; nop; nop\n" 1093 " nop; nop; nop; nop; nop; nop; nop; nop\n" 1094 " nop; nop; nop; nop; nop; nop; nop; nop\n" 1095 : : : "memory"); 1096 } 1097 1098 static char *way_string[] = { NULL, "direct mapped", "2-way", 1099 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way", 1100 "9-way", "10-way", "11-way", "12-way", 1101 "13-way", "14-way", "15-way", "16-way", 1102 }; 1103 1104 static void probe_pcache(void) 1105 { 1106 struct cpuinfo_mips *c = ¤t_cpu_data; 1107 unsigned int config = read_c0_config(); 1108 unsigned int prid = read_c0_prid(); 1109 int has_74k_erratum = 0; 1110 unsigned long config1; 1111 unsigned int lsize; 1112 1113 switch (current_cpu_type()) { 1114 case CPU_R4600: /* QED style two way caches? */ 1115 case CPU_R4700: 1116 case CPU_R5000: 1117 case CPU_NEVADA: 1118 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1119 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1120 c->icache.ways = 2; 1121 c->icache.waybit = __ffs(icache_size/2); 1122 1123 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1124 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1125 c->dcache.ways = 2; 1126 c->dcache.waybit= __ffs(dcache_size/2); 1127 1128 c->options |= MIPS_CPU_CACHE_CDEX_P; 1129 break; 1130 1131 case CPU_R5500: 1132 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1133 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1134 c->icache.ways = 2; 1135 c->icache.waybit= 0; 1136 1137 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1138 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1139 c->dcache.ways = 2; 1140 c->dcache.waybit = 0; 1141 1142 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; 1143 break; 1144 1145 case CPU_TX49XX: 1146 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1147 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1148 c->icache.ways = 4; 1149 c->icache.waybit= 0; 1150 1151 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1152 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1153 c->dcache.ways = 4; 1154 c->dcache.waybit = 0; 1155 1156 c->options |= MIPS_CPU_CACHE_CDEX_P; 1157 c->options |= MIPS_CPU_PREFETCH; 1158 break; 1159 1160 case CPU_R4000PC: 1161 case CPU_R4000SC: 1162 case CPU_R4000MC: 1163 case CPU_R4400PC: 1164 case CPU_R4400SC: 1165 case CPU_R4400MC: 1166 case CPU_R4300: 1167 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1168 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1169 c->icache.ways = 1; 1170 c->icache.waybit = 0; /* doesn't matter */ 1171 1172 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1173 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1174 c->dcache.ways = 1; 1175 c->dcache.waybit = 0; /* does not matter */ 1176 1177 c->options |= MIPS_CPU_CACHE_CDEX_P; 1178 break; 1179 1180 case CPU_R10000: 1181 case CPU_R12000: 1182 case CPU_R14000: 1183 case CPU_R16000: 1184 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); 1185 c->icache.linesz = 64; 1186 c->icache.ways = 2; 1187 c->icache.waybit = 0; 1188 1189 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); 1190 c->dcache.linesz = 32; 1191 c->dcache.ways = 2; 1192 c->dcache.waybit = 0; 1193 1194 c->options |= MIPS_CPU_PREFETCH; 1195 break; 1196 1197 case CPU_VR4133: 1198 write_c0_config(config & ~VR41_CONF_P4K); 1199 fallthrough; 1200 case CPU_VR4131: 1201 /* Workaround for cache instruction bug of VR4131 */ 1202 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || 1203 c->processor_id == 0x0c82U) { 1204 config |= 0x00400000U; 1205 if (c->processor_id == 0x0c80U) 1206 config |= VR41_CONF_BP; 1207 write_c0_config(config); 1208 } else 1209 c->options |= MIPS_CPU_CACHE_CDEX_P; 1210 1211 icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); 1212 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1213 c->icache.ways = 2; 1214 c->icache.waybit = __ffs(icache_size/2); 1215 1216 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); 1217 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1218 c->dcache.ways = 2; 1219 c->dcache.waybit = __ffs(dcache_size/2); 1220 break; 1221 1222 case CPU_VR41XX: 1223 case CPU_VR4111: 1224 case CPU_VR4121: 1225 case CPU_VR4122: 1226 case CPU_VR4181: 1227 case CPU_VR4181A: 1228 icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); 1229 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1230 c->icache.ways = 1; 1231 c->icache.waybit = 0; /* doesn't matter */ 1232 1233 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); 1234 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1235 c->dcache.ways = 1; 1236 c->dcache.waybit = 0; /* does not matter */ 1237 1238 c->options |= MIPS_CPU_CACHE_CDEX_P; 1239 break; 1240 1241 case CPU_RM7000: 1242 rm7k_erratum31(); 1243 1244 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1245 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1246 c->icache.ways = 4; 1247 c->icache.waybit = __ffs(icache_size / c->icache.ways); 1248 1249 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1250 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1251 c->dcache.ways = 4; 1252 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); 1253 1254 c->options |= MIPS_CPU_CACHE_CDEX_P; 1255 c->options |= MIPS_CPU_PREFETCH; 1256 break; 1257 1258 case CPU_LOONGSON2EF: 1259 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1260 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1261 if (prid & 0x3) 1262 c->icache.ways = 4; 1263 else 1264 c->icache.ways = 2; 1265 c->icache.waybit = 0; 1266 1267 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1268 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1269 if (prid & 0x3) 1270 c->dcache.ways = 4; 1271 else 1272 c->dcache.ways = 2; 1273 c->dcache.waybit = 0; 1274 break; 1275 1276 case CPU_LOONGSON64: 1277 config1 = read_c0_config1(); 1278 lsize = (config1 >> 19) & 7; 1279 if (lsize) 1280 c->icache.linesz = 2 << lsize; 1281 else 1282 c->icache.linesz = 0; 1283 c->icache.sets = 64 << ((config1 >> 22) & 7); 1284 c->icache.ways = 1 + ((config1 >> 16) & 7); 1285 icache_size = c->icache.sets * 1286 c->icache.ways * 1287 c->icache.linesz; 1288 c->icache.waybit = 0; 1289 1290 lsize = (config1 >> 10) & 7; 1291 if (lsize) 1292 c->dcache.linesz = 2 << lsize; 1293 else 1294 c->dcache.linesz = 0; 1295 c->dcache.sets = 64 << ((config1 >> 13) & 7); 1296 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1297 dcache_size = c->dcache.sets * 1298 c->dcache.ways * 1299 c->dcache.linesz; 1300 c->dcache.waybit = 0; 1301 if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >= 1302 (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) || 1303 (c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R) 1304 c->options |= MIPS_CPU_PREFETCH; 1305 break; 1306 1307 case CPU_CAVIUM_OCTEON3: 1308 /* For now lie about the number of ways. */ 1309 c->icache.linesz = 128; 1310 c->icache.sets = 16; 1311 c->icache.ways = 8; 1312 c->icache.flags |= MIPS_CACHE_VTAG; 1313 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; 1314 1315 c->dcache.linesz = 128; 1316 c->dcache.ways = 8; 1317 c->dcache.sets = 8; 1318 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; 1319 c->options |= MIPS_CPU_PREFETCH; 1320 break; 1321 1322 default: 1323 if (!(config & MIPS_CONF_M)) 1324 panic("Don't know how to probe P-caches on this cpu."); 1325 1326 /* 1327 * So we seem to be a MIPS32 or MIPS64 CPU 1328 * So let's probe the I-cache ... 1329 */ 1330 config1 = read_c0_config1(); 1331 1332 lsize = (config1 >> 19) & 7; 1333 1334 /* IL == 7 is reserved */ 1335 if (lsize == 7) 1336 panic("Invalid icache line size"); 1337 1338 c->icache.linesz = lsize ? 2 << lsize : 0; 1339 1340 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); 1341 c->icache.ways = 1 + ((config1 >> 16) & 7); 1342 1343 icache_size = c->icache.sets * 1344 c->icache.ways * 1345 c->icache.linesz; 1346 c->icache.waybit = __ffs(icache_size/c->icache.ways); 1347 1348 if (config & MIPS_CONF_VI) 1349 c->icache.flags |= MIPS_CACHE_VTAG; 1350 1351 /* 1352 * Now probe the MIPS32 / MIPS64 data cache. 1353 */ 1354 c->dcache.flags = 0; 1355 1356 lsize = (config1 >> 10) & 7; 1357 1358 /* DL == 7 is reserved */ 1359 if (lsize == 7) 1360 panic("Invalid dcache line size"); 1361 1362 c->dcache.linesz = lsize ? 2 << lsize : 0; 1363 1364 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); 1365 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1366 1367 dcache_size = c->dcache.sets * 1368 c->dcache.ways * 1369 c->dcache.linesz; 1370 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); 1371 1372 c->options |= MIPS_CPU_PREFETCH; 1373 break; 1374 } 1375 1376 /* 1377 * Processor configuration sanity check for the R4000SC erratum 1378 * #5. With page sizes larger than 32kB there is no possibility 1379 * to get a VCE exception anymore so we don't care about this 1380 * misconfiguration. The case is rather theoretical anyway; 1381 * presumably no vendor is shipping his hardware in the "bad" 1382 * configuration. 1383 */ 1384 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 && 1385 (prid & PRID_REV_MASK) < PRID_REV_R4400 && 1386 !(config & CONF_SC) && c->icache.linesz != 16 && 1387 PAGE_SIZE <= 0x8000) 1388 panic("Improper R4000SC processor configuration detected"); 1389 1390 /* compute a couple of other cache variables */ 1391 c->icache.waysize = icache_size / c->icache.ways; 1392 c->dcache.waysize = dcache_size / c->dcache.ways; 1393 1394 c->icache.sets = c->icache.linesz ? 1395 icache_size / (c->icache.linesz * c->icache.ways) : 0; 1396 c->dcache.sets = c->dcache.linesz ? 1397 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; 1398 1399 /* 1400 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way 1401 * virtually indexed so normally would suffer from aliases. So 1402 * normally they'd suffer from aliases but magic in the hardware deals 1403 * with that for us so we don't need to take care ourselves. 1404 */ 1405 switch (current_cpu_type()) { 1406 case CPU_20KC: 1407 case CPU_25KF: 1408 case CPU_I6400: 1409 case CPU_I6500: 1410 case CPU_SB1: 1411 case CPU_SB1A: 1412 c->dcache.flags |= MIPS_CACHE_PINDEX; 1413 break; 1414 1415 case CPU_R10000: 1416 case CPU_R12000: 1417 case CPU_R14000: 1418 case CPU_R16000: 1419 break; 1420 1421 case CPU_74K: 1422 case CPU_1074K: 1423 has_74k_erratum = alias_74k_erratum(c); 1424 fallthrough; 1425 case CPU_M14KC: 1426 case CPU_M14KEC: 1427 case CPU_24K: 1428 case CPU_34K: 1429 case CPU_1004K: 1430 case CPU_INTERAPTIV: 1431 case CPU_P5600: 1432 case CPU_PROAPTIV: 1433 case CPU_M5150: 1434 case CPU_QEMU_GENERIC: 1435 case CPU_P6600: 1436 case CPU_M6250: 1437 if (!(read_c0_config7() & MIPS_CONF7_IAR) && 1438 (c->icache.waysize > PAGE_SIZE)) 1439 c->icache.flags |= MIPS_CACHE_ALIASES; 1440 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) { 1441 /* 1442 * Effectively physically indexed dcache, 1443 * thus no virtual aliases. 1444 */ 1445 c->dcache.flags |= MIPS_CACHE_PINDEX; 1446 break; 1447 } 1448 fallthrough; 1449 default: 1450 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) 1451 c->dcache.flags |= MIPS_CACHE_ALIASES; 1452 } 1453 1454 /* Physically indexed caches don't suffer from virtual aliasing */ 1455 if (c->dcache.flags & MIPS_CACHE_PINDEX) 1456 c->dcache.flags &= ~MIPS_CACHE_ALIASES; 1457 1458 /* 1459 * In systems with CM the icache fills from L2 or closer caches, and 1460 * thus sees remote stores without needing to write them back any 1461 * further than that. 1462 */ 1463 if (mips_cm_present()) 1464 c->icache.flags |= MIPS_IC_SNOOPS_REMOTE; 1465 1466 switch (current_cpu_type()) { 1467 case CPU_20KC: 1468 /* 1469 * Some older 20Kc chips doesn't have the 'VI' bit in 1470 * the config register. 1471 */ 1472 c->icache.flags |= MIPS_CACHE_VTAG; 1473 break; 1474 1475 case CPU_ALCHEMY: 1476 case CPU_I6400: 1477 case CPU_I6500: 1478 c->icache.flags |= MIPS_CACHE_IC_F_DC; 1479 break; 1480 1481 case CPU_BMIPS5000: 1482 c->icache.flags |= MIPS_CACHE_IC_F_DC; 1483 /* Cache aliases are handled in hardware; allow HIGHMEM */ 1484 c->dcache.flags &= ~MIPS_CACHE_ALIASES; 1485 break; 1486 1487 case CPU_LOONGSON2EF: 1488 /* 1489 * LOONGSON2 has 4 way icache, but when using indexed cache op, 1490 * one op will act on all 4 ways 1491 */ 1492 c->icache.ways = 1; 1493 } 1494 1495 pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", 1496 icache_size >> 10, 1497 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", 1498 way_string[c->icache.ways], c->icache.linesz); 1499 1500 pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", 1501 dcache_size >> 10, way_string[c->dcache.ways], 1502 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", 1503 (c->dcache.flags & MIPS_CACHE_ALIASES) ? 1504 "cache aliases" : "no aliases", 1505 c->dcache.linesz); 1506 } 1507 1508 static void probe_vcache(void) 1509 { 1510 struct cpuinfo_mips *c = ¤t_cpu_data; 1511 unsigned int config2, lsize; 1512 1513 if (current_cpu_type() != CPU_LOONGSON64) 1514 return; 1515 1516 config2 = read_c0_config2(); 1517 if ((lsize = ((config2 >> 20) & 15))) 1518 c->vcache.linesz = 2 << lsize; 1519 else 1520 c->vcache.linesz = lsize; 1521 1522 c->vcache.sets = 64 << ((config2 >> 24) & 15); 1523 c->vcache.ways = 1 + ((config2 >> 16) & 15); 1524 1525 vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz; 1526 1527 c->vcache.waybit = 0; 1528 c->vcache.waysize = vcache_size / c->vcache.ways; 1529 1530 pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n", 1531 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz); 1532 } 1533 1534 /* 1535 * If you even _breathe_ on this function, look at the gcc output and make sure 1536 * it does not pop things on and off the stack for the cache sizing loop that 1537 * executes in KSEG1 space or else you will crash and burn badly. You have 1538 * been warned. 1539 */ 1540 static int probe_scache(void) 1541 { 1542 unsigned long flags, addr, begin, end, pow2; 1543 unsigned int config = read_c0_config(); 1544 struct cpuinfo_mips *c = ¤t_cpu_data; 1545 1546 if (config & CONF_SC) 1547 return 0; 1548 1549 begin = (unsigned long) &_stext; 1550 begin &= ~((4 * 1024 * 1024) - 1); 1551 end = begin + (4 * 1024 * 1024); 1552 1553 /* 1554 * This is such a bitch, you'd think they would make it easy to do 1555 * this. Away you daemons of stupidity! 1556 */ 1557 local_irq_save(flags); 1558 1559 /* Fill each size-multiple cache line with a valid tag. */ 1560 pow2 = (64 * 1024); 1561 for (addr = begin; addr < end; addr = (begin + pow2)) { 1562 unsigned long *p = (unsigned long *) addr; 1563 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ 1564 pow2 <<= 1; 1565 } 1566 1567 /* Load first line with zero (therefore invalid) tag. */ 1568 write_c0_taglo(0); 1569 write_c0_taghi(0); 1570 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ 1571 cache_op(Index_Store_Tag_I, begin); 1572 cache_op(Index_Store_Tag_D, begin); 1573 cache_op(Index_Store_Tag_SD, begin); 1574 1575 /* Now search for the wrap around point. */ 1576 pow2 = (128 * 1024); 1577 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { 1578 cache_op(Index_Load_Tag_SD, addr); 1579 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ 1580 if (!read_c0_taglo()) 1581 break; 1582 pow2 <<= 1; 1583 } 1584 local_irq_restore(flags); 1585 addr -= begin; 1586 1587 scache_size = addr; 1588 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); 1589 c->scache.ways = 1; 1590 c->scache.waybit = 0; /* does not matter */ 1591 1592 return 1; 1593 } 1594 1595 static void loongson2_sc_init(void) 1596 { 1597 struct cpuinfo_mips *c = ¤t_cpu_data; 1598 1599 scache_size = 512*1024; 1600 c->scache.linesz = 32; 1601 c->scache.ways = 4; 1602 c->scache.waybit = 0; 1603 c->scache.waysize = scache_size / (c->scache.ways); 1604 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 1605 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1606 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1607 1608 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1609 } 1610 1611 static void loongson3_sc_init(void) 1612 { 1613 struct cpuinfo_mips *c = ¤t_cpu_data; 1614 unsigned int config2, lsize; 1615 1616 config2 = read_c0_config2(); 1617 lsize = (config2 >> 4) & 15; 1618 if (lsize) 1619 c->scache.linesz = 2 << lsize; 1620 else 1621 c->scache.linesz = 0; 1622 c->scache.sets = 64 << ((config2 >> 8) & 15); 1623 c->scache.ways = 1 + (config2 & 15); 1624 1625 /* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */ 1626 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R) 1627 c->scache.sets *= 2; 1628 else 1629 c->scache.sets *= 4; 1630 1631 scache_size = c->scache.sets * c->scache.ways * c->scache.linesz; 1632 1633 c->scache.waybit = 0; 1634 c->scache.waysize = scache_size / c->scache.ways; 1635 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1636 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1637 if (scache_size) 1638 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1639 return; 1640 } 1641 1642 extern int r5k_sc_init(void); 1643 extern int rm7k_sc_init(void); 1644 extern int mips_sc_init(void); 1645 1646 static void setup_scache(void) 1647 { 1648 struct cpuinfo_mips *c = ¤t_cpu_data; 1649 unsigned int config = read_c0_config(); 1650 int sc_present = 0; 1651 1652 /* 1653 * Do the probing thing on R4000SC and R4400SC processors. Other 1654 * processors don't have a S-cache that would be relevant to the 1655 * Linux memory management. 1656 */ 1657 switch (current_cpu_type()) { 1658 case CPU_R4000SC: 1659 case CPU_R4000MC: 1660 case CPU_R4400SC: 1661 case CPU_R4400MC: 1662 sc_present = run_uncached(probe_scache); 1663 if (sc_present) 1664 c->options |= MIPS_CPU_CACHE_CDEX_S; 1665 break; 1666 1667 case CPU_R10000: 1668 case CPU_R12000: 1669 case CPU_R14000: 1670 case CPU_R16000: 1671 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); 1672 c->scache.linesz = 64 << ((config >> 13) & 1); 1673 c->scache.ways = 2; 1674 c->scache.waybit= 0; 1675 sc_present = 1; 1676 break; 1677 1678 case CPU_R5000: 1679 case CPU_NEVADA: 1680 #ifdef CONFIG_R5000_CPU_SCACHE 1681 r5k_sc_init(); 1682 #endif 1683 return; 1684 1685 case CPU_RM7000: 1686 #ifdef CONFIG_RM7000_CPU_SCACHE 1687 rm7k_sc_init(); 1688 #endif 1689 return; 1690 1691 case CPU_LOONGSON2EF: 1692 loongson2_sc_init(); 1693 return; 1694 1695 case CPU_LOONGSON64: 1696 loongson3_sc_init(); 1697 return; 1698 1699 case CPU_CAVIUM_OCTEON3: 1700 /* don't need to worry about L2, fully coherent */ 1701 return; 1702 1703 default: 1704 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 1705 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 1706 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 | 1707 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 1708 #ifdef CONFIG_MIPS_CPU_SCACHE 1709 if (mips_sc_init ()) { 1710 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; 1711 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", 1712 scache_size >> 10, 1713 way_string[c->scache.ways], c->scache.linesz); 1714 1715 if (current_cpu_type() == CPU_BMIPS5000) 1716 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1717 } 1718 1719 #else 1720 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) 1721 panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); 1722 #endif 1723 return; 1724 } 1725 sc_present = 0; 1726 } 1727 1728 if (!sc_present) 1729 return; 1730 1731 /* compute a couple of other cache variables */ 1732 c->scache.waysize = scache_size / c->scache.ways; 1733 1734 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 1735 1736 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1737 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1738 1739 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1740 } 1741 1742 void au1x00_fixup_config_od(void) 1743 { 1744 /* 1745 * c0_config.od (bit 19) was write only (and read as 0) 1746 * on the early revisions of Alchemy SOCs. It disables the bus 1747 * transaction overlapping and needs to be set to fix various errata. 1748 */ 1749 switch (read_c0_prid()) { 1750 case 0x00030100: /* Au1000 DA */ 1751 case 0x00030201: /* Au1000 HA */ 1752 case 0x00030202: /* Au1000 HB */ 1753 case 0x01030200: /* Au1500 AB */ 1754 /* 1755 * Au1100 errata actually keeps silence about this bit, so we set it 1756 * just in case for those revisions that require it to be set according 1757 * to the (now gone) cpu table. 1758 */ 1759 case 0x02030200: /* Au1100 AB */ 1760 case 0x02030201: /* Au1100 BA */ 1761 case 0x02030202: /* Au1100 BC */ 1762 set_c0_config(1 << 19); 1763 break; 1764 } 1765 } 1766 1767 /* CP0 hazard avoidance. */ 1768 #define NXP_BARRIER() \ 1769 __asm__ __volatile__( \ 1770 ".set noreorder\n\t" \ 1771 "nop; nop; nop; nop; nop; nop;\n\t" \ 1772 ".set reorder\n\t") 1773 1774 static void nxp_pr4450_fixup_config(void) 1775 { 1776 unsigned long config0; 1777 1778 config0 = read_c0_config(); 1779 1780 /* clear all three cache coherency fields */ 1781 config0 &= ~(0x7 | (7 << 25) | (7 << 28)); 1782 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | 1783 ((_page_cachable_default >> _CACHE_SHIFT) << 25) | 1784 ((_page_cachable_default >> _CACHE_SHIFT) << 28)); 1785 write_c0_config(config0); 1786 NXP_BARRIER(); 1787 } 1788 1789 static int cca = -1; 1790 1791 static int __init cca_setup(char *str) 1792 { 1793 get_option(&str, &cca); 1794 1795 return 0; 1796 } 1797 1798 early_param("cca", cca_setup); 1799 1800 static void coherency_setup(void) 1801 { 1802 if (cca < 0 || cca > 7) 1803 cca = read_c0_config() & CONF_CM_CMASK; 1804 _page_cachable_default = cca << _CACHE_SHIFT; 1805 1806 pr_debug("Using cache attribute %d\n", cca); 1807 change_c0_config(CONF_CM_CMASK, cca); 1808 1809 /* 1810 * c0_status.cu=0 specifies that updates by the sc instruction use 1811 * the coherency mode specified by the TLB; 1 means cachable 1812 * coherent update on write will be used. Not all processors have 1813 * this bit and; some wire it to zero, others like Toshiba had the 1814 * silly idea of putting something else there ... 1815 */ 1816 switch (current_cpu_type()) { 1817 case CPU_R4000PC: 1818 case CPU_R4000SC: 1819 case CPU_R4000MC: 1820 case CPU_R4400PC: 1821 case CPU_R4400SC: 1822 case CPU_R4400MC: 1823 clear_c0_config(CONF_CU); 1824 break; 1825 /* 1826 * We need to catch the early Alchemy SOCs with 1827 * the write-only co_config.od bit and set it back to one on: 1828 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB 1829 */ 1830 case CPU_ALCHEMY: 1831 au1x00_fixup_config_od(); 1832 break; 1833 1834 case PRID_IMP_PR4450: 1835 nxp_pr4450_fixup_config(); 1836 break; 1837 } 1838 } 1839 1840 static void r4k_cache_error_setup(void) 1841 { 1842 extern char __weak except_vec2_generic; 1843 extern char __weak except_vec2_sb1; 1844 1845 switch (current_cpu_type()) { 1846 case CPU_SB1: 1847 case CPU_SB1A: 1848 set_uncached_handler(0x100, &except_vec2_sb1, 0x80); 1849 break; 1850 1851 default: 1852 set_uncached_handler(0x100, &except_vec2_generic, 0x80); 1853 break; 1854 } 1855 } 1856 1857 void r4k_cache_init(void) 1858 { 1859 extern void build_clear_page(void); 1860 extern void build_copy_page(void); 1861 struct cpuinfo_mips *c = ¤t_cpu_data; 1862 1863 probe_pcache(); 1864 probe_vcache(); 1865 setup_scache(); 1866 1867 r4k_blast_dcache_page_setup(); 1868 r4k_blast_dcache_page_indexed_setup(); 1869 r4k_blast_dcache_setup(); 1870 r4k_blast_icache_page_setup(); 1871 r4k_blast_icache_page_indexed_setup(); 1872 r4k_blast_icache_setup(); 1873 r4k_blast_scache_page_setup(); 1874 r4k_blast_scache_page_indexed_setup(); 1875 r4k_blast_scache_setup(); 1876 r4k_blast_scache_node_setup(); 1877 #ifdef CONFIG_EVA 1878 r4k_blast_dcache_user_page_setup(); 1879 r4k_blast_icache_user_page_setup(); 1880 #endif 1881 1882 /* 1883 * Some MIPS32 and MIPS64 processors have physically indexed caches. 1884 * This code supports virtually indexed processors and will be 1885 * unnecessarily inefficient on physically indexed processors. 1886 */ 1887 if (c->dcache.linesz && cpu_has_dc_aliases) 1888 shm_align_mask = max_t( unsigned long, 1889 c->dcache.sets * c->dcache.linesz - 1, 1890 PAGE_SIZE - 1); 1891 else 1892 shm_align_mask = PAGE_SIZE-1; 1893 1894 __flush_cache_vmap = r4k__flush_cache_vmap; 1895 __flush_cache_vunmap = r4k__flush_cache_vunmap; 1896 1897 flush_cache_all = cache_noop; 1898 __flush_cache_all = r4k___flush_cache_all; 1899 flush_cache_mm = r4k_flush_cache_mm; 1900 flush_cache_page = r4k_flush_cache_page; 1901 flush_cache_range = r4k_flush_cache_range; 1902 1903 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; 1904 1905 flush_icache_all = r4k_flush_icache_all; 1906 local_flush_data_cache_page = local_r4k_flush_data_cache_page; 1907 flush_data_cache_page = r4k_flush_data_cache_page; 1908 flush_icache_range = r4k_flush_icache_range; 1909 local_flush_icache_range = local_r4k_flush_icache_range; 1910 __flush_icache_user_range = r4k_flush_icache_user_range; 1911 __local_flush_icache_user_range = local_r4k_flush_icache_user_range; 1912 1913 #ifdef CONFIG_DMA_NONCOHERENT 1914 if (dma_default_coherent) { 1915 _dma_cache_wback_inv = (void *)cache_noop; 1916 _dma_cache_wback = (void *)cache_noop; 1917 _dma_cache_inv = (void *)cache_noop; 1918 } else { 1919 _dma_cache_wback_inv = r4k_dma_cache_wback_inv; 1920 _dma_cache_wback = r4k_dma_cache_wback_inv; 1921 _dma_cache_inv = r4k_dma_cache_inv; 1922 } 1923 #endif /* CONFIG_DMA_NONCOHERENT */ 1924 1925 build_clear_page(); 1926 build_copy_page(); 1927 1928 /* 1929 * We want to run CMP kernels on core with and without coherent 1930 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether 1931 * or not to flush caches. 1932 */ 1933 local_r4k___flush_cache_all(NULL); 1934 1935 coherency_setup(); 1936 board_cache_error_setup = r4k_cache_error_setup; 1937 1938 /* 1939 * Per-CPU overrides 1940 */ 1941 switch (current_cpu_type()) { 1942 case CPU_BMIPS4350: 1943 case CPU_BMIPS4380: 1944 /* No IPI is needed because all CPUs share the same D$ */ 1945 flush_data_cache_page = r4k_blast_dcache_page; 1946 break; 1947 case CPU_BMIPS5000: 1948 /* We lose our superpowers if L2 is disabled */ 1949 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT) 1950 break; 1951 1952 /* I$ fills from D$ just by emptying the write buffers */ 1953 flush_cache_page = (void *)b5k_instruction_hazard; 1954 flush_cache_range = (void *)b5k_instruction_hazard; 1955 local_flush_data_cache_page = (void *)b5k_instruction_hazard; 1956 flush_data_cache_page = (void *)b5k_instruction_hazard; 1957 flush_icache_range = (void *)b5k_instruction_hazard; 1958 local_flush_icache_range = (void *)b5k_instruction_hazard; 1959 1960 1961 /* Optimization: an L2 flush implicitly flushes the L1 */ 1962 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES; 1963 break; 1964 case CPU_LOONGSON64: 1965 /* Loongson-3 maintains cache coherency by hardware */ 1966 __flush_cache_all = cache_noop; 1967 __flush_cache_vmap = cache_noop; 1968 __flush_cache_vunmap = cache_noop; 1969 __flush_kernel_vmap_range = (void *)cache_noop; 1970 flush_cache_mm = (void *)cache_noop; 1971 flush_cache_page = (void *)cache_noop; 1972 flush_cache_range = (void *)cache_noop; 1973 flush_icache_all = (void *)cache_noop; 1974 flush_data_cache_page = (void *)cache_noop; 1975 local_flush_data_cache_page = (void *)cache_noop; 1976 break; 1977 } 1978 } 1979 1980 static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd, 1981 void *v) 1982 { 1983 switch (cmd) { 1984 case CPU_PM_ENTER_FAILED: 1985 case CPU_PM_EXIT: 1986 coherency_setup(); 1987 break; 1988 } 1989 1990 return NOTIFY_OK; 1991 } 1992 1993 static struct notifier_block r4k_cache_pm_notifier_block = { 1994 .notifier_call = r4k_cache_pm_notifier, 1995 }; 1996 1997 int __init r4k_cache_init_pm(void) 1998 { 1999 return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block); 2000 } 2001 arch_initcall(r4k_cache_init_pm); 2002